BS EN 16602-60-02-2014 Space product assurance ASIC and FPGA development《航天产品保证 ASIC和FPGA开发》.pdf

《BS EN 16602-60-02-2014 Space product assurance ASIC and FPGA development《航天产品保证 ASIC和FPGA开发》.pdf》由会员分享，可在线阅读，更多相关《BS EN 16602-60-02-2014 Space product assurance ASIC and FPGA development《航天产品保证 ASIC和FPGA开发》.pdf（66页珍藏版）》请在麦多课文档分享上搜索。

1、BSI Standards PublicationBS EN 16602-60-02:2014Space product assurance ASIC and FPGA developmentBS EN 16602-60-02:2014 BRITISH STANDARDNational forewordThis British Standard is the UK implementation of EN 16602-60-02:2014.The UK participation in its preparation was entrusted to TechnicalCommittee AC

2、E/68, Space systems and operations.A list of organizations represented on this committee can be obtained on request to its secretary.This publication does not purport to include all the necessary provisions of a contract. Users are responsible for its correct application. The British Standards Insti

3、tution 2014.Published by BSI Standards Limited 2014ISBN 978 0 580 84273 3 ICS 49.140 Compliance with a British Standard cannot confer immunity from legal obligations.This British Standard was published under the authority of theStandards Policy and Strategy Committee on 30 September 2014.Amendments/

4、corrigenda issued since publicationDate T e x t a f f e c t e dEUROPEAN STANDARD NORME EUROPENNE EUROPISCHE NORM EN 16602-60-02 September 2014 ICS 49.140 English version Space product assurance - ASIC and FPGA development Assurance produit des projets spatiaux - dveloppement des ASIC et FPGA Raumfah

5、rtproduktsicherung - Entwicklung von ASIG und FPGA This European Standard was approved by CEN on 13 March 2014. CEN and CENELEC members are bound to comply with the CEN/CENELEC Internal Regulations which stipulate the conditions for giving this European Standard the status of a national standard wit

6、hout any alteration. Up-to-date lists and bibliographical references concerning such national standards may be obtained on application to the CEN-CENELEC Management Centre or to any CEN and CENELEC member. This European Standard exists in three official versions (English, French, German). A version

7、in any other language made by translation under the responsibility of a CEN and CENELEC member into its own language and notified to the CEN-CENELEC Management Centre has the same status as the official versions. CEN and CENELEC members are the national standards bodies and national electrotechnical

8、 committees of Austria, Belgium, Bulgaria, Croatia, Cyprus, Czech Republic, Denmark, Estonia, Finland, Former Yugoslav Republic of Macedonia, France, Germany, Greece, Hungary, Iceland, Ireland, Italy, Latvia, Lithuania, Luxembourg, Malta, Netherlands, Norway, Poland, Portugal, Romania, Slovakia, Slo

9、venia, Spain, Sweden, Switzerland, Turkey and United Kingdom. CEN-CENELEC Management Centre: Avenue Marnix 17, B-1000 Brussels 2014 CEN/CENELEC All rights of exploitation in any form and by any means reserved worldwide for CEN national Members and for CENELEC Members. Ref. No. EN 16602-60-02:2014 EB

10、S EN 16602-60-02:2014Table of contents Foreword 5 Introduction 6 1 Scope . 7 2 Normative references . 8 3 Terms, definitions and abbreviated terms 9 3.1 Terms from other standards 9 3.2 Terms specific to the present standard . 9 3.3 Abbreviated terms. 12 4 ASIC and FPGA programme management . 14 4.1

11、 General . 14 4.1.1 Introduction . 14 4.1.2 Organization 14 4.1.3 Planning 14 4.2 ASIC and FPGA control plan 14 4.3 Management planning tools 15 4.3.1 ASIC and FPGA development plan . 15 4.3.2 Verification plan 15 4.3.3 Design validation plan . 15 4.4 Experience summary report 15 5 ASIC and FPGA eng

12、ineering . 16 5.1 Introduction . 16 5.2 General requirements . 16 5.3 Definition phase 19 5.3.1 Introduction . 19 5.3.2 General requirements . 19 5.3.3 Feasibility and risk assessment . 19 5.3.4 ASIC and FPGA development plan . 20 5.3.5 System requirements review . 20 5.4 Architectural design 22 5.4

13、.1 General requirements . 22 5.4.2 Architecture definition 22 EN 16602-60-02:2014 (E)BS EN 16602-60-02:20145.4.3 Verification plan 23 5.4.4 Architecture verification and optimization 23 5.4.5 Preliminary data sheet 24 5.4.6 Preliminary design review . 24 5.5 Detailed design . 24 5.5.1 Introduction .

14、 24 5.5.2 General requirements . 25 5.5.3 Design entry 25 5.5.4 Netlist generation 26 5.5.5 Netlist verification 27 5.5.6 Updated data sheet . 28 5.5.7 Detailed design review 28 5.6 Layout . 29 5.6.1 General requirements . 29 5.6.2 Layout generation . 29 5.6.3 Layout verification . 30 5.6.4 Design v

15、alidation plan . 31 5.6.5 Updated data sheet . 31 5.6.6 Draft detail specification 31 5.6.7 Critical design review 31 5.7 Prototype implementation . 32 5.7.1 Introduction . 32 5.7.2 Production and test . 32 5.8 Design validation and release . 33 5.8.1 Design validation . 33 5.8.2 Radiation test perf

16、ormance . 33 5.8.3 Design release and FM production preparation . 34 5.8.4 Experience summary report 34 5.8.5 Final versions of application and procurement documents 34 5.8.6 Qualification and acceptance review . 35 6 Quality assurance system . 36 6.1 General . 36 6.2 Review meetings 36 6.3 Risk ass

17、essment and risk management 38 7 Development documentation 39 7.1 General . 39 7.2 Management documentation 39 EN 16602-60-02:2014 (E)BS EN 16602-60-02:20147.3 Design documentation 40 7.3.1 General . 40 7.3.2 Definition phase documentation 42 7.3.3 Architectural design documentation 42 7.3.4 Detaile

18、d design documentation . 42 7.3.5 Layout documentation . 43 7.3.6 Design validation documentation . 43 7.4 Application and procurement documents 43 7.4.1 Data sheet 43 7.4.2 Application note 43 7.4.3 Detail specification 44 8 Deliverables 45 8.1 General . 45 8.2 Deliverable items 45 Annex A (normati

19、ve) ASIC and FPGA control plan (ACP) DRD 46 Annex B (normative) ASIC and FPGA development plan (ADP) DRD . 48 Annex C (normative) ASIC and FPGA requirements specification (ARS) DRD 50 Annex D (normative) Feasibility and risk assessment report (FRA) - DRD . 52 Annex E (normative) Verification plan (V

20、P) DRD . 53 Annex F (normative) Design validation plan (DVP) DRD 54 Annex G (normative) Data sheet DRD. 55 Annex H (normative) Detail specification (DS) DRD . 57 Annex I (normative) Experience summary report DRD 59 Annex J (informative) Document requirements list and configuration items to be delive

21、red . 60 Bibliography . 61 Figures Figure 5-1: Development flow (example) 17 Figure 7-1: Design documentation . 41 Tables Table J-1 : Deliverables of the ASIC and FPGA development 60 EN 16602-60-02:2014 (E)BS EN 16602-60-02:2014Foreword This document (EN 16602-60-02:2014) has been prepared by Techni

22、cal Committee CEN/CLC/TC 5 “Space”, the secretariat of which is held by DIN. This standard (EN 16602-60-02:2014) originates from ECSS-Q-ST-60-02C. This European Standard shall be given the status of a national standard, either by publication of an identical text or by endorsement, at the latest by M

23、arch 2015, and conflicting national standards shall be withdrawn at the latest by March 2015. Attention is drawn to the possibility that some of the elements of this document may be the subject of patent rights. CEN and/or CENELEC shall not be held responsible for identifying any or all such patent

24、rights. This document has been prepared under a mandate given to CEN by the European Commission and the European Free Trade Association. This document has been developed to cover specifically space systems and has therefore precedence over any EN covering the same scope but with a wider domain of ap

25、plicability (e.g. : aerospace). According to the CEN-CENELEC Internal Regulations, the national standards organizations of the following countries are bound to implement this European Standard: Austria, Belgium, Bulgaria, Croatia, Cyprus, Czech Republic, Denmark, Estonia, Finland, Former Yugoslav Re

26、public of Macedonia, France, Germany, Greece, Hungary, Iceland, Ireland, Italy, Latvia, Lithuania, Luxembourg, Malta, Netherlands, Norway, Poland, Portugal, Romania, Slovakia, Slovenia, Spain, Sweden, Switzerland, Turkey and the United Kingdom. EN 16602-60-02:2014 (E)BS EN 16602-60-02:2014Introducti

27、on The added responsibilities of developing custom designed devices, as opposed to using off-the-shelf components, make certain management activities crucial to the success of the procurement programme. This was already considered by the applicable standard for “Space product assurance - EEE compone

28、nts”, ECSS-Q-ST-60 that classifies custom designed devices, such as ASIC components, under “Specific components”, for which particular requirements are applicable. The supplier accepts requirements for the development of custom designed components within the boundaries of this standard based on the

29、requirements of the system and its elements, and takes into consideration the operational and environmental requirements of the programme. The supplier implements those requirements into a system which enables to control for instance the technology selection, design, synthesis and simulation, layout

30、 and design validation in a schedule compatible with his requirements, and in a cost-efficient way. EN 16602-60-02:2014 (E)BS EN 16602-60-02:20141 Scope This Standard defines a comprehensive set of requirements for the user development of digital, analog and mixed analog-digital custom designed inte

31、grated circuits, such as application specific integrated circuits (ASICs) and field programmable gate arrays (FPGAs). The user development includes all activities beginning with setting initial requirements and ending with the validation and release of prototype devices. This Standard is aimed at en

32、suring that the custom designed components used in space projects meet their requirements in terms of functionality, quality, reliability, schedule and cost. The support of appropriate planning and risk management is essential to ensure that each stage of the development activity is consolidated bef

33、ore starting the subsequent one and to minimize or avoid additional iterations. For the development of standard devices, such as application specific standard products (ASSPs) and IP cores, and devices which implement safety related applications, additional requirements can be included which are not

34、 in the scope of this document. The principal clauses of this Standard correspond to the main concurrent activities of a circuit development programme. These include: ASIC and FPGA programme management, ASIC and FPGA engineering, ASIC and FPGA quality assurance. The provisions of this document apply

35、 to all actors involved in all levels in the realization of space segment hardware and its interfaces. This standard may be tailored for the specific characteristics and constraints of a space project, in accordance with ECSS-S-ST-00. EN 16602-60-02:2014 (E)BS EN 16602-60-02:20142 Normative referenc

36、es The following normative documents contain provisions which, through reference in this text, constitute provisions of this ECSS Standard. For dated references, subsequent amendments to, or revisions of any of these publications do not apply. However, parties to agreements based on this ECSS Standa

37、rd are encouraged to investigate the possibility of applying the most recent editions of the normative documents indicated below. For undated references the latest edition of the publication referred to applies. EN reference Reference in text Title EN 16601-00-01 ECSS-S-ST-00-01 ECSS system Glossary

38、 of terms EN 16602-10 ECSS-Q-ST-10 Space product assurance Product assurance management EN 16602-20 ECSS-Q-ST-20 Space product assurance Quality assurance EN 16602-30 ECSS-Q-ST-30 Space product assurance Dependability EN 16602-60 ECSS-Q-ST-60 Space product assurance Electrical, electronic and electr

39、omechanical (EEE) components EN 16603-10 ECSS-E-ST-10 Space engineering System engineering general requirements EN 16601-10 ECSS-M-ST-10 Space project management Project planning and implementation EN 16601-10-01 ECSS-M-ST-10-01 Space project management Organization and conduct of reviews EN 16601-4

40、0 ECSS-M-ST-40 Space project management Configuration and information management EN 16602-60-02:2014 (E)BS EN 16602-60-02:20143 Terms, definitions and abbreviated terms 3.1 Terms from other standards For the purpose of this Standard, the terms and definitions from ECSS-ST-00-01 apply. 3.2 Terms spec

41、ific to the present standard 3.2.1 application specific integrated circuit (ASIC) full custom or semi custom designed monolithic integrated circuit that can be digital, analog or a mixed function for one user 3.2.2 ASIC technology totality of all elements required for the design, manufacture and tes

42、t of ASIC components NOTE Design tools and their description, cell libraries, procedures, design rules, process line and test equipment. 3.2.3 application specific standard products (ASSP) ASICs designed to make standard products that are made available to a broader range of applications NOTE ASSPs

43、are most often are provided with a VHDL model and disseminated with documentation. 3.2.4 block diagram abstract graphical presentation of interconnected named boxes (blocks) representing an architectural or functional drawing 3.2.5 cell specific circuit function including digital or analog basic blo

44、cks 3.2.6 cell library collection of all mutually compatible cells which conforms to a set of common constraints and standardized interfaces designed and characterized for a specified technology EN 16602-60-02:2014 (E)BS EN 16602-60-02:20143.2.7 data sheet detailed functional, operational and parame

45、tric description of a component NOTE A data sheet can include, for instance, a block diagram, truth table, pin and signal description, environmental, electrical and performance parameters, tolerances, timing information, and package description. 3.2.8 design flow selection and sequence of engineerin

46、g methods and tools to be applied during the implementation of the design 3.2.9 design for test (DFT) structure technique used to allow a complex integrated circuit (IC) to be tested NOTE This can include any mechanism aimed to provide better observability or commandability of internal nodes of the

47、chip not accessible through primary inputs and outputs. 3.2.10 design iteration design changes that occur in any single phase or between two consecutive phases as defined in the ASIC and FPGA development plan, before the design is released for prototype implementation 3.2.11 detail specification pro

48、curement specification according to ESCC format that defines, for instance, the maximum ratings, parameter limitations, mechanical outline, pin description and screening requirements 3.2.12 development step major step of the development flow for the ASIC and FPGA development NOTE Definition phase, a

49、rchitectural design, detailed design, layout, prototype implementation and design validation. 3.2.13 fault coverage measure expressed as a percentage of the proportion of actually detectable faults versus all possible faults in a digital circuit, for a given set of test patterns and with respect to a specific fault model 3.2.14 field programmable gate array (FPGA) standard semiconductor device that becomes customized when programmed by the user with the FPGA specific software and hardware tools 3.2.15 floorplan abstracted, scaled layout drawing