BS DD IEC PAS 62326-7-1-2007 Performance guide for single- and double-sided flexible printed wiring boards《单面和双面柔性印制布线电路板的性能指南》.pdf

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1、 g49g50g3g38g50g51g60g44g49g42g3g58g44g55g43g50g56g55g3g37g54g44g3g51g40g53g48g44g54g54g44g50g49g3g40g59g38g40g51g55g3g36g54g3g51g40g53g48g44g55g55g40g39g3g37g60g3g38g50g51g60g53g44g42g43g55g3g47g36g58printed wiring boards ICS 31.180Performance guide for single- and double-sided flexible DRAFT FOR D

2、EVELOPMENTDD IEC/PAS 62326-7-1:2007DD IEC/PAS 62326-7-1:2007This Draft for Development was published under the authority of the Standards Policy and Strategy Committee on 29 June 2007 BSI 2007ISBN 978 0 580 50805 9of the PAS should be extended for a further 3 years or what other action should be tak

3、en and pass their comments on to the relevant international committee.Observations which it is felt should receive attention before the official call for comments will be welcomed. These should be sent to the Secretary of the responsible BSI Technical Committee at British Standards House, 389 Chiswi

4、ck High Road, London W4 4AL.The UK participation in its preparation was entrusted to Technical Committee EPL/501, Electronic assembly technology.A list of organizations represented on this committee can be obtained on request to its secretary.This publication does not purport to include all the nece

5、ssary provisions of a contract. Users are responsible for its correct application.Amendments issued since publicationAmd. No. Date Commentsstandard, but made available to the public and established in an organization operating under a given procedure.A review of this Draft for Development will be ca

6、rried out not later than 3 years after its publication.Notification of the start of the review period, with a request for the submission of comments from users of this Draft for Development, will be made in an announcement in the appropriate issue of Update Standards. According to the replies receiv

7、ed, the responsible BSI Committee will judge whether the validity National forewordThis Draft for Development was published by BSI. It is the UK implementation of IEC/PAS 62326-7-1:2007.This publication is not to be regarded as a British Standard.It is being issued in the Draft for Development serie

8、s of publications and is of a provisional nature. It should be applied on this provisional basis, so that information and experience of its practical application can be obtained.A PAS is a Technical Specification not fulfilling the requirements for a PUBLICLY AVAILABLE SPECIFICATION IECPAS 62326-7-1

9、First edition2007-04Performance guide for single- and double-sided flexible printed wiring boards Reference number IEC/PAS 62326-7-1:2007(E) DD IEC/PAS 62326-7-1:2007CONTENTS 1 Scope 5 2 Normative references .5 3 Terms and definitions .5 4 Test methods .5 5 Performance levels.6 6 Base materials .6 7

10、 Visual inspection 6 7.1 Test environment.6 7.2 Test specimens .6 7.3 Tools for testing.6 7.4 Preparation of limit samples.6 7.5 Description of inspection6 8 Dimensional inspections .22 8.1 Measurement of dimension 22 8.2 External dimension 22 8.3 Thickness23 8.4 Hole diameter23 8.5 Conductor width

11、23 8.6 Cumulative pattern pitch 23 8.7 Distance between hole centers 24 8.8 Design minimum distance between board edge and conductor25 8.9 Position accuracy 25 8.10 Registration of pressure sensitive or heatactivated adhesive (Including adhesive squeeze-out) to flexible printed board and stiffener27

12、 9 Electrical performance test .28 10 Mechanical performance test 29 11 Environmental performance 30 12 Chemical resistance .30 13 Cleanliness 30 14 Flame resistance 30 15 Marking, packaging, and storage 30 15.1 Marking on products 31 15.2 Marking on package 31 15.3 Packaging and storage 31 Annex A

13、Handling instruction manual handling of polyimide-base FPC32 Annex B Ion migration test 34 Annex C Whisker test .35 Annex D Additional information Explanation on JPCA performance guide for single-and double-sided flexible printed wiring boards .37 Figure 1 Nicks and pinholes in conductor7 Figure 2 R

14、educed area on land 7 DD IEC/PAS 62326-7-1:2007 2 Figure 3 Circumferential void at the component hole.7 Figure 4 Unnecessary copper between conductor/spur and nodule of conductor.8 Figure 5 Unnecessary copper, spurs and nodules in an open area and nodules of conductor corners.8 Figure 6 Etched conca

15、ve surface of the conductor and nodule at a conductor corner19 Figure 7 Conductor delamination19 Figure 8 Scratch on conductor10 Figure 9 Voids .10 Figure 10 Foreign substance11 Figure 11 Lifting and delamination of coverlay and covercoat12 Figure 12 Allowable squeeze-out of coverlay adhesive and oo

16、ze-out of covercoat and photosensitive resist 12 Figure 13 Plating defects .13 Figure 14 Penetration of plated metal or solder.15 Figure 15 Plating voids in plated through hole 16 Figure 16 Tear and nick .16 Figure 17 Burrs16 Figure 18 Thready burrs.17 Figure 19 Foreign substance between board and s

17、tiffener.17 Figure 20 Voids between board and stiffener 18 Figure 21 Cracks .18 Figure 22 Chip-off19 Figure 23 Protrusion and dent on flexible printed board 20 Figure 24 Bow and twist.21 Figure 25 Dent.21 Figure 26 Scratch on base film.21 Figure 27 Cumulative pitch.24 Figure 28 Misregistration of ho

18、le and land .25 Figure 29 Misregistration of land and coverlay (or covercoat)25 Figure 30 Registration of holes.26 Figure 31 The displacement of the outer dimensions Figure 32 Registration of pressure-sensitive or heat-activated adhesive from flexible printed board and stiffener (including adhesive

19、squeeze-out) .27 Figure B.1 Structure of specimen for ion migration test. 34 Figure C.1 Basic structure of the test equipment.35 Figure C.2 Example of the construction of the test equipment .35 Table 1 Allowable nicks and pinholes .7 Table 2 Allowable unnecessary copper, spur and nodule between cond

20、uctors 8 Table 3 Allowable etched concave of the surface conductor.19 Table 4 Allowable conductor delamination 9 Table 5 Allowable scratch on conductor10 Table 6 Allowable discoloration 10 .26DD IEC/PAS 62326-7-1:2007 3 Table 7 Allowable void .11 Table 8 Allowable non-conductive foreign substance 11

21、 Table 9 Allowable squeeze-out of coverlay adhesive, and ooze-out of covercoat and photosensitive register strike.12 Table 10 Effective land width at a land .12 Table 11 Gold plating.14 Table 12 Requirement for metal penetration between conductor and coverlay .15 Table 13 Requirements for metal pene

22、tration between conductor and base film15 Table 14 Gold plating.15 Table 15 Allowable plating voids 16 Table 16 Cracks.18 Table 17 Thermosetting adhesive on surface19 Table 18 Flux residue on surface19 Table 19 Residue of metal powder (solder, aluminum, copper, etc.) 20 Table 20 Residue of adhesive

23、20 Table 21 Dent21 Table 22 Dent21 Table 23 Allowable scratches on base film .22 Table 24 Dents on coverlay and covercoat .22 Table 25 Requirement for scratch on coverlay and covercoat22 Table 26 Tolerance of external dimension 23 Table 27 Thickness tolerance.23 Table 28 Hole diameter and tolerance

24、23 Table 29 Conductor width and tolerance.23 Table 30 Cumulative pattern pitch and tolerance 24 Table 32 Design minimum distance between board edge and conductor25 Table 33 Effective land area.26 Table 34 Allowable displacement between outlines of the stiffener and the FPC26 Table 35 Registration of

25、 punched outline to conductor patterns.27 Table 36 Electrical properties of flexible printed boards 28 Table 37 Mechanical properties of flexible printed boards .29 Table 38 Environmental tests and requirements30 Table 39 Requirements for packaging.31 Table A.1 Recommended pre-drying conditions 33 T

26、able 31 Tolerance of distance between hole centers .24 DD IEC/PAS 62326-7-1:2007 4 PERFORMANCE GUIDE FOR SINGLE- AND DOUBLE-SIDED FLEXIBLE PRINTED WIRING BOARDS 1 Scope This PAS provides the requirements for the single- and double-sided flexible printed wiring boards (hereinafter designated as “flex

27、ible printed board“ or FPC). In this document, an FPC means a single- or double-sided FPC prepared by lamination of a film of polyester or polyimide with copper foil(s) on one or both sides of a board including the type with no adhesive layer, and with conductor pattern formed by the subtractive met

28、hod (etching of the copper foil), or possibly by the build-up method. 2 Normative references The following referenced documents are indispensable for the application of this document. For dated references, only the edition cited applies. For undated references, the latest edition of the referenced d

29、ocument (including any amendments) applies. IEC 60326-7:1981, Printed boards Part 7: Specification for single- and double-sided flexible printed boards without through connections IEC 60326-8:1981, Printed boards Part 8: Specification for single- and double-sided flexible printed boards with through

30、 connections JPCA-TD01:2000, Terms and definitions for printed circuits JPCA-BM03:2003, Flexible printed wiring boards (adhesive and adhesiveless types) JIS C 5016:1994, Test methods for flexible printed wiring boards JIS C 5017:1994, Single- and double-sided flexible printed wiring boards JIS C 560

31、3:1993, Terms and definitions for printed circuits JIS C 6471:1995, Test methods of copper-clad laminates for flexible printed wiring boards JIS C 6472:1995, Copper-clad laminates for flexible printed wiring boards (polyester film, polyimide film) JIS C 6515:1998, Copper foil for printed wiring boar

32、ds 3 Terms and definitions For the purposes of this document, the terms and definitions given in JIS C 5603, JIS C 5017, JIS C 5016, and JPCA-FC03 apply. 4 Test methods The test methods used in this document as specified below shall be in conformance with JIS C 5016. a) Test methods requiring compli

33、cated referencing procedures are reproduced in this document. b) Tests on through connection apply only to double-sided FPCs. DD IEC/PAS 62326-7-1:2007 5 c) External appearance is the only requirement specified in this document for stiffeners affixed to FPCs. 5 Performance levels The FPCs are classi

34、fied into three levels, Levels 1, 2, and 3, and an additional special level, Level X, for applications requiring special attention. They are defined as: Level 1 FPCs requiring “ordinary“ performance; Level 2 FPCs requiring “high“ performance; Level 3 FPCs requiring “extra-high“ performance; Level X

35、FPCs requiring special performances which do not belong to the above-mentioned three levels, and the specifications requiring an agreement between user and supplier. A relevant level of the board is chosen for a specific application of the board. A different level can be selected for a specific sect

36、ion of the board when the required specification of the section is different from that of another part of the board. 6 Base materials The base materials used in FPCs shall satisfy the requirements specified in JPCA-BM03. 7 Visual inspection 7.1 Test environment The test environment shall meet the re

37、quirements of JIS C 5016, Clause 3. 7.2 Test specimens The test specimens shall meet the requirements of JIS C 5016, Clause 4. 7.3 Tools for testing A magnifying glass having a magnification of 3 to 10 shall be used for examining the appearance and the surface finish conditions of the product. Dimen

38、sions shall be measured with a scaled magnifying glass or an instrument capable of two-dimensional coordinate measuring, if necessary. Thickness shall be measured with a micrometer having an accuracy of 1 m or better. 7.4 Preparation of limit samples Limit samples showing the required criteria to ma

39、ke technical judgments may be prepared under agreement between user and supplier for the application of this document. 7.5 Description of inspection Requirements, procedures, and illustration for visual inspections are given in 7.5.1 through 7.5.6. Requirements that are not designated for a specific

40、 performance level shall apply to all the performance Levels 1, 2 and 3. DD IEC/PAS 62326-7-1:2007 6 7.5.1 Visual inspection of conductor 7.5.1.1 Open and short circuit There shall be no open and/or short circuit on FPCs. 7.5.1.2 Nicks and pinholes on conductor a) The allowable width (w) and length

41、(l) of a nick and a pinhole of the conductor reducing conductor width, as shown in Figure 1, shall meet the requirement given in Table 1 for the finished conductor width (W) (see Note 1). NOTE 1 The width of the finished conductors should be measured at the bottom of the conductor. Figure 1 Nicks an

42、d pinholes in conductor Table 1 Allowable nicks and pinholes Level Nicks and pinholes 1 and 2 w1 1/2W l 2W 3 w1 1/3W l W b) The void area on a land, as illustrated in Figure 2, shall not exceed 10 % of the effective exposed land area. Figure 2 Reduced area on land c) The circumferential void of a le

43、ad insertion hole, as illustrated in Figure 3, shall not exceed one-third of the total circumference. Figure 3 Circumferential void at the component hole DD IEC/PAS 62326-7-1:2007 7 7.5.1.3 Distance between conductor/spur and nodule of conductor The distance (s1) or (s2+ s3) in Figure 4 relative to

44、the finished conductor spacing(s) shall meet the requirement given in Table 2. Figure 4 Unnecessary copper between conductor/spur and nodule of conductor Table 2 Allowable unnecessary copper, spur and nodule between conductors Level Unnecessary copper, spurs and nodules, sor ( s2+ s3) 1 and 2 1/2 s

45、a or (s2+ s3) 3 2/3 s a or (s2+ s3) 7.5.1.4 Unnecessary copper between conductor/spur and nodule of conductor in an open area The spacing(s) between the board edges and the unnecessary copper or spur and nodule shall be larger than 0,125 mm in an open area where no conductor pattern is routed, as il

46、lustrated in Figure 5. The spacing(s) between the board edge and the unnecessary copper or spur and nodule shall be larger than 0,125 mm. The open area as stated in this clause shall have a width of no less than 0,375 mm. Figure 5 Unnecessary copper, spurs and nodules in an open area and nodules of

47、conductor corners 7.5.1.5 Etched concave surface of the conductor Etched concave surface (d) of the conductor relative to the conductor thickness (t), as illustrated in Figure 6, shall meet the requirement given in Table 3. The concave surface shall not run across the entire width of a conductor. DD

48、 IEC/PAS 62326-7-1:2007 8 Figure 6 Etched concave surface of the conductor and nodule at a conductor corner Table 3 Allowable etched concave of the surface conductor Level Etched concave surface of the conductor, d (t: conductor thickness) 1 and 2 d 1/3 t 3 d 1/5 t 7.5.1.6 Conductor delamination The

49、 width (w1) and length (l) of conductor delamination relative to the finished conductor width (W), as illustrated in Figure 7, shall meet the requirement given in Table 4. Figure 7 Conductor delamination Table 4 Allowable conductor delamination Level Conductor delamination, length (l), width (w1) 1 Coverlay laminated area l