ARMY MIL-I-48632-1986 INTEGRATED CIRCUIT DIGITAL CMOS CONTROL AND TIMING BASE MONOLITHIC SILICON《铁制硅互补金属氧化物半导体制数字集成电路》.pdf

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1、- 73 MIL-I-4b32 13 S 7777906 0322583 b MIL-1-48638 (AR) 31: JULY 1986 MILITARY SPECIFICATION INTEGRATED CIRCUIT, DIGITAL, CMOS CONTROL AND TIMING BASE, MONOLITHIC, SILICON This specification is approved for use by the U.S. Army Armament, Munitions and Chemical Command, and 1s available for use by al

2、l Departments and Agencies of the Department of Defense. 1. SCOPE 1.1 Scope. This specification establishes the performance, test, manufacturing and acceptance requirements for the integrated circuit (I.C.) to be used in the M718El/M741El Mines. 2. APPLICABLE DOCUMENTS 2.1 Government documents. 2.1.

3、1 Specifications and standards. Unless otherwise specified, the following specifications and standards of the issue listed in that issue of the Department of Defense Index of Specifications and Standards (DoDISS) specif ied fn the solicitation, form a part of this specification .to the extend specif

4、ied herein. SPEC1 F ICAT IONS MILITARY AM MIL-M-38510 - Microcircuits, General MIL-1-4 5208 - inspection System Requirements Specification for . - Mi cr oc i r cu i t s , Pr epar at i on for Delivery Of . .- MIL-M-55565 -. . .- Beneficial comments (recommendations, additions, deletions) and any pert

5、inent data which may be of use in improv- ing this document should be addressed to: Commander, U.S. Army Armament Research. Development and Engineer: ing Center, Attn: AMSMC-QA, Dover. New Jersey 07801-5001 by using the self-addressed Standardization Document . Improvement Proposal (DD Form 1426) ap

6、pearing at the end of this document or by letter. -. c THIS DOCUMENT CONTAINS 2-7 PAGES. SC N/A I FSC 1375 DISTRIBUTION STATEMENT A. Approved for public release; distribution is unlimited. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-MIL-I-L18b32

7、13 M 777770b 0322582 8 I MIL-1-48632 (AR) STANDARDS MIL I TARY MIL-STD-105 - Sampling Procedures and Tables for Inspection by Attributes. MIL-STD-883 - Test Methods and Procedures for I Microelectronics. MIL-STD- 13 31 - Parameters to be Controlled for the Specification of Micro- circuits. MIL-STD-

8、130 - Identification Marking of U.S. Military Property. 2.1.2 Other Government documents, drawings, and publications. The following other Government documents form a part of this specification to the extend herein. DRAWING U. S. ARMY ARMAMENT, MUNITIONS AND CHEMICAL COMMAND PRODUCT AND PACKAGING DRA

9、WINGS 9342575 - Logic Diagram, Integrated Circuit, 9317646 - Qualification, Electronic Component, Timing Base, CMOS. (Copies of specifications, Standards, handbooks, drawings, and publications required by manufacturers in connection with specific acquisition functions should be obtained from the con

10、tracting activity or as directed by the contracting officer.) In the event of a conflict between the text of this specification and the references cited herein, the text of this specification shall take precedence. 2.1.3 Order of precedence. 3. REQUIREMENTS 3.1 Parts and Materials. 3,l.l Components.

11、 The I.C. shall comply with all the requirements of the applicable drawings, specifications and standards. resistant or shall be plated or tceated to resist corrosion. External leads shall meet the requirements specified in 3.5.3. 3.1.2 Metals. External metal surface shall be corrosion 2 Provided by

12、 IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-MIL-I-4Bb32 13 m 773770b 0322583 T = MIL-1-48632 (AR) 3.1.3 Other materials. External parts, elements or coatings including markings shall not blister, crack, soften, flow or exhibit defect that adversely affect s

13、torage, operation or environmental capabilities of the integrated circuit delivered to this specification under the specified test condition. 3.2 Desiqn and construction. I.C. design and construction shall be in accordance with the requirements specified herein and in the applicable specifications o

14、r drawings. MIL-M-38510, Appendix C, Case Outline D6, Configuration 1. 18 pin, dual-in-line hermetically sealed package. The package shall be of the type shown in figure 16, utilizing a ceramic lid, a ceramic base with gold deposit for mounting the die, Alloy 42 or Kovar solid metal lead frame thru

15、to cavity with aluminum cladding, and a glass frit to accomplish the seal between the lid, lead frame and the base frit seal temperature shall be in excess of 400OC. No organic or polymeric material shall be used inside the package. delineated as inside a 2 MIL border and shall not include the area

16、within 1.5 MILS of the bonding pads. 3.2.4 Passivation. The chip shall be passivated with silicon dioxide and/orn nitrade to render it impervious to contaminated environments. The bonding pad areas shall be the only areas with no surface passivation. 3.2.5 Static charqe protection. Static charge pro

17、tection shall be provided internally on all terminals. 3.3 Desiqn documentation. When specified in the procurement document, design, topography and schematic circuit information for the microcircuit supplied under this specification shall be submitted to the procuring activity. Unless otherwise spec

18、ified, all design documentation shall be sufficient to depict completely the physical and electrical construction of the microcircuit supplied under this specification, and shall be traceable to the specific production lot (s) and inspection lot codes under which microcircuit are manufactured and te

19、sted so that revisions can be ident if i ed. 3.2.1 Dimensions. The package dimension shall conform to 3.2.2 Packaqe. The finished component shall be supplied in a 3.2.3 Die configuration. Active circuit area shall be the area 0 3.3.1 Die topography. For microcircuit dies, there shall be an enlarged

20、color photograph(s) showing the topography of elements of the die to a minimum magnification of BOX. If this results in a photograph larger than 8“ x lo“, the magnification may be reduced to accommodate an 8“ x 10“ view. O 3 . - - - _ - Provided by IHSNot for ResaleNo reproduction or networking perm

21、itted without license from IHS-,-,-3.3.2 Loqic diaqram. The actual logic diagrams of the microcircuit supplied under this specification shall be provided, showing all the logic/circuit elements functionally designed into the microcircuit together with their values, when applicable. 3.4 Electrical re

22、quirements. 3.4.1 Maximum Rating. (As specified in Table 1) Unit Characteristic Symbol Rating D C Supply Voltage VB 5 to +10 Volts (See 3.4.4) All Inputs VIN -0.5 to +10 Volts Temperature Operating TA (OP) -55 to +125OC Storage . TA(STG) -65 to +15OoC TABLEZ- MAXIMUM RATING 3.4.2 Electrical characte

23、ristics. (As specified in Table 2) TABLE 2 PERFORMANCE CHARACTERISTICS Characteristic Capacitance coupled feedback signal amplitude Terminal 10 Leakage Current Dynamic Load . Current (Average Current) “1“ Output Voltage: Terminal 15 Min vB=5.0V with terminai driven O. 5 by a simulated TTB signal sou

24、rce (See 4.5.12) Conditions - TA = +25oC VB = 7.5V See 4.5.2 -32OC - 4 TA 5 +63oD VB = 7.5V TA = +25oC VB = 7.5V -32OC I I O In e4 N o e a) QI In . .In 4 4 . e o .o In- In d d In In (sl c7 o o o . 3 ln 9 In 3 U U i? Ik I t 3 rn N e I Ei rn o 4 In r( In o . o 9 In I 16 Provided by IHSNot for ResaleNo

25、 reproduction or networking permitted without license from IHS-,-,-MIL-I-LtBb32 13 m 777770b 0322577 T n W QI 1 C 4 L) E O u * 4 W w z Y OH 2 E H -I 4 3 a H H H W Il ai 2 n m L) m QI - -. , 1. 2. Rack frequency 30 - 70% duty-cycle. Amplitude of square wave: Both power supplies shall be turned off mo

26、mentarily at the end of each hour of operation to allow all logic circuits to return to the reset state. O and 7r5V I 26 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-4.5.12 Capacitance - Coupled feedback test. The internal capacitance couplingbetw

27、een the output at terminal 9 and the input at terminal 10 shall be tested by measuring the amplitude of-the spike signal observed at terminal 10 with device connected as shown in Figure 15. The signal shall be observed using a storage oscilloscope (Tetetronix 7633 with vertical amplifier 7A26 and ti

28、me base 7B53A, on an equivalent instrument). The amplitude of the spike signal (VFB) shall be measured-as shown in Figure 15. amplitude shall be as specified in Table 2. The RAMP VOLTAGE SOURCE (SLOPE NOTE 1. 0.05 v/ sec) FIGURE X. FEED-BACK SIGNAL TEST Y -%- Signal at Terminal 10 FIGURE 15. FEEDBAC

29、K SIGNAL TEST 27 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-4.6 Screeniq. Screening shall be in zrccor.dance with MIL-STD-883, method 5004- with the exception of khe following:. ; Screen Method . Burn-In test -* 1015 at 125OC for 160 hours Post

30、Burn-in 1015 at 125OC ALL ELECTRICAL (See paragraph 4.5.11) Parameters per TABLE I. 5. 5.1 Packaqinq. Circuit shall be packaged with a conductive material so khat damage from static charge or stray voltage is prevented . 5,2 M8arkinq. Each circuit shall be marked with the last three digits of the pa

31、rt number and revision Letter. (Example: 165A) The circuit shall also be marked with a lot number traceable to the vendors manufacturing records. The vendor may add additional markings for his use provided the additional markings do not interfere with the required markings, 5.3 Inspection lot format

32、ion. (Lot Identification):. To meet the requirements for material traceability required by contract, each integrated circuit lot will contain only one interfix number. The lot identificatian/date number shall. be preceded by a - three-digit interfix number. integral part of the lot identification nu

33、mber, and must be used to identif y those lots produced homogeneously in one continuous process. changing the interfix number. The interfix number shall be an Any of the conditions described .below shall be cause for 5.3.1 Chanqe in manufacturinq process, Changes representative of those which are su

34、bject to this requirement are any basic design changes in the manufacturing process such as: a. Die structure topography changes (e.g ., double-diffused, b. epitaxial, isolation). Mask changes or redesign which alter die size. C. Change in. passivation or classification material thickness or techniq

35、ue (including addition or deletion of passivation) . 28 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,- MIL-I-4b32 13 m 999770b 0322b07 2 MIL-1-48632 (AR) d. Change in die substrate or element attach material, method e. Changes in wire dimensions. f

36、. or location. O Package or lid structure and material changes or changes to the internal cavity geometry. 5.3.2 Chanqe in manufacturinq location. If the active line moves from one geographical location to another, the interfix number will be changed. camplete line shutdown of more than 90 days dura

37、tion will be cause for a change of the interfix number. 5.3.3 Interruption in manufacturing process over 90 days. A 6. NOTES 6.1 Orderinq data. See MIL-A-48078 (PA) 6.2 Submission of inspection equipment designs for approval. (See MIL-A-48078) . Submit equipment designs as required to Commander: USA

38、MCCOM, ATTN: AMSMC-QAT-I(D), Dover, NJ 07801-5001. Request that the letter of submittal state contractor, contract . number, specification number, item nomenclature and classification of defects or test paragraph. 6.3 Drawings. Drawings listed in Section 2 of this specification under the heading US

39、Army Armament Research and Development Center (ARDC) may also include drawings prepared by and identified as, US Army Armament Research and Development Command, Edgewood Arsenal, Frankford Arsenal, Rock Island Arsenal, or Picatinny Arsenal drawings. these activities is now under the cognizance of AR

40、DC. results. Distribution of ammunition data cards, inspection, and test results shall include Commander: AMCCOM, Dover, NJ 07801-5001, o Technical data originally prepared by 6.4 Distribution of ammunition data cards, inspection and test ATTN: AMSMC-QAT-M (D) 6.5 Subject term (key word) listinq. Dy

41、namic burn-in test Dynamic load, Oscillator current Integrated Circuit, Digital, CMOS Contra1 and Timlng Base Leakage Current test LVD Functioning Mechanical Shock Sequential Operation Test Stress Screening Cus todi an : Preparing activity: (Project 13 75-A3 00) Army-AR Army-AR O 29 0 - - - Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-