ARMY MIL-DTL-62736 A-1998 PRINTED WIRING ASSEMBLY I O《I O型印刷线路装配》.pdf

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1、IIL-DTL-bZ73bA m 99999Ob 2059279 3b3 m I INCH-POUNDI 23 Januarv 1998 SUPERSEDING 16 March 1992 MILDTL-6273 6A(AT) MIL-P-62736(AT) DETAIL SPECIFICATION PRINTED WIRING ASSEMBLY, I/O This specification is approved for use by the U.S. Army Tank-automotive and Armaments Command, Department of the Army, a

2、nd is available for use by ali Departments and Agencies of the Department of Defense. 1. SCOPE 1.1 ScoDe. This specification covers an Input/Output (TIO) Printed Wiring Assembly, herein referred to as the PWA. This is one of six printed wiring assemblies which comprise the Simplified Test Equipmenth

3、ternal Combustion Engine-Reprogrammable (STEDCE-R) Vehicle Test Meter (VTM) (see Drawing 12259265). 2. APPLICABLE DOCUMENTS 2.1 General. The documents listed in this section are specified in sections 3 and 4 of this specification. This section does not include documents in other sections of this spe

4、cification or recommended for additional information or as examples. While every effort has been made to ensure the completeness of this list, document users are cautioned that they must meet all specified requirement documents cited in sections 3 and 4 of this specification, whether or not they are

5、 listed. Beneficial comments (recommendations, additions, deletions) and any pertinent data which may be of use in improving this document should be addressed to: U.S. Army Tank-automotive and Armaments Command, ATTN: AMSTA-TR-EBLUE, Warren, Mi 48397-5000, by using the Standardization Document Impro

6、vement Proposal D Form 1426) appearing at the end of this document, or by letter. AMSC NIA FSC 5998 DISTRIBUTION STATEMENT A. Approved for public release; distribution is unlimited. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-NIL-DTL-62736A = 999

7、9906 2059280 085 MIL-DTL-62 73 6A(AT) 2.2 Government documents. 2.2.1 SDecifications. standards. and handbooks. The following specifications, standards, and handbooks form a part of this document to the extent specified herein. Unless otherwise specified, the issues of these documents are those list

8、ed in the issue of the Department of Defense Index of Specifications and Standards (DoDISS) and supplement thereto, cited in the solicitation (see 6.2). STANDARDS DEPARTMENT OF DEFENSE MIL-STD-810 - Environmental Test Methods and Engineering Guidelines (see 4.2.1). (Unless otherwise indicated, copie

9、s of the above specifications, standards, and handbooks are available from the Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 191 11-5094.) 2.2.2 Other Government documents. drawings. and tmblications. The following other Government documents, drawings, and pu

10、blications form a part of this document to the extent specified herein. Unless otherwise specified, the issues are those cited in the solicitation. DRAWINGS ARMY 12259253 - Printed Wiring Assembly, I/O. (Copies of these drawings are available from the U.S. Army Tank-automotive and Armaments Command,

11、 Warren, MI 48397-5000.) 2.3 Non-Government publications. The following documents form a part of this document to the extent specified herein. Unless otherwise specified, the issues of the documents which are DoD adopted are those listed in the issue of the DoDISS cited in the solicitation. Unless o

12、therwise specified, the issues of documents not listed in the DoDISS are the issues of the documents cited in the solicitation (see 6.2). AMERICAN NATIONAL STANDARDS INSTITUTE (ANSI) ANSVIPC J-STD-O0 1 - Requirements for Soldered Electrical and Electronic Assemblies. 2 Provided by IHSNot for ResaleN

13、o reproduction or networking permitted without license from IHS-,-,-MIL-DTL-6273 6A(AT) (Application for copies should be addressed to the American National Standards Institute (ANSI, 11 West 42nd Street, New York, NY 10036.) ELECTRONIC INDUSTRIES ASSOCIATION (EU) RECOMMENDED STANDARDS 23 2 485 - In

14、terface Between Data Terminai Equipment and Data Circuit Terminating Equipment Employing Serial Binary Data Interchange. - Electrical Characteristics of Generators and Receivers for Use in Balanced Digital Multipoint Systems. (Application for copies should be addressed to the Electronic Industries A

15、ssociation, 2001 Eye Street W, Washington, DC 20006.) 2.4 Order of precedence. In the event of a conflict between the text of this document and the references cited herein, the text of this document takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unles

16、s a specific exemption has been obtained. 3. REQUIREMENTS 3.1 First article. When specified (see 6.2), a sample PWA shall be subjected to first article inspection in accordance with 4.1.1. 3.2 Design, materials, and manufacturhw processes. Design, materials, and manufacturing process selection shall

17、 be as specified herein and in applicable referenced specifications, standards, and drawings. Materials shall be uniform and free from imperfections or defects which affect their performance and serviceability. All metallic parts shall be made from corrosion resistant metals or treated with corrosio

18、n-resistant materials. Asbestos and Cadmium materials shall not be used in any form in any part of the PWA. No item, part or assembly shall contain radioactive materials in which the specific activity is greater than 0.002 microcuries per gram or activity per item equals or exceeds 0.01 microcuries.

19、 3.2.1 Recycled. recovered. or environmentally preferable materials. Recycled, recovered, or environmentally preferable materials should be used to the maximum extent possible provided that the material meets or exceeds the operational and maintenance requirements, and promotes economically advantag

20、eous life cycle costs. 3.3 Operating requirements. Each PWA shall provide the following functional, operational, and performance capabilities. 3 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-MIL-DTL-6273 6A(AT) 3.3.1 Input power. The PWA shall requ

21、ire not more than the current specied in table I. TABLE I. Input power. i Source Volta e Current Pl-5, 6 5 Vdc- 150 mAg Pl-13 14 15 Vdc Pl-l9,20 -15 Vdc 8.5 mA - 1/ Vdc = Volts direct current - 21 mA = milliampere 3.3.2 Lopic levels. 3.3 2.1 Complimentary metal oxide semiconductor (CMOS) logic level

22、s. Unless otherwise specified (see 6.2), CMOS logic levels accepted by and output fiom the PWA shall be as follows: Input High (Logic Level 1) = 3.5 Vdc minimum (min) Input Low (Logic Level O) = 1.5 Vdc maximum (max.) Output High (Logic Level 1) = 4.5 Vdc min Output Low (Logic Level O) = 0.5 Vdc max

23、. 3.3.2.2 Transistor-Transistor Logic (TTL) lokc levels. Unless otherwise specified (see 6.2), TTL logic levels accepted by U16 and U17 shall be: Input High (Logic Level 1) = 2.0 Vdc min Input Low (Logic Level O) = 0.8 Vdc max. 3.3.3 Input isolation. (NOTE: A suEx 7 following a capitalized signal na

24、me denotes logic negation.) 3.3.3.1 Data bus isolation. Logic levels applied to any one BUS pin (Pl-21 through Pl-28) shall not be affected by logic levels present at any other BUS pin. 3.3.3.2 J3-T. J3-U. IOF/7. MRD/. OEN-O. OEN-O/. O. CLEAR/. and TPB isolation. Logic levels applied to any one of P

25、l-1 1Pl-12, P1-15R1-16, Pl-35 through Pl-38, Pl-57, and Pl-66 shall have no effect on, nor be affected by logic levels applied at any of the other pins specified in this paragraph. Pl-62 should be grounded through a 1 kilohrn (Kohrn) resistor to yield appropriate results. 3.3.4 DCA/-15 Vdc source. T

26、he voltage at Pl-19 and Pl-20 shall not be greater than 0.6 Vdc when Pl-42 is pulled up to a voltage greater than 0.4 Vdc and less than 32 Vdc. 4 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-MIL-DTL-bZ73bA H 999990b 2059283 894 P 1-73 MIL-DTL-6273

27、 6A(AT) 1 3.3.5 Reset. P 1-79 U8 pins 3,5 u9 pins 2, 5,7, 10, 12, 15 3.3.5.1 Power-up reset. Pl-68, U1 pin 21, U2 pin 2, U3 pin 2, U9 pin 1, U12 pin 13, and UZO pins 1 and 6 shall conform to the timing diagram shown in figure 1 when the voltage at P1-5 and P 1-6 is brought from O Vdc to +5 Vdc. O O

28、O 3.3.5.2 CLEAR/. Applying a logic level O to Pl-62 shall bring Pl-68 to logic level O in less than 62 nanoseconds (ns). 3.3.5.3 States during power-up reset or CLEAR/. While P1-62 is held at logic level O, the following pins shall be at the logic level designated in table II. I Pl-76 I 1 I I U12pin

29、s3,9,11 1 O 3.3.6 BUS transceiver. 3.3.6.1 Data in. With U4 pin 1 at logic level O, data shall be applied and the results shall be observed as shown in table III. 3.3.6.2 Extended I/O latch. While U4 pin 1 is at logic level O, the waveforms shown in figure 2 shall be applied to latch the data shown

30、in table IV in U9. 5 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-MIL-DTL-b273bA 99999Ob 205928ii 720 Applied data P1- 28 27 26 25 24 23 22 21 O0 o o o o o 0101010101010101 10 1 o 1 o 1 o 111 11 11 MIL-DTL-6273 A(AT) Observed data 9 8 7 6 5 4 3 2

31、O0 o o 00000 1 o 1 O1010 11 11 11111 u4 pin Applied data P1- 28 27 26 25 24 23 22 21 00000000000000 01010101010101 10101010101010 11111111111111 Observed data u9 pin 15 12 10 07 05 02 3.3.6.3 Extended U0 decoder. While U4 pin 1 is at logic level O, the waveforms shown in figure 2 shall be applied to

32、 latch the data shown in table V into U9 and the results shall be observed at U10. Applied data P1- 28 27 26 25 24 23 22 21 xxxxo O xxxxo O xxxxo O xxxxo O 1 xxxxo 1 xxxxo 1 xxxxo 1 1 o xxxxo 1 1 xxxx Observed data u10 pin 10 11 12 13 14 0000000 0100001 1000010 100100 0001000 0110000 o o o 0.0 10000

33、0 1xxxooooo 3.3.6.4 BUS transceiver direction logic. U4 pin 1 shall conform to the logic shown in table W. 6 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-MIL-DTL-6273bA m 9999906 2059285 667 Applied data Pl-35 Pl-36 UlOpin 14 UlOph 13 Observed dat

34、a U4ph 1 Io X X XI O I Applied data P1-35 PI-36 P1-57 O X X 1 O O 1 O 1 1 1 X X O X X 1 1 O O 1 1 O 1 Observed data: U1 pin 23, U2 pin 11, adU3 ph 11 O 1 O 1 O O I 1 Selected Load MDU or Register Read Status Read Control Load X Both Y z Both (X denotes a dont care condition) Applied data P1- 28 27 2

35、6 25 24 23 22 21 X X 1 1 O O O 1 X X 1 1 O O O 1 X X O O O O O 1 BothXXlOOOOl X X O 1 O O O 1 3.3.7 Multiplv/divide unit WU). 3.3.7.1 MDU crvstal oscillator. The signal at Y2 pin 8 shall have a frequency of 1 megahertz (MHz) 2 1 kilohertz (kHz). The rise and fall times of the signal at Y2 pin 8 shal

36、l be less than 150 ns. 3.3.7.2 MDU chiD select 1 (CSl) logic. U1 pin 23 shall conform to the logic shown in table VII. 3.3.7.3 MDU register selection. The MDU registers shall be selected for either loading or reading by using the timing diagram of figure 2 and the appropriate data from table VIH. 7

37、Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-MIL-DTL-6273 6A(AT) u5 Pin 6 5 3 2 4 13 12 14 3.3.7.4 MDU rePister load. Mer latching the data fiom table WII into U9 to select the MDU Control, X, Y, or 2 register by applying the waveforms in figure 2

38、, the data fiom the register selected shall be loaded by applying the waveforms in figure 3. Frequency 307.20 kHz k 307 Hz I/ 153.60 kHz 5 154 Hz 76.800 kHz +: 77 Hz 38.400 kHz 5 38 Hz 19.200 kHz f. 19 Hz 9.6000 kHz 2 10 Hz 4.8000 kHz k 5 Hz 2.4000 kHz 2 2 Hz 3.3.7.5 MDU register read. After latchin

39、g the data fiom table WII into U9 to select the MDU Status, X, Y, or Z register by applying the waveforms in figure 2, the data fiom the register selected shall be read by applying the waveforms in figure 4. 3.3.7.6 Multiplv with add. The MDU shall multiply a 16 bit operand that has been loaded into

40、 MDU register X by a 16 bit operand that has been loaded into MDU register Z, then add a 16 bit operand that has been loaded into MDU register Y. The MDU shall produce a 32 bit result, the high order 16 bits of which shall be read from the MDU Y register and the low order bits of which shall be read

41、 from the MDU 2 register, a minimum of 17 microseconds (ps) . Soldering shall meet or exceed the requirements of ANSVIPC J-STD-O01 (see 4.2). 3.4 Interface requirements. Each PWA shall accommodate the following requirements. 3.4.1 Overall envelope. Overail envelope of the PWA shaii be in accordance

42、with drawing 12259253. 3.5 Ownership and support requirements. 3.5.1 Interchaneeability. Interchangeability tolerances should permit parts, subassemblies and assemblies to be used in their parent assemblies without regard to the source of supply or manufacturer. Parts, subassemblies and assemblies h

43、aving the full range of dimensions and characteristics permitted by the specification governing the part, subassembly or assembly should be usable as replacement items without selection and without departure from the specified performance guidelines of the parent items. 3.5.2 Identification marking.

44、 Unless otherwise specified (see 6.2), identification marking shall be permanent and legible and shall as minimum include the following: a. Nomenclature PRINTED WIRING ASSEMBLY, YO b. Military part number. c. Manufacturers cage code and name. d. Manufacturers serial numbers. e. Contract number. f Sy

45、mbo1“US. 3.6 Operating environment requirements. Each PWA shall operate under the following environmental conditions without damage or loss of performance. 3.6.1 Temperature. 3.6.1.1 High temperature (operatina). The PWA shall be capable of operation without damage or malfunction at a high temperatu

46、re of +125“F (52C) (without solar radiation). 3.6.1.2 Low temperature (operating). The PWA shaii be capable of operation without damage or malfunction at a low temperature of +20F (-7C). For ambient temperatures below +20“F (-7OC), the test set shall be operated in a shelter. 3.6.1.3 High temperatur

47、e (nonoperating). The PWA shaii be capable of being stored and transported in its case without damage at an ambient temperature of +16OoF (71C). 12 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-MIL-DTL-62736A 9999906 2059291 960 = Title MIL-DTL-627

48、3 6A(AT) Reuuirement 3.6.1.4 Low temperature (nonoperatinp;). The PWA shall be capable of being stored and transported in its case without damage at an ambient temperature of -60F (-5 1OC). 3.6.2 Fungus. All nonmetallic materials that are not inherently fungistatic shall function in a fungus environ

49、ment without adversely affecting the operatiodperformance of the PWA. 3.6.3 Shock. The PWA shall evidence no degradation of function and meet the requirements of 3.3 when subjected to the shock test. 3.6.4 Vibration. The PWA shall evidence no degradation of function and meet the requirements of 3.3 when subjected to the vibration test. 3.6.5 Bum-in. Unless otherwise specified (see 6.2), the PWA shall be subjec