ANSI INCITS397 V3-2005 Information Technology - AT Attachment with Packet Interface - 7 - Volume 3 - Serial Transport Protocols and Physical Interconnect (ATA ATAPI-7 V3)《带有数据包接口的集.pdf

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1、American National StandardDeveloped byfor Information Technology AT Attachment with Packet Interface - 7Volume 3 - Serial Transport Protocolsand Physical Interconnect(ATA/ATAPI-7 V3) ANSI INCITS 397-2005 (Vol. 3)ANSIINCITS397-2005(Vol. 3)Copyright American National Standards Institute Provided by IH

2、S under license with ANSINot for ResaleNo reproduction or networking permitted without license from IHS-,-,-Copyright American National Standards Institute Provided by IHS under license with ANSINot for ResaleNo reproduction or networking permitted without license from IHS-,-,-ANSIINCITS 397-2005(Vo

3、l. 3)American National Standardfor Information Technology AT Attachment with Packet Interface - 7Volume 3 - Serial Transport Protocolsand Physical Interconnect(ATA/ATAPI-7 V3)SecretariatInformation Technology Industry CouncilApproved February 7, 2005 American National Standards Institute, Inc.Abstra

4、ctThis standard specifies the AT Attachment Interface between host systems and storage devices. It pro-vides a common attachment interface for systems manufacturers, system integrators, software suppliers,and suppliers of intelligent storage devices. It includes the Packet Command feature set implem

5、ented bydevices commonly known as ATAPI devices. It also includes the Serial Transport Protocols and PhysicalInterconnect for AT Atachment devices commonly known as Serial ATA.This standard maintains a high degree of compatibility with the AT Attachment Interface with Packet Inter-face - 6 (ATA/ATAP

6、I-6), ANSI INCITS 361-2002, and while providing additional functions, is not intendedto require changes to presently installed devices or existing software.Copyright American National Standards Institute Provided by IHS under license with ANSINot for ResaleNo reproduction or networking permitted wit

7、hout license from IHS-,-,-Approval of an American National Standard requires review by ANSI that therequirements for due process, consensus, and other criteria for approval havebeen met by the standards developer.Consensus is established when, in the judgement of the ANSI Board ofStandards Review, s

8、ubstantial agreement has been reached by directly andmaterially affected interests. Substantial agreement means much more thana simple majority, but not necessarily unanimity. Consensus requires that allviews and objections be considered, and that a concerted effort be madetowards their resolution.T

9、he use of American National Standards is completely voluntary; theirexistence does not in any respect preclude anyone, whether he has approvedthe standards or not, from manufacturing, marketing, purchasing, or usingproducts, processes, or procedures not conforming to the standards.The American Natio

10、nal Standards Institute does not develop standards andwill in no circumstances give an interpretation of any American NationalStandard. Moreover, no person shall have the right or authority to issue aninterpretation of an American National Standard in the name of the AmericanNational Standards Insti

11、tute. Requests for interpretations should beaddressed to the secretariat or sponsor whose name appears on the titlepage of this standard.CAUTION NOTICE: This American National Standard may be revised orwithdrawn at any time. The procedures of the American National StandardsInstitute require that act

12、ion be taken periodically to reaffirm, revise, orwithdraw this standard. Purchasers of American National Standards mayreceive current information on all standards by calling or writing the AmericanNational Standards Institute.American National StandardPublished byAmerican National Standards Institut

13、e, Inc.25 West 43rd Street, New York, NY 10036Copyright 2005 by Information Technology Industry Council (ITI)All rights reserved.No part of this publication may be reproduced in anyform, in an electronic retrieval system or otherwise,without prior written permission of ITI, 1250 Eye Street NW, Washi

14、ngton, DC 20005. Printed in the United States of AmericaCAUTION: The developers of this standard have requested that holders of patents that may berequired for the implementation of the standard disclose such patents to the publisher. However,neither the developers nor the publisher have undertaken

15、a patent search in order to identifywhich, if any, patents may apply to this standard. As of the date of publication of this standardand following calls for the identification of patents that may be required for the implementation ofthe standard, no such claims have been made. No further patent sear

16、ch is conducted by the de-veloper or publisher in respect to any standard it processes. No representation is made or impliedthat licenses are not required to avoid infringement in the use of this standard.Copyright American National Standards Institute Provided by IHS under license with ANSINot for

17、ResaleNo reproduction or networking permitted without license from IHS-,-,-iContentsPageForeword .xivIntroduction xvii1 Scope. 12 Normative references. 32.1 Approved references 32.1.1 ANSI References . 32.1.2 ISO References . 32.2 References under development. 32.3 Other references 43 Definitions, a

18、bbreviations, and conventions. 53.1 Definitions and abbreviations. 53.2 Conventions. 93.2.1 Precedence 93.2.2 Lists 93.2.3 Keywords . 93.2.4 Numbering . 103.2.5 Signal conventions. 103.2.6 Bit conventions. 113.2.7 State diagram conventions 123.2.8 Timing conventions 133.2.9 Byte ordering for data tr

19、ansfers . 133.2.10 Byte, word and DWORD Relationships . 154 General operational requirements (See Volume 1) . 165 I/O register descriptions (See Volume 1). 166 Command descriptions (See Volume 1) 167 Parallel interface physical and electrical requirements (See Volume 2). 168 Parallel interface signa

20、l assignments and descriptions (See Volume 2). 169 Parallel interface general operating requirements of the physical, data link, and transport layers (See Volume 2) 1610 Parallel interface register addressing (See Volume 2). 1611 Parallel interface transport Protocols (See Volume 2). 1612 Parallel i

21、nterface timing (See Volume 2) 1613 Serial interface general overview. 1713.1 Overview 1713.2 Sub-module operation 1813.3 Parallel ATA Emulation (Optional) . 1913.3.1 Software reset 20Copyright American National Standards Institute Provided by IHS under license with ANSINot for ResaleNo reproduction

22、 or networking permitted without license from IHS-,-,-iiPage13.3.2 Device 0-only emulation 2113.3.3 Device 0/Device 1 emulation (optional) . 2113.3.3.1 Software reset 2213.3.3.2 EXECUTE DEVICE DIAGNOSTICS 2213.3.3.3 Restrictions and limitations 2214 Serial interface physical layer 2314.1 Overview 23

23、14.1.1 List of services . 2314.2 Connectors specifications 2314.2.1 Overview 2314.2.1.1 General descriptions 2314.2.2 Connector drawings. 2514.2.2.1 Device plug connector . 2514.2.2.2 Signal cable receptacle connector. 2814.2.2.3 Signal host plug connector 3014.2.2.4 Host receptacle connector . 3014

24、.2.2.5 Power cable receptacle connector. 3214.2.3 Connector pinouts 3414.2.4 Backplane connector configuration and blind-mating tolerance 3514.2.5 Connector locations . 3614.2.6 Connector conformance requirements 3914.2.6.1 Signal. 3914.2.6.2 Housing and contact electrical requirements. 4514.2.6.3 M

25、echanical and environmental requirements 4614.2.6.4 Sample selection . 4714.2.6.5 Test sequence . 4814.3 Cable assemblies 4814.4 Phy (Physical layer electronics). 5014.4.1 Physical plant as a system 5014.4.1.1 Test bit patterns and sequence characteristics . 5014.4.1.2 Low transition density bit pat

26、tern sequences. 5114.4.1.3 High transition density bit pattern sequences 5214.4.1.4 Low frequency spectral content bit pattern sequences 5214.4.1.5 Simultaneous switching outputs bit pattern sequences . 5314.4.1.6 Composite bit pattern sequences 5314.4.2 Bit error rate testing - Informative 5414.4.2

27、.1 Error-burst-rate-thresholding measurement - Informative . 5414.4.2.2 Bit-error-rate measurements - Informative. 5414.4.3 Frame error rate testing . 5514.4.3.1 Frame error-rate patterns 5514.4.3.1.1 Loopback test 5514.4.4 Test requirements - non-compliant patterns 5514.4.5 Test requirements - comp

28、liant frame patterns . 5514.4.6 Test requirements - loopback 5614.4.6.1 Test requirements - loopback - far-end retimed. 5614.4.6.2 Test requirements - loopback - far-end analog (vendor specific) 5614.4.6.3 Test requirements - loopback - near-end analog (vendor specific) . 5614.4.7 Test Method - Data

29、 Rate Frequency Variation - SSC Profile 5714.4.8 Block diagram 58Copyright American National Standards Institute Provided by IHS under license with ANSINot for ResaleNo reproduction or networking permitted without license from IHS-,-,-iiiPage14.4.9 Electrical specifications 6114.4.10 Frame error-rat

30、e measurements 6514.4.11 Receiver Differential voltage 6514.4.12 Receiver Common-mode voltage. 6514.4.13 Transmitter Differential voltage 6514.4.14 Transmitter Common-mode voltage. 6514.4.15 Rise/fall times. 6514.5 Electrical features. 6714.5.1 Definitions 6714.5.2 Differential voltage/timing (EYE)

31、diagram . 6714.5.2.1 Jitter output/tolerance mask . 6814.5.2.2 Sampling differential noise budget. 7014.5.2.3 Jitter output 7014.5.2.3.1 Jitter measurements. 7014.5.3 Spread spectrum clocking (SSC). 7114.5.4 Common-mode biasing 7314.5.5 Matching. 7314.5.6 Out of band signaling . 7414.5.6.1 Idle bus

32、status 7514.5.6.2 Power-up and COMRESET sequences . 7614.5.6.2.1 Host power-up and COMRESET state machine 7614.5.6.2.2 Device power-up and COMRESET state machine 8214.5.6.2.3 Power-up and COMRESET timing. 8814.5.6.2.4 COMINIT sequence . 9014.5.6.2.5 COMWAKE 9214.5.6.2.6 Interface power states 9214.5

33、.6.2.7 Power-on sequence timing diagram. 9314.5.6.2.8 READY to Partial/Slumber . 9414.5.6.2.9 Partial/Slumber to READY . 9414.5.6.3 ON to Partial/Slumber 9414.5.6.3.1 Host initiated 9414.5.6.3.2 Detailed sequence . 9514.5.6.3.3 Device initiated. 9614.5.6.3.4 Detailed sequence . 9614.6 Elasticity buf

34、fer management. 9714.7 BIST (Built in self test) 9814.7.1 Loopback testing 9814.7.1.1 Loopback - Far-end retimed. 9814.7.1.2 Loopback - Far-end analog (Optional) . 9914.7.1.2.1 Loopback - Near-end analog (Optional). 10015 Serial interface Link layer. 10115.1 Overview 10115.1.1 Frame transmission 101

35、15.1.2 Frame receipt. 10115.2 Encoding method . 10115.2.1 Notation and conventions. 10115.2.2 Character code. 10315.2.2.1 Code construction 10315.2.2.2 The concept of running disparity 103Copyright American National Standards Institute Provided by IHS under license with ANSINot for ResaleNo reproduc

36、tion or networking permitted without license from IHS-,-,-ivPage15.2.2.3 Data encoding 10515.2.2.4 Encoding examples . 10515.2.2.5 8b/10b valid encoded characters. 10715.2.2.5.1 Data characters . 10715.2.2.5.2 Control characters . 11115.2.3 Transmission summary 11215.2.3.1 Transmission order 11215.2

37、.3.1.1 Bits within a byte 11215.2.3.1.2 Bytes within a DWORD 11215.2.3.1.3 Dwords within a frame . 11215.2.4 Reception. 11315.2.4.1 Disparity and the detection of a code violation 11315.3 Transmission Method 11515.4 Primitives . 11615.4.1 Overview 11615.4.1.1 Primitive disparity. 11615.4.1.2 Primiti

38、ve handshakes. 11615.4.2 Primitive descriptions. 11715.4.3 Primitive encoding . 11915.4.4 ALIGN primitive 12015.4.5 CONT primitive 12015.4.5.1 Scrambling of data following the CONT primitive 12115.4.6 DMAT primitive 12115.4.7 EOF primitive . 12215.4.8 HOLD/HOLDA primitives . 12215.4.8.1 Flow Control

39、 Signaling Latency . 12315.4.9 PMREQ_P, PMREQ_S, PMACK, and PMNAK primitives. 12415.4.10 R_ERR primitive 12415.4.11 R_IP primitive 12415.4.12 R_OK primitive. 12515.4.13 R_RDY primitive 12515.4.14 SOF primitive . 12515.4.15 SYNC primitive 12515.4.16 WTRM primitive . 12515.4.17 X_RDY primitive 12515.4

40、.18 Examples . 12515.5 CRC calculation . 13015.6 Scrambling. 13115.6.1 Frame content scrambling . 13115.6.1.1 Relationship between scrambling and CRC 13115.6.2 Repeated primitive suppression 13115.6.2.1 Relationship between scrambling of FIS data and repeated primitives 13115.7 Link layer state diag

41、rams. 13215.7.1.1 Link idle state diagram. 13215.7.1.2 Link transmit state diagram 13515.7.1.3 Link receive state diagram. 14515.7.1.4 Link power mode state diagram. 146Copyright American National Standards Institute Provided by IHS under license with ANSINot for ResaleNo reproduction or networking

42、permitted without license from IHS-,-,-vPage16 Serial interface Transport layer 15016.1 Transport layer overview 15016.1.1 FIS construction . 15016.1.2 FIS decomposition . 15016.2 Frame Information Structure ( FIS) 15016.3 Overview 15016.4 Payload content . 15016.5 FIS types 15016.5.1 Register - Hos

43、t to Device . 15116.5.1.1 Description . 15116.5.1.2 Transmission 15216.5.1.3 Reception. 15216.5.2 Register - Device to Host . 15316.5.2.1 Description - Register Device to Host FIS 15416.5.2.2 Transmission 15416.5.2.3 Reception. 15416.5.3 Set Device Bits - Device to Host 15516.5.3.1 Description Set D

44、evice Bits Device to Host FIS. 15516.5.3.2 Transmission 15516.5.3.3 Reception. 15616.5.4 DMA Activate - Device to Host. 15716.5.4.1 Description . 15716.5.4.2 Transmission 15716.5.4.3 Reception. 15716.5.5 First Party DMA Setup - Device to Host or Host to Device (Bidirectional) 15816.5.5.1 Description

45、 . 15816.5.5.2 Transmission 15916.5.5.3 Reception. 15916.5.6 BIST Activate - Bidirectional. 16016.5.6.1 Description . 16016.5.6.2 Transmission 16116.5.6.3 Reception. 16116.5.7 PIO Setup - Device to Host 16216.5.7.1 Description . 16216.5.7.2 Transmission of PIO Setup by Device Prior to a Data Transfe

46、r from Host to Device. 16316.5.7.3 Reception of PIO Setup by Host Prior to a Data Transfer from Host to Device. 16316.5.7.4 Transmission of PIO Setup by Device Prior to a Data Transfer from Device to Host. 16316.5.7.5 Reception of PIO Setup by Host Prior to a Data Transfer from Device to Host. 16316

47、.5.8 Data - Host to Device or Device to Host (Bidirectional) . 16416.5.8.1 Description . 16416.5.8.2 Transmission 16416.5.8.3 Reception. 16516.6 Host transport states 16616.6.1 Host transport idle state diagram . 166Copyright American National Standards Institute Provided by IHS under license with A

48、NSINot for ResaleNo reproduction or networking permitted without license from IHS-,-,-viPage16.6.2 Host Transport transmit command FIS diagram 16916.6.3 Host Transport transmit control FIS diagram. 17116.6.4 Host Transport transmit First Party DMA Setup -Device to Host or Host to Device FIS state di

49、agram . 17216.6.5 Host Transport transmit BIST Activate FIS 17416.6.6 Host Transport decompose Register FIS diagram 17516.6.7 Host Transport decompose a Set Device Bits FIS state diagram 17616.6.8 Host Transport decompose a DMA Activate FIS diagram and DMA Data Transfer 17716.6.9 Host Transport decompose a PIO Setup FIS state diagram . 18016.6.10 Host Transport decompose a First Party DMA Setup