ANSI INCITS 370-2004 Information Technology - ATA ATAPI Host Adapters Standard (ATA - Adapter).pdf

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1、American National StandardDeveloped byfor Information Technology ATA/ATAPI Host Adapters Standard (ATA - Adapter)ANSI INCITS 370-2004ANSIINCITS370-2004ANSIINCITS 370-2004American National Standardfor Information Technology -ATA/ATAPI Host Adapters Standard(ATA - Adapter)SecretariatInformation Techno

2、logy Industry CouncilApproved February 19, 2004American National Standards Institute, Inc.AbstractThis standard specifies the Host System Interface used to control AT Attachment Interface devices. It pro-vides a common Programming interface for systems manufacturers, system integrators, software sup

3、pli-ers, and suppliers of intelligent storage devices. Approval of an American National Standard requires review by ANSI that therequirements for due process, consensus, and other criteria for approval havebeen met by the standards developer.Consensus is established when, in the judgement of the ANS

4、I Board ofStandards Review, substantial agreement has been reached by directly andmaterially affected interests. Substantial agreement means much more thana simple majority, but not necessarily unanimity. Consensus requires that allviews and objections be considered, and that a concerted effort be m

5、adetowards their resolution.The use of American National Standards is completely voluntary; theirexistence does not in any respect preclude anyone, whether he has approvedthe standards or not, from manufacturing, marketing, purchasing, or usingproducts, processes, or procedures not conforming to the

6、 standards.The American National Standards Institute does not develop standards andwill in no circumstances give an interpretation of any American NationalStandard. Moreover, no person shall have the right or authority to issue aninterpretation of an American National Standard in the name of the Ame

7、ricanNational Standards Institute. Requests for interpretations should beaddressed to the secretariat or sponsor whose name appears on the titlepage of this standard.CAUTION NOTICE: This American National Standard may be revised orwithdrawn at any time. The procedures of the American National Standa

8、rdsInstitute require that action be taken periodically to reaffirm, revise, orwithdraw this standard. Purchasers of American National Standards mayreceive current information on all standards by calling or writing the AmericanNational Standards Institute.American National StandardPublished byAmerica

9、n National Standards Institute, Inc.25 West 43rd Street, New York, NY 10036Copyright 2004 by Information Technology Industry Council (ITI)All rights reserved.No part of this publication may be reproduced in anyform, in an electronic retrieval system or otherwise,without prior written permission of I

10、TI, 1250 Eye Street NW, Washington, DC 20005. Printed in the United States of AmericaCAUTION: The developers of this standard have requested that holders of patents that may be re-quired for the implementation of the standard disclose such patents to the publisher. However, nei-ther the developers n

11、or the publisher have undertaken a patent search in order to identify which, ifany, patents may apply to this standard. As of the date of publication of this standard, followingcalls for the identification of patents that may be required for the implementation of the standard,notice of one or more s

12、uch claims has been received. By publication of this standard, no positionis taken with respect to the validity of this claim or of any rights in connection therewith. The knownpatent holder(s) has (have), however, filed a statement of willingness to grant a license underthese rights on reasonable a

13、nd nondiscriminatory terms and conditions to applicants desiring to ob-tain such a license. Details may be obtained from the publisher. No further patent search is con-ducted by the developer or publisher in respect to any standard it processes. No representation ismade or implied that this is the o

14、nly license that may be required to avoid infringement in the use ofthis standard.iContentsPageForeword .ivIntroduction vii1 Scope . 12 Normative References . 12.1 Content Imported from Normative Standards . 12.2 Industry Standard References 13 Definitions, Abbreviations, and Conventions 23.1 Defini

15、tions and Abbreviations 23.2 Conventions 54 ATA Host Adapters 74.1 Adapter Types. 74.2 Adapter Modes 75 ISA Bus Adapter. 85.1 Mode of Operation 85.2 Detection . 85.3 Adapter Set Up 85.4 ATA Bus Timings 85.5 Electrical and Physical 85.6 Registers. 86 PCI Compatibility and PCI-Native Mode Bus Master A

16、dapters 86.1 Mode of Operation 86.2 Detection . 86.3 Adapter Set Up 86.4 ATA Bus Timings 96.5 Electrical and Physical 96.6 PCI Registers 96.7 ATA Bus Master Registers 126.8 Interrupt Line Considerations 156.9 Bus Master Operation . 157 Automatic Direct Memory Access (ADMA) Adaptors - General Descrip

17、tion 177.1 Background . 177.2 The ADMA Engine 177.3 ADMA Overview 187.4 ADMA PCI Registers. 22iiPage7.5 ADMA Registers 317.6 Auto DMA Mode Data Structures 377.7 ADMA Operation. 447.8 Host Operation 487.9 Resets. 50AnnexesA Programming Guidelines 51B PCI Compatibility and PCI-Native Mode Bus Master A

18、dapter Configuration 55Tables1 Compatibility Mode Standard I/O Register Addresses. 72 PCI Compatibility and PCI-Native Mode Bus Master Adapters Configuration Registers 93 PCI Compatibility and PCI-Native Mode Bus Master Adapters Class Code Registers. 94 PCI Adapter bit definitions in Programming Int

19、erface Byte 105 ATA Bus Master Register Offsets 126 ATA Bus Master Command Register. 137 Bus Master ATA Status Register . 148 PRD Table Pointer Register. 159 Physical Region Descriptor Table Entry. 1510 Adapter Bus Master Status Register bits . 1611 ADMA PCI Configuration Space Header Registers . 23

20、12 ADMA PCI Command Register 2413 ADMA PCI Status Register 2414 ADMA PCI Class Code 2515 ADMA Power Management Registers . 2816 ADMA Power Management Capability Register 2917 ADMA Power Management Control/Status Register . 2918 ADMA Power Management State Control bits. 2919 ADMA Memory Mapped Regist

21、ers. 3220 ADMA Control Register 3421 ADMA Status Register . 3522 CPB Structure 3823 ATA Register Field. 4024 APRD Data Structure. 42iiiPage25 PCI Configuration Registers. 5526 ATA Timing Register 5627 Device 1 ATA Timing Register . 5728 UDMA Control Register 5829 UDMA Timing Register. 5930 UDMA Cont

22、rol Register 60Figures1 State Diagram Convention . 62 ADMA Data Structures . 203 Power Management State Transitions . 304 CPB States. 435 ADMA State Transitions . 456 Host Software States 48ivForeword (This foreword is not part of American National Standard ANSI INCITS 370-2004.)This standard was de

23、veloped by Technical Committee T13 on ATA Storage Inter-faces of the InterNational Committee for Information Technology Standards(INCITS), starting in 2001. This document includes two annexes that are informativeand are not considered part of the standard.Requests for interpretation, suggestions for

24、 improvement and addenda, or defect re-ports are welcome. They should be sent to the INCITS Secretariat, Information Tech-nology Industry Council, 1250 Eye Street, NW, Suite 200, Washington, DC 20005-3922.This standard was processed and approved for submittal to ANSI by the InterNation-al Committee

25、for Information Technology Standards, INCITS. Committee approval ofthe standard does not necessarily imply that all committee members voted for ap-proval. At the time it approved this standard, the INCITS Committee had the followingmembers:Karen Higginbottom, ChairJennifer Garner, SecretaryOrganizat

26、ion Represented Name of RepresentativeApple Computer, Inc. David MichaelFarance, Inc . Frank FaranceHewlett-Packard Company. Karen HigginbottomScott Jameson (Alt.)Steve Mills (Alt.)EIA Edward Mikoski, Jr.Suan Hoyler (Alt.)IBM Corporation . Ronald F. SillettiInstitute for Certification of Computer Pr

27、ofessionals Kenneth M. ZemrowskiThomas Kurihara (Alt.)IEEE . Judith GormanRichard Holleman (Alt.)Robert Pritchard (Alt.)Intel Corporation. Philip WennblomDave Thewlis (Alt.)Microsoft Corporation . Mike KsarFrank Camara (Alt.)National Institute of Standards the device used bits 0-6. This register is

28、no longer used in the ATA standard. 4.2.1.2 PCI-Native Mode This mode is only applicable to adapters bridging to the PCI bus. In this mode the control of the transfer is through the ATA Command and Control Block Registers and registers in the adapter. The addresses of the Command or Control block ar

29、e defined in the Base Address Register (BAR) of the adapter and are defined by ANSI INCITS 370-2004 8 the Host software. There is only one Host interrupt line for all the channels attached to an adapter. There is no restriction on the number of adapters there can be in the system. 4.2.2 ADMA Mode In

30、 this mode the ATA Command and Control Block registers are not accessible to the Host. Control is exercised through a data structure held in host memory and adapter registers. 5 ISA Bus Adapter This type of adapter is commonly called a paddle card for use in PC compatible systems. The function of th

31、e adapter is to decode the I/O addresses appropriate to the channels it controls. 5.1 Mode of Operation Only operates in Compatibility Mode. 5.2 Detection There is no standard method to detect the presence of this type of adapter. Software may be able to detect the presence of ATA drives by examinin

32、g the ATA registers at the standard I/O addresses and thereby infer the presence of an adapter. 5.3 Adapter Set Up There is no standard method used to set up these adapters. In most cases the I/O address banks are set by hard jumpers or by vendor specific registers. 5.4 ATA Bus Timings ISA timings.

33、No programmable timing is available. 5.5 Electrical and Physical The electrical and physical specifications of the ATA bus are defined in the ATA Standard; the ISA bus characteristics are defined in the ISA Spec. 5.6 Registers The compatibility register set shall be implemented. 6 PCI Compatibility

34、and PCI-Native Mode Bus Master Adapters PCI Adapters conforming to this standard may operate in Compatibility or Native-PCI Mode. Some adapters can be configured to operate in either mode; some are fixed to one of the modes. The mode configuration may be determined from the PCI Configuration registe

35、rs. 6.1 Mode of Operation 6.1.1 Compatibility Mode Adapters operating in Compatibility Mode support two channels conforming to the Primary and Secondary channel address and have a separate IRQ for each channel. 6.1.2 PCI-Native Mode Adapters operating in Compatibility Mode may support one or two cha

36、nnels. 6.2 Detection The Class Code fields determine the capabilities. 6.3 Adapter Set Up The Class Code fields determine the capabilities of an adapter and may be used to configure the channels to Compatibility or PCI-Native mode. The PCI BARs may be used to configure and determine the I/O addresse

37、s to use to access the ATA and adapter registers. ANSI INCITS 370-2004 9 6.4 ATA Bus Timings Determination of the ATA PIO timings, DMA protocols and DMA timings supported is vendor specific. Consequently configuring these attributes is vendor specific. 6.5 Electrical and Physical The electrical and

38、physical specifications of the ATA bus are defined in the ATA Standard; the PCI bus characteristics are defined in the PCI SPEC specification. 6.6 PCI Registers The PCI Adapter implements a subset of the PCI standard type 00h configuration header register set. All registers have the standard meaning

39、 as defined in the PCI Specification, Issue 2.2. The registers with specific meanings with respect to this standard are defined below. Register contents that are otherwise defined in the PCI standard are indicates as “PCI”. Fields marked reserved are all zeros and read only. Table 2 PCI Compatibilit

40、y and PCI-Native Mode Bus Master Adapters Configuration Registers Byte Offset Bits 31-24 Bits 23-16 Bits 15-8 Bits 7-0 00h PCI 04h PCI 08h Class Code PCI 0Ch PCI 10h Base Address 0 - Base Address of Cmd-Block Regs, ATA Channel X 14h Base Address 1 - Base Address of Control Regs, ATA Channel X 18h Ba

41、se Address 2 - Base Address of Cmd-Block Regs, ATA Channel Y 1Ch Base Address 3 - Base Address of Control Regs, ATA Channel Y 20h Base Address 4 - Base Address of ATA Bus Master Registers 24h Base Address 5 Vendor Specific 28h PCI 2Ch Subsystem ID PCI 30h PCI 34h PCI 38h PCI 3Ch PCI Interrupt Line 6

42、.6.1 PCI Class Code Address Offset 09h Size 24 bits Table 3 PCI Compatibility and PCI-Native Mode Bus Master Adapters Class Code Registers Byte Offset Description Attribute Value 09h Programming Interface Code See Table 4 See Table 4 0Ah Sub-class Code Read Only 01h IDE 0Bh Base-Class Code Read Only

43、 01h Mass Storage ANSI INCITS 370-2004 10 6.6.1.1 Programming Interface Code Table 4 defines the usage and values of the Programming and Interface Byte. Table 4 PCI Adapter bit definitions in Programming Interface Byte Bit Read/write Description 0 Implementation dependent Determines the mode that th

44、e primary ATA channel is operating in. Clearing this bit to zero corresponds to compatibility, setting the bit to one means PCI-native mode. This bit is implemented as read-only if the channel supports only one mode, or read-write if both modes are supported. For implementations that support both mo

45、des the power on and hardware reset states are vendor specific. 1 Read Only This bit indicates whether or not the primary channel has a fixed mode of operation. If this bit is cleared to zero, the mode is fixed and is determined by the read-only value of bit 0. If this bit is set to one, the channel

46、 supports both modes and may be set to either mode by writing bit 0. 2 Implementation dependent Determines the mode that the secondary ATA channel is operating in. Clearing this bit to zero corresponds to compatibility, setting the bit to one means PCI-native mode. This bit is implemented as read-on

47、ly if the channel supports only one mode, or read-write if both modes are supported. For implementations that support both modes the power on and hardware reset states are vendor specific. 3 Read Only This bit indicates whether or not the secondary channel has a fixed mode of operation. If this bit

48、is cleared to zero, the mode is fixed and is determined by the read-only value of bit 2. If this bit is set to one, the channel supports both modes and may be set to either mode by writing bit 2. 4-6 Read Only Reserved and shall be cleared to zero. 7 Read Only This bit shall indicate that the adapte

49、r can do bus master operation when it is set to one. This bit shall indicate that the adapter is not capable of bus master operation when it is cleared to 0. 6.6.2 PCI Base Address Registers (BAR) Base Address Registers 0-3 have Bit zero hard-wired to one to indicate I/O space. Initialization of the following BARs is described in the PCI Specification 6.6.2.1 PCI Base Address Register (BAR) 0 This is the base address for the command block registers for ATA Channel X. Address Offset 10h Default Value 00000001h When operating in Compatibility Mode any write t