IEEE 1364-2005 en Standard Verilog Hardware Description Language (IEEE Computer Society Document)《Verilog的硬件描述语言》.pdf

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1、IEEE Std 1364-2005(Revision of IEEE Std 1364-2001)IEEE Standard for VerilogHardware Description LanguageI E E E3 Park Avenue New York, NY10016-5997, USA7April 2006IEEE Computer SocietySponsored by theDesign Automation Standards CommitteeThe Institute of Electrical and Electronics Engineers, Inc.3 Pa

2、rk Avenue, New York, NY 10016-5997, USACopyright 2006 by the Institute of Electrical and Electronics Engineers, Inc.All rights reserved. Published 7 April 2006. Printed in the United States of America.IEEE is a registered trademark in the U.S. Patent the communication of hardware design data; and th

3、emaintenance, modification, and procurement of hardware. The primary audiences for this standardare the implementors of tools supporting the language and advanced users of the language.Keywords: computer, computer languages, digital systems, electronic systems, hardware, hard-ware description langua

4、ges, hardware design, HDL, PLI, programming language interface, Verilog,Verilog HDL, Verilog PLIIEEE Standards documents are developed within the IEEE Societies and the Standards CoordinatingCommittees of the IEEE Standards Association (IEEE-SA) Standards Board. The IEEE develops its standardsthroug

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19、r, Customer Service,222 Rosewood Drive, Danvers, MA 01923 USA; +1 978 750 8400. Permission to photocopy portions of any indi-vidual standard for educational classroom use can also be obtained through the Copyright Clearance Center.NOTEAttention is called to the possibility that implementation of thi

20、s standard may require use of subjectmatter covered by patent rights. By publication of this standard, no position is taken with respect to theexistence or validity of any patent rights in connection therewith. The IEEE shall not be responsible foridentifying patents for which a license may be requi

21、red by an IEEE standard or for conducting inquiries into thelegal validity or scope of those patents that are brought to its attention.Copyright 2006 IEEE. All rights reserved. iiiIntroductionThe Verilog hardware description language (HDL) became an IEEE standard in 1995 as IEEE Std 1364-1995. It wa

22、s designed to be simple, intuitive, and effective at multiple levels of abstraction in a standardtextual format for a variety of design tools, including verification simulation, timing analysis, test analysis,and synthesis. It is because of these rich features that Verilog has been accepted to be th

23、e language of choiceby an overwhelming number of integrated circuit (IC) designers.Verilog contains a rich set of built-in primitives, including logic gates, user-definable primitives, switches,and wired logic. It also has device pin-to-pin delays and timing checks. The mixing of abstract levels ise

24、ssentially provided by the semantics of two data types: nets and variables. Continuous assignments, inwhich expressions of both variables and nets can continuously drive values onto nets, provide the basicstructural construct. Procedural assignments, in which the results of calculations involving va

25、riable and netvalues can be stored into variables, provide the basic behavioral construct. A design consists of a set of mod-ules, each of which has an input/output (I/O) interface, and a description of its function, which can be struc-tural, behavioral, or a mix. These modules are formed into a hie

26、rarchy and are interconnected with nets.The Verilog language is extensible via the programming language interface (PLI) and the Verilog proce-dural interface (VPI) routines. The PLI/VPI is a collection of routines that allows foreign functions to accessinformation contained in a Verilog HDL descript

27、ion of the design and facilitates dynamic interaction withsimulation. Applications of PLI/VPI include connecting to a Verilog HDL simulator with other simulationand computer-assisted design (CAD) systems, customized debugging tasks, delay calculators, andannotators.The language that influenced Veril

28、og HDL the most was HILO-2, which was developed at Brunel Univer-sity in England under a contract to produce a test generation system for the British Ministry of Defense.HILO-2 successfully combined the gate and register transfer levels of abstraction and supported verificationsimulation, timing ana

29、lysis, fault simulation, and test generation.In 1990, Cadence Design Systems placed the Verilog HDL into the public domain and the independentOpen Verilog International (OVI) was formed to manage and promote Verilog HDL. In 1992, the Board ofDirectors of OVI began an effort to establish Verilog HDL

30、as an IEEE standard. In 1993, the first IEEEworking group was formed; and after 18 months of focused efforts, Verilog became an IEEE standard asIEEE Std 1364-1995. After the standardization process was complete, the IEEE P1364 Working Group started looking for feed-back from IEEE 1364 users worldwid

31、e so the standard could be enhanced and modified accordingly. Thisled to a five-year effort to get a much better Verilog standard in IEEE Std 1364-2001.With the completion of IEEE Std 1364-2001, work continued in the larger Verilog community to identifyoutstanding issues with the language as well as

32、 ideas for possible enhancements. As Accellera began work-ing on standardizing SystemVerilog in 2001, additional issues were identified that could possibly have led toincompatibilities between Verilog 1364 and SystemVerilog. The IEEE P1364 Working Group was estab-lished as a subcomittee of the Syste

33、mVerilog P1800 Working Group to help ensure consistent resolution ofsuch issues. The result of this collaborative work is this standard, IEEE Std 1364-2005.This introduction is not a part of IEEE Std 1364-2005, IEEE Standard for VerilogHardware Description Language.iv Copyright 2006 IEEE. All rights

34、 reserved.Notice to usersErrataErrata, if any, for this and all other standards can be accessed at the following URL: http:/stan-dards.ieee.org/reading/ieee/updates/errata/index.html. Users are encouraged to check this URL for errataperiodically.InterpretationsCurrent interpretations can be accessed

35、 at the following URL: http:/standards.ieee.org/reading/ieee/interp/index.html.PatentsAttention is called to the possibility that implementation of this standard may require use of subject mattercovered by patent rights. By publication of this standard, no position is taken with respect to the exist

36、ence orvalidity of any patent rights in connection therewith. The IEEE shall not be responsible for identifyingpatents or patent applications for which a license may be required to implement an IEEE standard or forconducting inquiries into the legal validity or scope of those patents that are brough

37、t to its attention.ParticipantsAt the time this standard was completed, the IEEE P1364 Working Group had the following membership:Johny Srouji, IBM, IEEE SystemVerilog Working Group Chair Tom Fitzpatrick, Mentor Graphics Corporation, Chair Neil Korpusik, Sun Microsystems, Inc., Co-chair Stuart Suthe

38、rland, Sutherland HDL, Inc., Editor Shalom Bresticker, Intel Corporation, Editor through February 2005 The Errata Task Force had the following membership:Karen Pieper, Synopsys, Inc., Chair Kurt Baty, WFSDB ConsultingStefen Boyd, Boyd TechnologyShalom Bresticker, Intel CorporationDennis Brophy, Ment

39、or Graphics CorporationCliff Cummings, Sunburst Design, Inc.Charles Dawson, Cadence Design Systems, Inc.Tom Fitzpatrick, Mentor Graphics CorporationRonald Goodstein, First Shot Logic Simulation andDesignMark Hartoog, Synopsys, Inc.James Markevitch, Evergreen Technology GroupDennis Marsa, XilinxFranc

40、oise Martinolle, Cadence Design Systems, Inc.Mike McNamara, Verisity, Ltd.Don Mills, LCDM EngineeringAnders Nordstrom, Cadence Design Systems, Inc.Karen Pieper, Synopsys, Inc.Brad Pierce, Synopsys, Inc.Steven Sharp, Cadence Design Systems, Inc.Alec Stanculescu, Fintronic USA, Inc.Stuart Sutherland,

41、Sutherland HDL, Inc.Gordon Vreugdenhil, Mentor Graphics CorporationJason Woolf, Cadence Design Systems, Inc.Copyright 2006 IEEE. All rights reserved. vThe Behavioral Task Force had the following membership:Steven Sharp, Cadence Design Systems, Inc., Chair The PLI Task Force had the following members

42、hip:Charles Dawson, Cadence Design Systems, Inc., Chair Ghassan Khoory, Synopsys, Inc., Co-chair In addition, the working group wishes to recognize the substantial efforts of past contributors:Michael McNamara, Cadence Design Systems, Inc., 1364 Working Group past chair (through September 2004) Alec

43、 Stanculescu, Fintronic USA, 1364 Working Group past vice-chair (through June 2004) Stefen Boyd, Boyd Technology, ETF past co-chair (through November 2004) The following members of the entity balloting committee voted on this standard. Balloters may have votedfor approval, disapproval, or abstention

44、. Kurt Baty, WFSDB ConsultingStefen Boyd, Boyd TechnologyShalom Bresticker, Intel CorporationDennis Brophy, Mentor Graphics CorporationCliff Cummings, Sunburst Design, Inc.Steven Dovich, Cadence Design Systems, Inc.Tom Fitzpatrick, Mentor Graphics CorporationRonald Goodstein, First Shot Logic Simula

45、tion andDesignKeith Gover, Mentor Graphics CorporationMark Hartoog, Synopsys, Inc.Ennis Hawk, Jeda TechnologiesAtsushi Kasuya, Jeda TechnologiesJay Lawrence, Cadence Design Systems, Inc.Francoise Martinolle, Cadence Design Systems, Inc.Kathryn McKinley, Cadence Design Systems, Inc.Michael McNamara,

46、Verisity, Ltd.Don Mills, LCDM EngineeringMehdi Mohtashemi, Synopsys, Inc.Karen Pieper, Synopsys, Inc.Brad Pierce, Synopsys, Inc.Dave Rich, Mentor Graphics CorporationSteven Sharp, Cadence Design Systems, Inc.Alec Stanculescu, Fintronic, USAStuart Sutherland, Sutherland HDL, Inc.Gordon Vreugdenhil, M

47、entor Graphics CorporationTapati Basu, Sysnopsys, Inc.Steven Dovich, Cadence Design Systems, Inc.Ralph Duncan, Mentor Graphics CorporationJim Garnett, Mentor Graphics CorporationJoao Geada, CLK Design AutomationAndrzej Litwiniuk, Synopsys, Inc.Francoise Martinolle, Cadence Design Systems, Inc.Sachch

48、idananda Patel, Synopsys, Inc.Michael Rohleder, Freescale Semiconductor, Inc.Rob Slater, Freescale Semiconductor, Inc.John Stickley, Mentor Graphics CorporationStuart Sutherland, Sutherland HDL, Inc.Bassam Tabbara, Novas Software, Inc.Jim Vellenga, Cadence Design Systems, Inc.Doug Warmke, Mentor Gra

49、phics CorporationAccelleraBluespec, Inc.Cadence Design Systems, Inc.Fintronic U.S.A.IBMInfineon TechnologiesIntel CorporationMentor Graphics CorporationSun Microsystems, Inc.Sunburst Design, Inc.Sutherland HDL, Inc.Synopsys, Inc.vi Copyright 2006 IEEE. All rights reserved.When the IEEE-SA Standards Board approved this standard on 8 November 2005, it had the followingmembership:Steve M. Mills, ChairRichard H. Hulett, Vice ChairDon Wright, Past ChairJudith Gorman, Secretary*Member EmeritusAlso included are the following nonvoting IEEE-SA Standards Board liaisons:Satish K. Aggarwa