IEEE 1364-2004 en Behavioural languages - Part 4 Verilog hardware description language (IEEE Computer Society Document)《行为语言 第4部分 Verilog邮件描述语言(IEEE计算机协会文件)》.pdf

《IEEE 1364-2004 en Behavioural languages - Part 4 Verilog hardware description language (IEEE Computer Society Document)《行为语言 第4部分 Verilog邮件描述语言(IEEE计算机协会文件)》.pdf》由会员分享，可在线阅读，更多相关《IEEE 1364-2004 en Behavioural languages - Part 4 Verilog hardware description language (IEEE Computer Society Document)《行为语言 第4部分 Verilog邮件描述语言(IEEE计算机协会文件)》.pdf（862页珍藏版）》请在麦多课文档分享上搜索。

1、 INTERNATIONAL STANDARD IEC 61691-4First edition 2004-10IEEE 1364 Behavioural languages Part 4: Verilog hardware description language Reference number IEC 61691-4(E):2004 IEEE Std. 1364(E):2001 Publication numbering As from 1 January 1997 all IEC publications are issued with a designation in the 600

2、00 series. For example, IEC 34-1 is now referred to as IEC 60034-1. Consolidated editions The IEC is now publishing consolidated versions of its publications. For example, edition numbers 1.0, 1.1 and 1.2 refer, respectively, to the base publication, the base publication incorporating amendment 1 an

3、d the base publication incorporating amendments 1 and 2. Further information on IEC publications The technical content of IEC publications is kept under constant review by the IEC, thus ensuring that the content reflects current technology. Information relating to this publication, including its val

4、idity, is available in the IEC Catalogue of publications (see below) in addition to new editions, amendments and corrigenda. Information on the subjects under consideration and work in progress undertaken by the technical committee which has prepared this publication, as well as the list of publicat

5、ions issued, is also available from the following: IEC Web Site (www.iec.ch) Catalogue of IEC publications The on-line catalogue on the IEC web site (www.iec.ch/searchpub) enables you to search by a variety of criteria including text searches, technical committees and date of publication. On-line in

6、formation is also available on recently issued publications, withdrawn and replaced publications, as well as corrigenda. IEC Just Published This summary of recently issued publications (www.iec.ch/online_news/ justpub) is also available by email. Please contact the Customer Service Centre (see below

7、) for further information. Customer Service Centre If you have any questions regarding this publication or need further assistance, please contact the Customer Service Centre: Email: custserviec.ch Tel: +41 22 919 02 11 Fax: +41 22 919 03 00 Behavioural languages Part 4: Verilog hardware description

8、 language INTERNATIONAL STANDARD IEC 61691-4First edition 2004-10IEEE 1364 Commission Electrotechnique Internationale International Electrotechnical Commission Copyright IEEE 2004 All rights reserved IEEE is a registered trademark in the U.S. Patent & Trademark Office, owned by the Institute of Elec

9、trical and Electronics Engineers, Inc. No part of this publication may be reproduced or utilized in any form or by any means, electronic or mechanical, including photocopying and microfilm, without permission in writing from the publisher. International Electrotechnical Commission, 3, rue de Varemb,

10、 PO Box 131, CH-1211 Geneva 20, Switzerland Telephone: +41 22 919 02 11 Telefax: +41 22 919 03 00 E-mail: inmailiec.ch Web: www.iec.ch The Institute of Electrical and Electronics Engineers, Inc, 3 Park Avenue, New York, NY 10016-5997, USA Telephone: +1 732 562 3800 Telefax: +1 732 562 1571 E-mail: s

11、tds-infoieee.org Web: www.standards.ieee.org Copyright 2001 IEEE. All rights reserved.vii1.Overview. 25 1.1Objectives of this standard 25 1.2Conventions used in this standard. 25 1.3Syntactic description. 26 1.4Contents of this standard. 26 1.5Header file listings 28 1.6Examples. 29 1.7Prerequisites

12、 29 2.Lexical conventions30 2.1Lexical tokens.30 2.2White space.30 2.3Comments.30 2.4Operators.30 2.5Numbers30 2.5.1Integer constants.31 2.5.2Real constants 34 2.5.3Conversion. 34 2.6Strings34 2.6.1String variable declaration.35 2.6.2String manipulation35 2.6.3Special characters in strings.35 2.7Ide

13、ntifiers, keywords, and system names36 2.7.1Escaped identifiers.36 2.7.2Generated identifiers37 2.7.3Keywords.37 2.7.4System tasks and functions37 2.7.5Compiler directives38 2.8Attributes38 2.8.1Examples39 2.8.2Syntax40 3.Data types.44 3.1Value set.44 3.2Nets and variables 44 3.2.1Net declarations.4

14、4 3.2.2Variable declarations.46 3.3Vectors.47 3.3.1Specifying vectors47 3.3.2Vector net accessibility48 3.4Strengths48 3.4.1Charge strength48 3.4.2Drive strength.48 3.5Implicit declarations.49 3.6Net initialization.49 3.7Net types49 3.7.1Wire and tri nets.49 3.7.2Wired nets50 2Published by IEC under

15、 licence from IEEE. 2004 IEEE. All rights reserved. IEC 61691-4:2004(E) IEEE 1364-2001(E) CONTENTS IEEE Introduction 23 FOREWORD 19 viiiCopyright 2001 IEEE. All rights reserved.3.7.3Trireg net50 3.7.4Tri0 and tri1 nets54 3.7.5Supply nets.55 3.8regs.55 3.9Integers, reals, times, and realtimes.55 3.9.

16、1Operators and real numbers.56 3.9.2Conversion.56 3.10 Arrays57 3.10.1Net arrays.57 3.10.2reg and variable arrays.57 3.10.3Memories.57 3.11 Parameters.58 3.11.1Module parameters.59 3.11.2Local parameterslocalparam 60 3.11.3Specify parameters. 61 3.12 Name spaces62 4.Expressions 64 4.1Operators64 4.1

17、.1Operators with real operands.65 4.1.2Binary operator precedence. 66 4.1.3Using integer numbers in expressions.67 4.1.4Expression evaluation order.67 4.1.5Arithmetic operators68 4.1.6Arithmetic expressions with regs and integers69 4.1.7Relational operators.70 4.1.8Equality operators70 4.1.9Logical

18、operators.71 4.1.10 Bit-wise operators.71 4.1.11 Reduction operators72 4.1.12 Shift operators.73 4.1.13 Conditional operator.74 4.1.14 Concatenations75 4.1.15 Event or.76 4.2Operands76 4.2.1Vector bit-select and part-select addressing76 4.2.2Array and memory addressing.78 4.2.3Strings79 4.3Minimum,

19、typical, and maximum delay expressions81 4.4Expression bit lengths83 4.4.1Rules for expression bit lengths.83 4.4.2An example of an expression bit-length problem84 4.4.3Example of self-determined expressions.85 4.5Signed expressions.86 4.5.1Rules for expression types.86 4.5.2Steps for evaluating an

20、expression.86 4.5.3Steps for evaluating an assignment87 4.5.4Handling X and Z in signed expressions.87 5.Scheduling semantics.88 5.1Execution of a model.88 5.2Event simulation 88 3Published by IEC under licence from IEEE. 2004 IEEE. All rights reserved. IEC 61691-4:2004(E) IEEE 1364-2001(E) Copyrigh

21、t 2001 IEEE. All rights reserved.ix 5.3The stratified event queue88 5.4The Verilog simulation reference model.89 5.4.1Determinism.90 5.4.2Nondeterminism.90 5.5Race conditions90 5.6Scheduling implication of assignments.90 5.6.1Continuous assignment91 5.6.2Procedural continuous assignment.91 5.6.3Bloc

22、king assignment91 5.6.4Nonblocking assignment91 5.6.5Switch (transistor) processing91 5.6.6Port connections.92 5.6.7Functions and tasks92 6.Assignments.93 6.1Continuous assignments.93 6.1.1The net declaration assignment94 6.1.2The continuous assignment statement.94 6.1.3Delays96 6.1.4Strength96 6.2P

23、rocedural assignments97 6.2.1Variable declaration assignment97 6.2.2Variable declaration syntax98 7.Gate and switch level modeling.99 7.1Gate and switch declaration syntax99 7.1.1The gate type specification. 101 7.1.2The drive strength specification 101 7.1.3The delay specification. 102 7.1.4The pri

24、mitive instance identifier102 7.1.5The range specification. 102 7.1.6Primitive instance connection list. 103 7.2and, nand, nor, or, xor, and xnor gates105 7.3buf and not gates106 7.4bufif1, bufif0, notif1, and notif0 gates.107 7.5MOS switches. 109 7.6Bidirectional pass switches110 7.7CMOS switches.1

25、10 7.8pullup and pulldown sources.111 7.9Logic strength modeling112 7.10 Strengths and values of combined signals113 7.10.1Combined signals of unambiguous strength113 7.10.2Ambiguous strengths: sources and combinations114 7.10.3Ambiguous strength signals and unambiguous signals.119 7.10.4Wired logic

26、 net types.123 7.11 Strength reduction by nonresistive devices 126 7.12 Strength reduction by resistive devices126 7.13 Strengths of net types.126 7.13.1tri0 and tri1 net strengths126 7.13.2trireg strength126 7.13.3supply0 and supply1 net strengths126 4Published by IEC under licence from IEEE. 2004

27、IEEE. All rights reserved. IEC 61691-4:2004(E) IEEE 1364-2001(E) xCopyright 2001 IEEE. All rights reserved.7.14 Gate and net delays.127 7.14.1min:typ:max delays128 7.14.2trireg net charge decay.129 8.User-defined primitives (UDPs)131 8.1UDP definition.131 8.1.1UDP header133 8.1.2UDP port declaration

28、s133 8.1.3Sequential UDP initial statement.133 8.1.4UDP state table133 8.1.5Z values in UDP.134 8.1.6Summary of symbols.134 8.2Combinational UDPs.135 8.3Level-sensitive sequential UDPs.136 8.4Edge-sensitive sequential UDPs136 8.5Sequential UDP initialization137 8.6UDP instances139 8.7Mixing level-se

29、nsitive and edge-sensitive descriptions.140 8.8Level-sensitive dominance.141 9.Behavioral modeling142 9.1Behavioral model overview.142 9.2Procedural assignments143 9.2.1Blocking procedural assignments143 9.2.2The nonblocking procedural assignment.145 9.3Procedural continuous assignments.148 9.3.1The

30、 assign and deassign procedural statements.149 9.3.2The force and release procedural statements.150 9.4Conditional statement151 9.4.1If-else-if construct152 9.5Case statement.154 9.5.1Case statement with dont-cares157 9.5.2Constant expression in case statement.157 9.6Looping statements158 9.7Procedu

31、ral timing controls.160 9.7.1Delay control161 9.7.2Event control162 9.7.3Named events.162 9.7.4Event or operator163 9.7.5Implicit event_expression list164 9.7.6Level-sensitive event control.165 9.7.7Intra-assignment timing controls.166 9.8Block statements170 9.8.1Sequential blocks.170 9.8.2Parallel

32、blocks171 9.8.3Block names.172 9.8.4Start and finish times.172 9.9Structured procedures173 9.9.1Initial construct174 9.9.2Always construct174 5Published by IEC under licence from IEEE. 2004 IEEE. All rights reserved. IEC 61691-4:2004(E) IEEE 1364-2001(E) Copyright 2001 IEEE. All rights reserved.xi 1

33、0.Tasks and functions176 10.1 Distinctions between tasks and functions.176 10.2 Tasks and task enabling176 10.2.1Task declarations.177 10.2.2Task enabling and argument passing.178 10.2.3Task memory usage and concurrent activation180 10.3 Functions and function calling181 10.3.1Function declarations.

34、182 10.3.2Returning a value from a function.183 10.3.3Calling a function.184 10.3.4Function rules.184 10.3.5Use of constant functions.185 11.Disabling of named blocks and tasks.187 12.Hierarchical structures.190 12.1 Modules.190 12.1.1Top-level modules.192 12.1.2Module instantiation192 12.1.3Generat

35、ed instantiation194 12.2 Overriding module parameter values 204 12.2.1defparam statement206 12.2.2Module instance parameter value assignment.207 12.2.3Parameter dependence.209 12.3 Ports209 12.3.1Port definition209 12.3.2List of ports209 12.3.3Port declarations.210 12.3.4List of ports declarations21

36、2 12.3.5Connecting module instance ports by ordered list.212 12.3.6Connecting module instance ports by name213 12.3.7Real numbers in port connections214 12.3.8Connecting dissimilar ports.215 12.3.9Port connection rules.215 12.3.10 Net types resulting from dissimilar port connections216 12.3.11 Conne

37、cting signed values via ports217 12.4 Hierarchical names .217 12.5 Upwards name referencing.220 12.6 Scope rules .222 13.Configuring the contents of a design.224 13.1 Introduction.224 13.1.1Library notation.224 13.1.2Basic configuration elements.225 13.2 Libraries225 13.2.1Specifying libraries - the

38、 library map file225 13.2.2Using multiple library mapping files.227 13.2.3Mapping source files to libraries227 13.3 Configurations.227 13.3.1Basic configuration syntax.227 13.3.2Hierarchical configurations230 6Published by IEC under licence from IEEE. 2004 IEEE. All rights reserved. IEC 61691-4:2004

39、(E) IEEE 1364-2001(E) xiiCopyright 2001 IEEE. All rights reserved.13.4 Using libraries and configs.231 13.4.1Precompiling in a single-pass use-model.231 13.4.2Elaboration-time compiling in a single-pass use-model231 13.4.3Precompiling using a separate compilation tool231 13.4.4Command line considera

40、tions231 13.5 Configuration examples232 13.5.1Default configuration from library map file232 13.5.2Using the default clause.232 13.5.3Using the cell clause233 13.5.4Using the instance clause.233 13.5.5Using a hierarchical config233 13.6 Displaying library binding information234 13.7 Library mapping

41、examples.234 13.7.1Using the command line to control library searching234 13.7.2File path specification examples234 13.7.3Resolving multiple path specifications235 14.Specify blocks236 14.1 Specify block declaration236 14.2 Module path declarations237 14.2.1 Module path restrictions.238 14.2.2 Simpl

42、e module paths.238 14.2.3 Edge-sensitive paths239 14.2.4 State-dependent paths.240 14.2.5 Full connection and parallel connection paths244 14.2.6 Declaring multiple module paths in a single statement245 14.2.7 Module path polarity.246 14.3 Assigning delays to module paths.247 14.3.1 Specifying trans

43、ition delays on module paths248 14.3.2 Specifying x transition delays.249 14.3.3 Delay selection250 14.4 Mixing module path delays and distributed delays.251 14.5 Driving wired logic.252 14.6 Detailed control of pulse filtering behavior253 14.6.1Specify block control of pulse limit values254 14.6.2G

44、lobal control of pulse limit values.255 14.6.3SDF annotation of pulse limit values.255 14.6.4Detailed pulse control capabilities.256 15.Timing checks262 15.1 Overview.262 15.2 Timing checks using a stability window.265 15.2.1$setup.266 15.2.2$hold266 15.2.3$setuphold267 15.2.4$removal269 15.2.5$reco

45、very270 15.2.6$recrem271 15.3 Timing checks for clock and control signals273 15.3.1$skew.274 15.3.2$timeskew275 15.3.3$fullskew277 7Published by IEC under licence from IEEE. 2004 IEEE. All rights reserved. IEC 61691-4:2004(E) IEEE 1364-2001(E) Copyright 2001 IEEE. All rights reserved.xiii 15.3.4$wid

46、th279 15.3.5$period.280 15.3.6$nochange281 15.4 Edge-control specifiers.283 15.5 Notifiers: user-defined responses to timing violations.284 15.5.1Requirements for accurate simulation.286 15.5.2Conditions in negative timing checks288 15.5.3Notifiers in negative timing checks.290 15.5.4Option behavior

47、.290 15.6 Enabling timing checks with conditioned events290 15.7 Vector signals in timing checks291 15.8 Negative timing checks.292 16.Backannotation using the Standard Delay Format (SDF)294 16.1 The SDF annotator294 16.2 Mapping of SDF constructs to Verilog.294 16.2.1Mapping of SDF delay constructs

48、 to Verilog declarations294 16.2.2Mapping of SDF timing check constructs to Verilog296 16.2.3SDF annotation of specparams297 16.2.4SDF annotation of interconnect delays298 16.3 Multiple annotations.299 16.4 Multiple SDF files.300 16.5 Pulse limit annotation.300 16.6 SDF to Verilog delay value mappin

49、g301 17.System tasks and functions302 17.1 Display system tasks.302 17.1.1The display and write tasks303 17.1.2Strobed monitoring310 17.1.3Continuous monitoring311 17.2 File input-output system tasks and functions311 17.2.1Opening and closing files.311 17.2.2File output system tasks 313 17.2.3Formatting data to a string.314 17.2.4Reading data from a file.315 17.2.5File positioning319 17.2.6Flushing output319 17.2.7I/O error status.319 17.2.8Loading memory data from a file320 17.2.9Loading timing d