SAE SSB-1 004A-2009 Failure Rate Estimating (Annex to SSB-1 Guidelines for Using of Plastic Encapsulated Microcircuits and Semiconductors in Military Aerospace and Other Rugged App.pdf

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4、0 (outside USA) Fax: 724-776-0790 Email: CustomerServicesae.org SAE WEB ADDRESS: http:/www.sae.org SAE values your input. To provide feedback on this Technical Report, please visit http:/www.sae.org/technical/standards/SSB1_004A TECHNICAL REPORT SSB-1.004 REV. A Issued 1999-12 Revised 2009-04 Failur

5、e Rate Estimating NOTICE This document has been taken directly from the original TechAmerica document and contains only minor editorial and format changes required to bring it into conformance with the publishing requirements of SAE Technical Standards. The release of this document is intended to re

6、place the original with the SAE International document. Any numbers established by the original document remain unchanged. The original document was adopted as an SAE publication under the provisions of the SAE Technical Standards Board (TSB) Rules and Regulations (TSB 001) pertaining to accelerated

7、 adoption of specifications and standards. TSB rules provide for (a) the publication of portions of unrevised specifications and standards without consensus voting at the SAE committee level, and (b) the use of the existing specification or standard format. TechAmerica Engineering Bulletin SSB-1.004

8、-A Failure Rate Estimating SSB-1.004-A (Annex to SSB-1, Guidelines for Using of Plastic Encapsulated Microcircuits and Semiconductors in Military, Aerospace and her Rugged Applications) OtApril 2009 NOTICE TechAmerica Engineering Standards and Publications are designed to serve the public interest b

9、y eliminating misunderstandings between manufacturers and purchasers, facilitating interchangeability and improvement of products, and assisting the purchasers in selecting and obtaining with minimum delay the proper product for their particular needs. Existence of such Standards and Publications sh

10、all not in any respect preclude any member or nonmember of TechAmerica from manufacturing or selling products not conforming to such Standards and Publications, nor shall the existence of such Standards and Publications preclude their voluntary use by those other than TechAmerica members, whether th

11、e standard is to be used either domestically or internationally. Standards and Publications are adopted by TechAmerica in accordance with the American National Standards Institute (ANSI) patent policy. By such action, TechAmerica does not assume any liability to any patent owner, nor does it assume

12、any obligation whatever to parties adopting the Standard or Publication. Technical Publications are distinguished from TechAmerica Standards in that they contain a compilation of engineering data or information useful to the technical community and represent approaches to good engineering practices

13、that are suggested by the formulating committee. This Bulletin is not intended to preclude or discourage other approaches that similarly represent good engineering practice, or that may be acceptable to, or have been accepted by, appropriate bodies. Parties who wish to bring other approaches to the

14、attention of the formulating committee to be considered for inclusion in future revisions of this publication are encouraged to do so. It is the intention of the formulating committee to revise and update this publication from time to time as may be occasioned by changes in technology, industry prac

15、tice, or government regulations, or for other appropriate reasons. (Formulated under the cognizance of the G-12 Solid State Devices Committee.) Published by 2009 TechAmerica Standards it involves identification and classification of failure mechanisms, development and use of monitors, and investigat

16、ion of failure kinetics allowing prediction of failure rate at use conditions. Failure kinetics are the characteristics of failure for a given physical failure mechanism, including (where applicable) acceleration factor, derating curve, activation energy, median life, standard deviation, characteris

17、tic life, instantaneous failure rate, etc. The failure rate of semiconductor devices is inherently low. As a result, the semiconductor industry uses a technique called accelerated testing to assess device reliability. Elevated stresses are used to produce the same failure mechanisms as would be obse

18、rved under normal use conditions, but in a shorter time period. Acceleration factors are used by device manufacturers to estimate failure rates based on the results of accelerated testing. The objective of this testing is to identify these failure mechanisms and eliminate them as a cause of failure

19、during the useful life of the product. This document provides reference information concerning methods commonly used by the semiconductor industry to estimate failure rates from accelerated test results. These methods are frequently used by OEMs in conjunction with physics of failure reliability ana

20、lysis to assess the suitability of plastic encapsulated microcircuits and semiconductors for specific end use applications. 2 Reference Documents SSB-1.002 Environmental Tests and Associated Failure Mechanisms SSB-1.003 Acceleration Factors 1 SSB-1.004-A 3 Use Condition Based Reliability Evaluation

21、The SEMATECH Reliability Technology Advisory Board (RTAB) developed a reliability evaluation methodology based on the use conditions that a component is expected to encounter in its market applications1. Figure 1 depicts the process flow for use condition certification. One of the most critical step

22、s in the process is defining environmental, lifetime, and manufacturing use conditions (step I) since it provides the basis for all follow on activities that lead to establishing baseline performance (step VI). Determining the target market segment for a product establishes the use environment and l

23、ifetime that are appropriate for the technology. It is important to note that semiconductor manufacturers derive baseline performance estimates for use conditions associated with their predominant market segment(s). Table 1, prepared by the SEMATECH RTAB, encompasses the majority of specific conditi

24、ons within each major market segment. When assessing the suitability of a device for a specific application, it is essential to account for differences between the use environment and the environment the manufacturer used for reliability evaluation. Determine exploratory reliability stresses (II) Ga

25、ther package material property data to boundreliability stress conditions (IIA) Gather data to validate stress types needed for thetechnology (IIB) Establish which stresses are required (IIB,C) Develop global numeric stress models (IID) Develop a table of issues, best known accelerationsfrom histori

26、cal data and published works (IIE) Create speculative reliability stresses (IIF)Define Environmental, Lifetime andmanufacturing Use conditions (I)Define extended stress conditions necessaryto identify fail mechanisms andvalidate/develop models (III, IV)Determine final stress conditions (V)Establish

27、baseline performance (VI)Figure 1 Process Flow for Use Condition Certification 1SEMATECH Technology Transfer # 99083810A-XFR: Use Condition Based Reliability Evaluation of New Semiconductor Technologies (Aug 20, 1999) 2 SSB-1.004-A Table 1 Examples of Major Market Segment Environmental Ranges Major

28、Market Segment Op Life Power On (Hrs / Week) Cycles / Day Moisture Low Power Op Temp (Ambient In Enclosure) Storage Temp Indoor: PC/ Desktop, Server, Workstation, Consumer 5 10 yrs 60 168 Env. Cycle: 1-2 Power Cycle: 2-4 30 -36C 85-92% RH 0 to 40C -40 to 50CConsumer Portable: Notebook PCs, PDAs, Cel

29、 Phones, etc. 5 10 yrs 60 168 Env. Cycle: 2-4 Power Cycle: 4-6 30 -36C 85-92% RH -18 to 55C -40 to 55COther: Automotive, Telecom switching, Unattended outside, etc. 7 25 yrs 20 168 Env. Cycle: 2-4 Power Cycle: 2-10 30 -36C 85-92% RH -55 to 125C -40 to 55CTo illustrate this point, here is a specific

30、example comparing reliability assessment results for a benign use environment versus results for a more stressful environment such as those encountered in many military, aerospace, and other rugged applications. Upon reviewing a device manufacturers product reliability report, we note that this manu

31、facturer extrapolates HAST test results for temperature-humidity-bias induced failure mechanisms assuming use conditions of 70C junction temperature and 17.6% relative humidity. For one product technology, the manufacturer publishes a failure rate estimate of 5 Failures-In-Time (FITs), or Mean-Time-

32、To-Failure (MTTF) 22,500 years. If, however, we recalculate the failure estimate for a use environment of 85C junction temperature and 90% relative humidity (with all other elements of the failure rate calculation remaining equal), the result becomes 2431 (FITs), MTTF 47 years. 3 SSB-1.004-A 4 Failu

33、re Rate Estimating Methodology The most frequently used reliability measure for semiconductor devices is the failure rate (). For constant failure rate, the failure rate is the ratio of the number of failures to the product of the number of devices on test and the interval in hours (i.e. = number of

34、 failures / number of devices / number of test hours). The standard method for reporting long term failure rates for semiconductor devices is to express failure rate in Failures-In-Time (FITs), or the fraction of the number of failures per billion (109) device-hours. To project from a sample to the

35、population in general, one must establish confidence intervals. The application of confidence intervals is a statement of how “confident” one is that the sample failure rate approximates that for the population. To obtain failure rates at different confidence levels, it is necessary to make use of s

36、pecific probability distributions. The chi-square distribution (2), which relates observed and expected frequencies of an event, is frequently used to establish confidence intervals. The relationship between failure rate and the chi-square distribution is as follows: ()92102,=tAfdf = failure rate (F

37、ailures-In-Time) 2= chi-square function = (100 - confidence level) / 100 d.f. = (2n + 2) degrees of freedom n = number of failures Af= acceleration factor t = (sample size x total test time) device-hours When estimating failure rates, device manufacturers use acceleration factors to extrapolate acce

38、leration test results to use conditions. SSB-1.003, Acceleration Factors, provides reference information concerning commonly used acceleration factors. SSB-1.002, Environmental Tests and Associated Failure Mechanisms, provides reference information concerning the environmental stresses associated wi

39、th acceleration tests specifically designed to apply to (or have unique implications for) plastic encapsulated microcircuits and semiconductors, and the specific failures induced by these environmental stresses. 4 SSB-1.004-A Device manufacturers typically estimate failure rates at either 60% or 90%

40、 confidence levels. Table 2 presents chi-square distribution functions (2) for various confidence levels: Table 2 Chi-Square (2) Distribution Functions Confidence Level () Failures (n) d.f. (2n+2) 25% 50% 60% 75% 90% 95% 99% 0 2 0.575 1.386 1.833 2.773 4.605 5.991 9.210 1 4 1.923 3.357 4.045 5.385 7

41、.779 9.488 13.277 2 6 3.455 5.348 6.211 7.841 10.645 12.592 16.812 3 8 5.071 7.344 8.351 10.219 13.362 15.507 20.090 4 10 6.737 9.342 10.473 12.549 15.987 18.307 23.209 5 12 8.438 11.340 12.584 14.845 18.549 21.026 26.217 6 14 10.165 13.339 14.685 17.117 21.064 23.685 29.141 7 16 11.912 15.338 16.78

42、0 19.369 23.542 26.296 32.000 8 18 13.675 17.338 18.868 21.605 25.989 28.869 34.805 9 20 15.452 19.337 20.951 23.828 28.412 31.410 37.566 10 22 17.240 21.337 23.031 26.039 30.813 33.924 40.289 11 24 19.037 23.337 25.106 28.241 33.196 36.415 42.980 12 26 20.843 25.336 27.179 30.435 35.563 38.885 45.6

43、42 13 28 22.657 27.336 29.249 32.620 37.916 41.337 48.278 14 30 24.478 29.336 31.316 34.800 40.256 43.773 50.892 In order to derive the overall failure rate for a product, failure rates of potential failure mechanisms are estimated separately, then added together. This is known as the Sum-of-the-Fai

44、lure-Rates method: niTotal +=.21where Totalrepresents the overall failure rate and irepresents the failure rate for each failure mechanism. 5 SSB-1.004-A Failure Rate from Multiple Test Types If there are multiples sources of failure rate data for the same failure mechanism then an averaging techniq

45、ue must be employed to provide an estimate for that failure mechanism. The average failure rate is the geometric mean: nnjjave/11=where jis the failure rate calculated from the data for test j and n is the total number of different test types. As an example, for humidity, data may be available from

46、HAST, THB, and autoclave testing. The average failure rate would be the geometric mean of the individual failure rates as follows: 3AutoclaveTHBHASTave =Failure Rate for Multiple Environmental Segments Multiple use environment segments corresponding to one type of potential failure mechanism are com

47、monly encountered. For example, several temperature cycling environments may be specified (different temperature limits and possibly different cycle rates). This can be handled in a couple of different ways. One way would be to calculate the failure rate for each environment segment and then use onl

48、y the highest (worst case) value in the Sum-of-the-Failure-Rates calculation. Another, less conservative method would be to calculate an effective failure rate as a weighted sum over the individual segments as follows: =kkkeffA where Akis the fraction of service life (time) spent in the kth segment

49、and kis the failure rate calculated for the kth segment. Note: this methodology assumes that failure rates in the various environment segments are constant. As an example, a use condition for a temperature cycling environment may include three segments as follows: 1/2 of the time at temperature range T1 (corresponding to failure rate