NAVY MIL-D-85331-1979 DIGITAL WORD GENERATOR PERFORMANCE AND INTERFACE《数字词产生和连系装置》.pdf

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1、MIL-D-5331 66 7977906 01Li5Lh4 3 1. MIL-D-85331(AS) 18 July 1979 MILITARY SPECIFICATION DIGITAL WORD GENERATOR PERFORMANCE AND INTERFACE This specification is approved for use by Naval Air Systems Command, Department of the Navy, and is available for use by all Denartments and Agencies of the Depart

2、ment of Defense. SCOPE 1.1 Scope. This document establishes the minimum per- formance characteristics for a commercially available Digital Word Generator (DWG). controlled test systems and specifically the hybrid test system described by MIL-H-85330(AS). The document provides sufPi- cient informatio

3、n to an offeror of a hybrid test system to integrate the DWG into his system or to provide a fit, form and functionally compatible unit with the Navys existing inventory of DWGs. The DWG is intended for use in computer APPLICABLE DOCUMENTS , I 2. 2.1 Publications. The following document forms a part

4、 of this specification to the extent specified herein. Unless otherwise indicated, the issue in effect on date of invitation for bids or request for proposal shall apply. SPECIFICATIONS MILITARY MIL-H-85330(AS) - Hybrid Test System Specification Beneficial comments (recommendations, additions, delet

5、ions) and any pertinent data which may be of use in improving this document should be addressed to: Naval Air Engineering Center, Engineering Specifications and Standards Department (ESSD) Code 93, Lakehurst NJ by using the self-addressed Standardization Document Improvement Proposal (DD for 1426) a

6、ppearing at the end of this document or by letter. Commanding Officer, 08733, FSC 6625 3 THIS DOCUMENT CONTAINS PAGES, U Licensed by Information Handling ServicesMIL-D-5331 66 W 777770b 01Y5165 5 W I I DEVICE STIMULUS LOGIC HIGH ?OOHER SUPPLY CTIYULUS LOGIC LOW rOYIER WPILY REPOKSC REFERL:.CE POWER

7、HIPPLY DIGITAL WRD GENERATOR b FIGURE 1- System Configuration. -2bo+ MAX c UNIT UNDER TEST I : -2- . O . . -. . . -I Licensed by Information Handling ServicesMIL-D-5333 66 7777706 0345366 7 I 1- 56 25 36 37 38 39 40 41 42 43 44 45 46. 47 40 49 50 51 52 - , +- MI L-D-85331 (AS) ED- I I 4 I .I I -1 56

8、1 -a- l e 3 4 5 6 7 0 9 10 ll 12 17 24 - FIGURE 2. -. Computer/DWG I/O. . - 3- i c DOO L_ Doll FLAG GND _. . Licensed by Information Handling ServicesPUL-D-85333 66 = 7977706 0345367 7 680 o FIGURE 3. DWG/Computer interface. -4- o Licensed by Information Handling Services3. REQUIREMENTS 3.1 General.

9、 A typical system configuration is shown pictorially in Figure 1. The DWG shall be controlled by a digital computer which supplies 16 bit binary words to control the mode of operation of the system. Data and control signals are exchanged between the computer and DWG through connector J6, Figure 2, (

10、connector information per DWG Outline Drawing) on the rear of the DWG. Computer inputs (16 data bits) and a control command line, to the DWG are routed to Control Card Al (A31U30051). The Control Card is supplied with all DWGs and provides the proper terminations (Figure 3) for digital data sources

11、employing Transistor Transistor Logic (TTL) micro- circuit logic output drivers having ground true logic levels (Logical 1 = LO; Logical O = Hi). The DWG also outputs data to the computer (12 data lines and a control flag line) via DWG connector J6. The lines are driven by microcircuit output driver

12、s located on the Control Card Al within the DWG. The data lines and flag drivers produce ground true logic levels compatible with systems employing TTL logic circuitry. An example of a typical computer input/output card is the iewlett Packard HP12566-60024 Microcircuit Interface Card. 3.2 Mechanical

13、 Packaging. The DWG is packaged in one (lj drawer containing the following circuit cards: i a. Control Card (Al) - P/N A31U30051. The Control Card accepts data and instructions from the Computer in order to control both DWG memory and Timing Generator operati0n. All data to and from the Computer pas

14、ses through this card. b. Timing Generator Card (A12) - P/N A31U30052. The Timing Generator Card accepts instructions and data from the Control Card to generate the timing required or DWG memory access and UUT testing. Functionally, the Timing Generator generates the programmable test clock, sets th

15、e test length, loads and increments the test pattern-counter, generates the stimulus (SI, S2, and S3), response (R), and write (WR) strobes for the DWG and UUT. It also provides for external timing and synchronization modes with the UUT. NOTE I-/ A brief description of the DWG and its theory o opera

16、tion is provided in an Appendix contained herein. - 5- Licensed by Information Handling Servicesfl-IL-D-85331 66 777770b 0145167 2 M P c. Memory Card (A2 through All) - P/N A31U30053. Each memory card contains 24 independent input/output lines which are available to generate stimuli and sample respo

17、nses. Each card is sub-divided into two (2) halves: (1) Pins 1 to 12, and (2) Pins 13 to 24. The entire card and all of its functions are controlled by the Control and Timing Generator Cards. 3.3 Electrical Requi reme tits 3.3.1 AC/DC Power Requirements. AC power is brought. to the DWG via connector

18、 52 to operate its internal blower. DC (+5V) power is brough in via connector 54. power of 15 watts and a maximum of 55 amps DC are required per drawer (240 pins). Figure 4 illustrates the method of applying power and shows pin assignments. The AC power, used to operate the blower (Bl), is supplied

19、by U detachable three (3) conductor power cable. 3.3.2 Logic Level References. All logic level reference voltages applied to the programmable drivers/receivers (located on Memory Cards) are supplied from external power supplies. Since the requirement for references varies according to the users test

20、 application, the power supplies are not furnished as part of the DWG and must therefore, be supplied by the user. A maximum blower 3.3.2.1 Logic Level Reference Group A and B. When testing UUTs that are configured with different types of logic element (e.g. Metal Oxide Semi-conductor (MOS), Diode T

21、ransistor Logic (DTL), Resistor Transistor Logi? (RTL), TTL, etc.), at least two (2) groups of programmable (-20V) logic level references are needed. Each group requires three (3) voltages to establish the analog threshold levels for driver Hi, driver Lo and references. Therefore, the six (6) refere

22、nce voltages used for groups IAt and B are obtained from six (6) programmable power supplies external to the DWG. 3.3.2.2 Reference groups A and BI are fed into the rear via 53. Figure 5 illustrates the method of inputting logic level reference groups A and B and distribution in the DWG. Although bo

23、th A and B references enter the memory card, only one (1) of the references are used for that -6- Licensed by Information Handling ServicesMIL-D-85331 66 7777906 OL45170 7 Il5V AC 60 nz 15W GD 52 HI T NEU1 CND INDICATOR 54 1 44 37 39 38 51 49 l-t 36 I: 21 R L - FIGURE 4. AC/DC power requirements. li

24、 I 1 I l I 1 I I J Licensed by Information Handling ServicesNIL-D-5331 66 W 799770b 0145171 O W . . REFERENCE A REFEREN$, B J3 t 1. 2. -zc5 CRI 3 44 5 - DRIVER HI a - DRIVER LO CR2 RECEIVER REFERENCE 6 7. 0 -5 c7 CR3 9 CR4 IO 4) II - DRIVER til + 4B - DRIVERLO RECEIVER REFERENCE FIGURE 5. Logic leve

25、l reference groups A and B input and distribution. - 8- . U Licensed by Information Handling ServicesMIL-D-5333 bb 779770b 0345372 2 M card. The choice is made by adding three (3) jumpers to a jumper block (see Figure 6) located on the programmable memory card. 3.3.2.3 The DWG is configured such tha

26、t pins 1-120 are assigned to reference group A and pins 121-240 are assigned to reference group B!. 3.4 Signal Interfaces 3.4.1 DWG/UUT Input/Output. hlemory Cards (1-10) provide the digital test signalinterface with the UUT, in modular increments of 24 1/0 test pins per card. programmable as either

27、 a driver 1 (for inputting test logic stimuli to the UUT) or receiver O (accepting test logic responses from the UUT). Ten (IO) Memory Cards are installed in the DWG. This provides a digital test interface with the UUT of 240 1/0 test pins. available via the edge connector (Figure 7) on the top of e

28、ach memory card. Mating connector and information for interfacing with edge connector J1 is listed in Table I. Each test pin is The 24 1/0 test pins are made 3.5 Digital Word Generator Performance. The digital word generator performance is in accordance with the following: a. The unit shall provide

29、capability for dynamic testing of units under test having up to 240 pins digital interface. Each test pin provided for this purpose shall be operable as either a driver or comparator under computer control. b. The digital word generator shal.1 provide a 256 bit memory for each test pin. c. Logic lev

30、els for the 240 pins shall be programmable over the following voltage ranges: 1. Programmable Drivers. The high logic level (logic 1) shall be programmable from O volts to +20 volts. The low logic level (logic O) shall be programmable from -20 volts to O volts. The maximum differential voltage (high

31、 minus low) shall be 20 volts. 2. Programmable Receivers. The logic level (threshold reference voltage) shall be programmable from -20 volts to +20 volts. The maximum signal input voltage shall not exceed k20 volts. 3. Driver/Receiver Programming. The levels shall be programmable in two (2) independ

32、cnt groups. Group 1 encompasses the first 120 pins, and Group 2 encompasses the second 120 pins. The programmable drivers shall source up to ._ - 9- . o Licensed by Information Handling ServicesMIL-D-85331( AS ) I LOGIC REFERENCE (MOTHER A-BI BOAROI I PI I Pm JI JUMPERS ARE LOCATED ON BOARD POSITION

33、 72 (ON PROGRPMMAOLE Mf MORY CAROS ONLY) ALL JUMPERS hiUST RE IN THE A OR B POSITION OR NOT INSTALLED. NOTE: UNDERLINE0 LETTERS INDICATE LOWER CASE. FIGURE 6. Logic level reference group seection. I LOGIC REFEHCNCE C I I I ! . . o Licensed by Information Handling ServicesMIL-D-85331 66 W 7977706 CIL

34、45174 b W D 5 E 6 F 7 G 8 J 9 K 10 L u M 12 N DIGITAL WORD GENERATOR WRY DRm A31U30053 I I I I I I- l I 1 - I ! I 13 P i4 R 15 6 16 T 17 U 18 V i9 W 20 X 21 ;Y 22 Z 23 AA 24 BB - I FIGURE 7, Memory driver card 1/0 interface ! -11- . o Licensed by Information Handling Servicesfl4L-D-85331 66 II 99799

35、06 01115175 8 50 ma (typical) in the high state, and sink up to 50 ma (typical) in the low state. d. Pins 1 through 240 shall be capable of sending and receiving digital test patterns at rates up to 10 MHZ. e. All driver circuits shall be short circuit proof, and shall limit output current into a sh

36、ort circuit Co the following values: 1. 50 ma minimum to +lo0 ma maximum or programmable drivers. f. The dynamic source impedance of driver circuits shall be : 1. 25 ohms maxi.mum for programmable drivers. g. The comparator circuits of programmable cards shall return a logic 1 when the UUT presents

37、a level in excess of the comparator reference, or a logic O when the UUT presents a level below the comparator reference, with the following tolerances : 1. 500 mv for levels up to 5 volts 2. 1 volt for levels between 5 and absol ut e 3. 2 volts for levels in excess of absolute ab so 1 ut e 15 volts

38、 15 volts from h. Input current (or reference current) the Unit Under Test logic function (or reference supply) to the programmable comparator circuit shall be equal to the input (or reference supply) voltage minus 2 volts, divided by 4000. 2 i. The worst case currents. drawn by the driver reference

39、 voltages (V+ and V-) are : per Driver 1. I+ = -0.5 ma + v+ + V+ 4K Rload in High State 2. I+ = V+ + iv-i per Driver in LOW State 1.6K NOTE: - 2/ When a line is programmed as a UUT output, I+ = I- = 0 -12- o Licensed by Information Handling Services3. I- O per Driver in High State 4. I- = 8.5 ma + V

40、+ + V- + V- - O. 75K 16K Rload per Driver in Low State j. The programmable driver oPfset shall be equal to: V offset = (0.85 + 0.017 Iload (MA) *IO% k. An external oscillator input (20 MHZ max.) from the interface to the digital word generator shai.1 be provided via card edge connector (Figure 8) A1

41、2 J1-A and this input shall have a 56 ohm input impedance with respect to ground. The external oscillator input shall allow operation of the digital word generator/extender from clocks of origin . in the UUT or interface device, when programmed for this mode by the user. The external oscillator inpu

42、t will be counted down by a 12-stage programmable counter in the digital word generator, so that the ratio of division between external oscillator input and resulting test clock shall be programmable between values of 2:l and 8190:l in binary fashion. 1. An external clock input from interface to the

43、 digital word generator shall be provided via card A12 J1-F and shall be designed for operation with TTL or TTL-Schottky driving circuits, The external clock input, when programmed for use, shall be the basic test clock. Maximum frequency of the external clock input shall be 10 MHZ. Input impedance

44、shall be 330 ohms to +5 WC and 680 ohms to ground. m. The digital word generator outputs designated CP-1 and CP-2 from card A12 J1-B and J1-C, respectively, shall be identical to internal test clocks, and capable of driving a transmission line terminated by 130 ohms or more. CP-1 is a free running c

45、lock. CP-2 is free running except when the handshake mode is programmed in which case CP-2 is synchronized to the external flag signal. n. There shall be an external flag input from the interface via card A12 J1-D to the digital word generator in the handshake mode. The characteristics of this input

46、 shall be equivalent to a 330 ohm resistor to +5 volts DC, and a 680 ohm resistor to ground. The external flag function from the interface (unit under test or adapter) shall be true whenever data has been accepted from the digital word generator and the external device is ready. The external flag sh

47、all go false and then true after each command for subsequent commands/ clocks to continue. Logic levels shall be TTL compatible, positive true. -13- Licensed by Information Handling ServicesMT. OSCm EXT. C.P. MT. S:G. MT. R.G. MT. FLAG Jl A 1 - F 6 J 8 K 9 D 4 I IO I +5vDc 1 I 1 Jl Bt .B . C 3 F 5 H

48、 7 L 10 M u. N I2 1 MT. CP1 EXT. CP2 EXT. COMM.U?l) EXT. GATE s1 I s2 - R ! FIGURE 8. Timing Generator card 1/0 interface. -14- O. Licensed by Information Handling Services MIL-D-85333 bb 7T9e17Ob 0345378 3 o. There shall be an external command signal. from the digital word generator to the interfac

49、e via card A12 J1-E in the handshake mode. The external command signal shall go true whenever the digital word generator presents test data (e.g., a test pattern) to the external device, and shall go false when the external device returns the external flag as acknowledgment. The external cdmmand signal shall be a TTL compatible positive true signal, capable of driving a line terminated by 130 ohms or greater. p. There shall be a gate signal from the digital word generator to the interface via card A12 J1-H. This shall be a TTL compatible