JEDEC JESD89-1A-2007 Test Method for Real-Time Soft Error Rate.pdf

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1、JEDEC STANDARD Test Method for Real-Time Soft Error Rate JESD89-1A Addendum No. 1 to JESD89 (Revision of JESD89-1, June 2004) OCTOBER 2007 (Reaffirmed: JANUARY 2012)JEDEC SOLID STATE TECHNOLOGY ASSOCIATION NOTICE JEDEC standards and publications contain material that has been prepared, reviewed, and

2、 approved through the JEDEC Board of Directors level and subsequently reviewed and approved by the JEDEC legal counsel. JEDEC standards and publications are designed to serve the public interest through eliminating misunderstandings between manufacturers and purchasers, facilitating interchangeabili

3、ty and improvement of products, and assisting the purchaser in selecting and obtaining with minimum delay the proper product for use by those other than JEDEC members, whether the standard is to be used either domestically or internationally. JEDEC standards and publications are adopted without rega

4、rd to whether or not their adoption may involve patents or articles, materials, or processes. By such action JEDEC does not assume any liability to any patent owner, nor does it assume any obligation whatever to parties adopting the JEDEC standards or publications. The information included in JEDEC

5、standards and publications represents a sound approach to product specification and application, principally from the solid state device manufacturer viewpoint. Within the JEDEC organization there are procedures whereby a JEDEC standard or publication may be further processed and ultimately become a

6、n ANSI standard. No claims to be in conformance with this standard may be made unless all requirements stated in the standard are met. Inquiries, comments, and suggestions relative to the content of this JEDEC standard or publication should be addressed to JEDEC at the address below, or call (703) 9

7、07-7559 or www.jedec.org Published by JEDEC Solid State Technology Association 2007 2500 Wilson Boulevard Arlington, VA 22201-3834 This document may be downloaded free of charge; however JEDEC retains the copyright on this material. By downloading this file the individual agrees not to charge for or

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10、ndard No. 89-1A Page 1 TEST METHOD FOR REAL-TIME SOFT ERROR RATE (From JEDEC Board Ballot JCB-07-87, formulated under the cognizance of the JC-14.1 Subcommitee on Reliability Test Metods for Packaged Devices.) 1 Scope This test is used to determine the Soft Error Rate (SER) of solid state volatile m

11、emory arrays and bistable logic elements (e.g. flip-flops) for errors which require no more than re-reading or re-writing to correct and as used in terrestrial environments. It simulates the operating condition of the device and is used for qualification, characterization, or reliability monitoring.

12、 This test is intended for execution in ambient conditions without the artificial introduction of radiation sources. JESD89-1 is offered to define concisely the requirements for executing this test in a standardized fashion. It is intended for use in conjunction with JESD89 which includes background

13、 on reasons for these requirements. NOTE 1 Typically, soft error rate characterization by this test method will be executed by the device manufacturer. Other parties may also apply this method appropriately in conjunction with the manufacturers product data sheet. NOTE 2 The term real-time soft-erro

14、r rate (RTSER) is preferred over the term system soft-error rate (SSER). NOTE 3 Special considerations apply to devices that are more than memory arrays and/or bistable logic elements. These can preclude the application of this test procedure. Refer to JESD89 for further discussion on some examples.

15、 1.1 Applicable documents JESD89 Measurement and Reporting of Alpha Particles and Terrestrial Cosmic Ray-Induced Soft Errors in Semiconductor Devices JESD89-2 Test Method for Alpha Source Accelerated Soft Error Rate JESD89-3 Test Method for Beam Accelerated Soft Error Rate JESD22-A108 Temperature, B

16、ias, and Operating Life 2 Apparatus The performance of this test requires equipment that is capable of providing the particular test conditions to which the test samples will be subjected. (As a practical matter, this equipment will typically provide the means to collect data on many samples under e

17、valuation over the same time period.) The integrity of the test apparatus shall be verified prior to data collection. The particulars of the verification process are left to the individual investigator for their specific equipment. JEDEC Standard No. 89-1A Page 2 2.1 Vehicle design and operation The

18、 circuitry through which the samples shall be biased shall be designed with the following considerations: The biasing and operating schemes shall consider the limitations of the device and shall not overstress the devices or contribute to thermal runaway. The test circuit shall be designed to limit

19、power dissipation such that if a device failure occurs, excessive power cannot be applied to other devices in the sample. 2.2 Device mounting Equipment design, if required, shall provide for mounting of devices to minimize adverse effects while parts are under test, (e.g., improper heat dissipation)

20、. 2.3 Power supplies and signal sources Instruments (e.g., oscilloscopes) used to set up and monitor power supplies and signal sources shall be calibrated and have long-term stability. Electrical noise shielding shall be in place to allow for accurate test results. 3 Terms and definitions absolute m

21、aximum rated temperature: The maximum junction or ambient temperature of an operating device as listed in its data sheet and beyond which damage (latent or otherwise) may occur. It is frequently specified by device manufacturers for a specific device and/or technology. NOTE Manufacturers may also sp

22、ecify maximum case temperatures for specific packages. absolute maximum rated voltage: The maximum voltage that may be applied to a device and beyond which damage (latent or otherwise) may occur. It is frequently specified by device manufacturers for a specific device and/or technology. critical cha

23、rge (Qcrit): The minimum amount of collected charge that will cause the node to change state hard error: An irreversible change in operation that is typically associated with permanent damage to one or more elements of a device or circuit (e.g., gate oxide rupture, destructive latch-up events). NOTE

24、 The error is called “hard” because the data is lost and the circuit or device no longer functions properly, even after power reset and re-initialization. minimum operating voltage: The minimum power supply voltage at which a device is specified to operate in compliance with the applicable device sp

25、ecification or data sheet. JEDEC Standard No. 89-1A Page 3 3 Terms and definitions (contd) multiple-bit upset (MBU): A multiple-cell upset (MCU) in which two or more error bits occur in the same word. NOTE An MBU cannot be corrected by a simple (single-bit) ECC. multiple-cell upset (MCU): A single e

26、vent that induces several bits in an IC array to fail at the same time. NOTE The error bits are usually, but not always, physically adjacent. real-time soft error rate (RTSER); system soft error rate (SSER): The soft error rate in a naturally occurring alpha particle and neutron environment. NOTE 1

27、The RTSER is measured using a large number of devices to obtain a statistically significant error count, in contrast to an accelerated SER test where an intense radiation source is used on a single device or small number of devices. NOTE 2 The RTSER error counts can be increased by using a higher ne

28、utron flux at higher altitudes, but for the purposes of this specification, the term “accelerated” is reserved for intense radiation sources that do not occur in natural terrestrial environments. single-event burnout (SEB): An event in which a single energetic-particle strike induces a localized hig

29、h-current state in a device that results in catastrophic failure. single-event effect (SEE): Any measurable or observable change in state or performance of a microelectronic device, component, subsystem, or system (digital or analog) resulting from a single energetic-particle strike. NOTE Single-eve

30、nt effects include single-event upset (SEU), multiple-bit SEU (MBU), multiple-cell upset (MCU), single-event functional interrupt (SEFI), single-event latch-up (SEL), single-event hard error (SHE), single-event transient (SET), single-event burnout (SEB), and single-event gate rupture (SEGR). single

31、-event functional interrupt (SEFI): A soft error that causes the component to reset, lock-up, or otherwise malfunction in a detectable way, but does not require power cycling of the device (off and back on) to restore operability, unlike single-event latch-up (SEL), or result in permanent damage as

32、in single-event burnout (SEB). NOTE An SEFI is often associated with an upset in a control bit or register. single-event gate rupture (SEGR): An event in which a single energetic-particle strike results in a breakdown and subsequent conducting path through the gate oxide of a MOSFET. NOTE An SEGR is

33、 manifested by an increase in gate leakage current and can result in either the degradation or the complete failure of the device. single-event hard error (SHE): An irreversible change in operation resulting from a single radiation event and typically associated with permanent damage to one or more

34、elements of a device (e.g., gate oxide rupture). JEDEC Standard No. 89-1A Page 4 3 Terms and definitions (contd) single-event latch-up (SEL): An abnormal high-current state in a device caused by the passage of a single energetic particle through sensitive regions of the device structure and resultin

35、g in the loss of device functionality. NOTE 1 SEL may cause permanent damage to the device. If the device is not permanently damaged, power cycling of the device (off and back on) is necessary to restore normal operation. NOTE 2 An example of SEL in a CMOS device occurs when the passage of a single

36、particle induces the creation of parasitic bipolar (p-n-p-n) shorting of power to ground. single-event transient (SET): A momentary voltage excursion (voltage spike) at a node in an integrated circuit caused by the passage of a single energetic particle. single-event upset (SEU): A soft error caused

37、 by the signal induced by the passage of a single energetic particle. soft error, device: An erroneous output signal from a latch or memory cell that can be corrected by performing one or more normal functions of the device containing the latch or memory cell. NOTE 1 As commonly used, the term refer

38、s to an error caused by radiation or electromagnetic pulses and not to an error associated with a physical defect introduced during the manufacturing process. NOTE 2 Soft errors can be generated from SEU, SEFI, MBU, MCU, and/or SET. The term SER, which includes a variety of soft error mechanisms, ha

39、s been adopted by the commercial industry while the more specific terms SEU, SEFI, etc. are typically used by the avionics, space, and military electronics communities. soft error, power-cycle (PCSE): A soft error that is not corrected by repeated reading or writing but can be corrected by the remov

40、al of power (e.g., nondestructive latch-up). soft error, static: A soft error that is not corrected by repeated reading but can be corrected by rewriting without the removal of power soft error, transient: A soft error that can be corrected by repeated reading without rewriting and without the remov

41、al of power. JEDEC Standard No. 89-1A Page 5 4 Procedure 4.1 Test duration The test duration shall be specified by internal qualification requirements or the applicable procurement document. The test duration is defined as the time from the first data write at test conditions to the last read at tes

42、t conditions. The time spent performing any chamber setup and power down shall not be considered a portion of the total specified test duration. 4.2 Test conditions 4.2.1 Temperature Unless otherwise specified, the junction temperature for the devices under evaluation shall be controlled to within a

43、 tolerance of +/-10C of each other. (A junction temperature of 40C is recommended where guidance is needed; other junction temperature conditions may be dictated by customer specification or technical constraints.) 4.2.2 Operating voltage Unless otherwise specified, the operating voltage shall be th

44、e nominal operating voltage specified for the device. In order to characterize SER as a function of Qcrit, a lower/higher voltage is permitted. This voltage shall not exceed the absolute maximum rated voltage for the device and shall be agreed upon by the device manufacturer. Care shall be taken in

45、all cases to understand what the device operating voltages are in either bypass mode or regulated mode. 4.2.3 Biasing configurations The parts shall be operated in a dynamic mode during the life test consistent with those described for High Temperature Operating Life (HTOL) in JESD22-A108. Device ou

46、tputs may be unloaded or loaded to achieve the specified output voltage level. If a device has a thermal shutdown feature, it shall not be biased in a manner that could cause the device to go into thermal shutdown. 4.2.3.1 Real-Time SER test Unless otherwise stated, the RTSER test shall be configure

47、d to provide write/read function to the entire available array of the device samples with insitu pass/fail recording. The cumulative time in each valid data state for each memory array element shall be approximately equal, i.e., a two-state memory element shall see equal cumulative time over the RTS

48、ER test in the high state and the low state. It is recommended that the patterns or pattern suite otherwise approximate typical use. For characterization purposes test conditions can be modified. These include supply voltages, clock frequencies, input signals, etc., which may be operated outside the

49、ir specified values. When operating outside the application range of the part, predictable and nondestructive behavior of the devices under test shall be assured. JEDEC Standard No. 89-1A Page 6 4.3 Test readiness Prior to running the SER test, a tester readiness check shall be performed. This check shall be performed with the hardware in the manner it will be used for the test. The parts shall be operated to the basic write/read pattern that will be used for the test. The check is completed successfully when no parts fail the basic write/read pattern. This check shall be per