JEDEC JESD87-2001 Standard Test Structures for Reliability Assessment of AICu Metallizations with Barrier Materials《结构可靠性评估与AICu Metallizations屏障材料的标准测试》.pdf

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1、 2500 Wilson Boulevard Arlington, Virginia 22201-3834 (703) 907-7559 FAX (703) 907-7583 July 20, 2001 ANNOUNCEMENT AVAILABILITY OF JEDEC STANDARD The JEDEC Solid State Technology Association (JEDEC) announces the release of JEDEC Standard No. 87 (JESD87), “Standard Test Structure for Reliability Ass

2、essment of AICu Metallizations with Barrier Materials.” This document describes design of test structures needed to assess the reliability of aluminum-copper, refractory metal barrier interconnect systems. This includes any metal interconnect system where a refractory metal barrier or other barrier

3、material prevents the flow of aluminum and/or copper metal ions from moving between interconnect layers. This document is not intended to show design of test structures to assess aluminum or aluminum-copper alloy systems, without barriers to Al and Cu ion movement, nor for Cu only metal systems. Som

4、e total interconnect systems might not include barrier materials on all metal layers. The structures in this standard are designed for cases where a barrier material separates two Al or Al alloy metal layers. The purpose of this document is to describe the design of test structures needed to assess

5、electromigration (EM) and stress-induced-void (SIV) reliability of AlCu barrier metal systems. JESD87 was developed by the JC-14.2 Subcommittee on Wafer-Level Reliability under the chairmanship of Mr. Michael J. Dion of Intersil Corporation. To obtain copies of JESD87 ($36.00 ea.), contact Global En

6、gineering Documents, 15 Inverness Way East, Englewood, CO 80112-5704 or call U.S.A. and Canada 1-800-854-7179, International (303) 397-7956. To download this document for free, access the JEDEC web site at www.jedec.org. JEDEC STANDARD Standard Test Structures for Reliability Assessment of AICu Meta

7、llizations with Barrier Materials JESD87 JULY 2001 JEDEC SOLID STATE TECHNOLOGY ASSOCIATION NOTICE JEDEC standards and publications contain material that has been prepared, reviewed, and approved through the JEDEC Board of Directors level and subsequently reviewed and approved by the EIA General Cou

8、nsel. JEDEC standards and publications are designed to serve the public interest through eliminating misunderstandings between manufacturers and purchasers, facilitating interchangeability and improvement of products, and assisting the purchaser in selecting and obtaining with minimum delay the prop

9、er product for use by those other than JEDEC members, whether the standard is to be used either domestically or internationally. JEDEC standards and publications are adopted without regard to whether or not their adoption may involve patents or articles, materials, or processes. By such action JEDEC

10、 does not assume any liability to any patent owner, nor does it assume any obligation whatever to parties adopting the JEDEC standards or publications. The information included in JEDEC standards and publications represents a sound approach to product specification and application, principally from

11、the solid state device manufacturer viewpoint. Within the JEDEC organization there are procedures whereby an JEDEC standard or publication may be further processed and ultimately become an ANSI/EIA standard. No claims to be in conformance with this standard may be made unless all requirements stated

12、 in the standard are met. Inquiries, comments, and suggestions relative to the content of this JEDEC standard or publication should be addressed to JEDEC Solid State Technology Association, 2500 Wilson Boulevard, Arlington, VA 22201-3834, (703)907-7560/7559 or www.jedec.org Published by JEDEC Solid

13、State Technology Association 2001 2500 Wilson Boulevard Arlington, VA 22201-3834 This document may be downloaded free of charge, however JEDEC retains the copyright on this material. By downloading this file the individual agrees not to charge for or resell the resulting material. PRICE: Please refe

14、r to the current Catalog of JEDEC Engineering Standards and Publications or call Global Engineering Documents, USA and Canada (1-800-854-7179), International (303-397-7956) Printed in the U.S.A. All rights reserved PLEASE! DONT VIOLATE THE LAW! This document is copyrighted by the Electronic Industri

15、es Alliance and may not be reproduced without permission. Organizations may obtain permission to reproduce a limited number of copies through entering into a license agreement. For information, contact: JEDEC Solid State Technology Association 2500 Wilson Boulevard Arlington, Virginia 22201-3834 or

16、call (703) 907-7559 JEDEC Standard No. 87 Page 1 Standard Test Structures For Reliability Assessment of AlCu Metallizations with Barrier Materials (From JEDEC Board Ballot JCB-00-105, formulated under the cognizance of the JC-14.2 Subcommittee on Wafer-Level Reliability.) 1 Scope This document descr

17、ibes design of test structures needed to assess the reliability of aluminum-copper, refractory metal barrier interconnect systems. This includes any metal interconnect system where a refractory metal barrier or other barrier material prevents the flow of aluminum and/or copper metal ions from moving

18、 between interconnect layers. The barrier material might exist in one or all of the following locations: Above and/or below the aluminum-copper metal layer, and Above and/or below the contact or via to connect metal layers. Barrier materials commonly include, but would not be limited to: tungsten (W

19、), titanium (Ti), titanium-nitride (TiN), titanium-aluminide (Ti2Al3), and platinum (Pt). This document is not intended to show design of test structures to assess aluminum or aluminum-copper alloy systems, without barriers to Al and Cu ion movement, nor for Cu only metal systems. Some total interco

20、nnect systems might not include barrier materials on all metal layers. The structures in this standard are designed for cases where a barrier material separates two Al or Al alloy metal layers. Throughout this document, the term via is used to describe design of a conductive path between conductive

21、metal layers. This term is also used to describe a conductive path between doped Si or poly-Si and a metal conductor that might also be referred to as a contact. The purpose of this document is to describe the design of test structures needed to assess electromigration (EM) and stress-induced-void (

22、SIV) reliability of AlCu barrier metal systems. JEDEC Standard No. 87 Page 2 2 Test structure design issues 2.1 Kelvin connection All structures must allow Kelvin connections for resistance measurement. Each end of the metal resistor lines must have 1) a connection to source/sink high currents, and

23、2) a connection for voltage monitor. 2.2 Line width At line widths greater than the median grain size, electromigration proceeds via grain boundary diffusion. Lines with multiple grains across the line width must be evaluated for reliability. The narrowest line width allowed by layout design rules m

24、ust be assessed. As line width gets narrower than median grain size, commonly referred to as bamboo grains, electromigration will not be dominated by grain boundary diffusion and reliability of the line will be different than for wider lines. 2.3 Line length 2.3.1 Short lines When a line is short, b

25、ack diffusion of metal ions can slow or stop electromigration *). To ensure that electromigration is being properly assessed, the test line must be sufficiently long to ensure that no or minimal back diffusion of ions will slow void growth. 2.3.2 Long lines and failure criterion With barrier materia

26、l interconnect systems, after copper depletion in the AlCu line, electromigration structures on most processes (but not all processes) will gradually increase in resistance until the pre-defined resistance-increase failure criterion has been reached. The resistance increase is caused by EM voiding a

27、nd is a direct measure of the EM rate. Failure criterion is usually a fractional increase in the starting resistance; such that the starting resistance (or starting line length) defines, to a large extent, when the failure criterion might be meet. Provision must be made to standardize, or otherwise

28、normalize, line-length effects on time-to-failure. * I. Blech, Electromigration in Thin Aluminum films on Titanium Nitride, J. Appl. Phys., 47, 1976, pp. 1203. JEDEC Standard No. 87 Page 3 2 Test structure design issues (contd) 2.4 Reservoirs It has been shown ), ), ) that areas and/or volumes of me

29、tal surrounding vias, often referred to as reservoirs, can have significant impact on electromigration in barrier material interconnect systems; however, a complete understanding of these effects is not presently available. Given the significant impact that reservoirs have, test structure design mus

30、t be very specific in the regions surrounding the vias to be used with a given failure and acceptance criterion. 2.5 Extrusion monitor Monitoring for metal extrusions is important. Placement of monitor lines at minimum spacing from the stress lines allows for appropriate extrusion monitor and provid

31、es a level of optical loading that will tend to produce test lines with final dimensions closer to those likely to be found in a typical design. Use of additional lines for optical loading is not restricted by this standard. Placement of a single, isolated, minimum dimension lines may yield unrepres

32、entative line widths and should be avoided. 3 Electromigration test structure definition: Line and Via structures 3.1 Structure introduction For each “new“ metal-layer/Via combination, build structures to assess reliability of a particular metal-line/barrier combination using the characteristics (se

33、e also Figure 1): Kelvin connected, wide source lines, extrusion monitors, narrow lines with single via (to upper and/or lower barrier), wide lines with vias (to upper and/or lower barrier), and all needed combinations of via-to-line. M. Dion, Electromigration Lifetime Enhancement for Lines with Mul

34、tiple Branches Proceedings of the 38th International Reliability Physics Symposium, 2000, pp. 324. E. Atokav, “Effect of VLSI Interconnect Layout on Electromigration Performance,“ Proceedings of the 36th International Reliability Physics Symposium, 1998, pp. 348. B. Baerg, “Recent Problems in Electr

35、omigration,“ Proceedings of the 35th International Reliability Physics Symposium, 1997, pp. 211. JEDEC Standard No. 87 Page 4 3 Electromigration test structure definition: Line and Via structures (contd) Figure 1An example barrier metal EM structure, with Kelvin connected wide current source lines,

36、extrusion monitor lines, a non-minimum width 400 m long test line connected through vias. Many other configurations are possible. 3.2 Very wide source line Very wide current source lines are at both ends of the structure and should be greater than or equal to 5 times the test line width. 3.3 Voltage

37、 sense (to allow Kelvin connection) Voltage sense lines will be connected to the wide current feed lines at each end of the structure, adjacent and as close as possible to the vias to the test line. The voltage sense lines will not be directly connected to the test line since they could act as reser

38、voirs. 3.4 Extrusion monitor Along the length and on each side of the test line there will be lines on both sides to sense for shorting by metal extrusions or whiskers. The extrusion lines will be of minimum allowed width and separated from the test line by the minimum allowed space. 3.5 Narrow line

39、, with single via In designing a narrow line structure, the following dimensions are important: minimum line width, minimum via size, minimum overlap of metal to via, and minimum space between lines. Design of the narrow line with a single via can have different configurations depending upon the rel

40、ative values. Use single contact/via and minimum width line: 1 Contact or Via at the cathode end of a line. Minimum line width Minimum metal overlap over/around/below the Via Test line length =400 m (lengthBlech length, constant length for R failure criterion). See also 3.7. V-Sense I-Source =5WV-Se

41、nseI-SourceExtrusion Monitor Line 400m Test Line WMinimum Space Minimum Line JEDEC Standard No. 87 Page 5 3 Electromigration test structure definition: Line and Via Structures (contd) 3.6 Wide lines 1) Wide lines can fail for electromigration differently than narrow lines. It is important to stress

42、lines that have multiple metal grains across the line width. Other characteristics are similar to those of the narrow, single via line. 2) Length =400 m (Blech length). See also 3.7. 3) If the median AlCu grain size is known, then line width shall be 3 times the grain size, otherwise line width shal

43、l be 3 m. However, getting vias to fit in the line width, with minimum spaces and overlaps will often dictate the line width. Select the wide-line width and number of vias connected to the line such that: a) At the cathode end(s), vias must span the width of the line, with minimum spaces and overlap

44、s, and b) line width is either greater than or equal to 3 X (median grain size) OR- c) line width is greater than or equal to 3 m. 4) The line will have a single row of vias across the line width, at the end of the line for the metal-barrier interface. Minimum via-to-via spacing and minimum metal ov

45、erlaps of via must be used. Available test equipment must be capable of stressing the line widths used. 5) It is recommended that maximum joule heating *) at the maximum stress current be less than 10 C. * JEDEC Standard 33A (JESD33A), Standard Method for Measuring and using the Temperature Coeffici

46、ent of Resistance to Determine the Temperature of a Metallization Line. JEDEC Standard No. 87 Page 6 3 Electromigration test structure definition: Line and Via Structures (contd) 3.7 Line length alternatives When a 400 m test line is not available, it is possible to normalize measured data from an a

47、rbitrary length line to that of a 400 m test line. Following the procedure published by Ann Witrouw, et al. ), experimentation and modeling are used to obtain EM failure characteristic model parameters for a structure of a given length (initial resistance - Ro, incubation time ti, maximum resistance

48、 change possible Rmax, a time constant - , and constant - pc). Given these parameters is possible to model an equivalent lifetime for a 400 m, standard structure length, with all other design features being the same. Attempts using this alternative should be documented with procedure and intermediat

49、e results. 3.8 Connection to current tap Three (3) current tap to test-line designs types would be acceptable (others may be equally acceptable) . 3.8.1 Mirror design Top or bottom metal feed to lower metal as seen in Figure 2. This design can be used to source electron current from either end, and can be flipped vertically to evaluate another metal-via combination. A. Witrouw, Incubation, Time-Dependent Drift and Saturation During Al-Si-Cu Electromigration: Modeling and Implications for Desi