JEDEC JESD8-22B-2014 HSUL 12 LPDDR2 and LPDDR3 I O with Optional ODT.pdf

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1、JEDEC SOLID STATE TECHNOLOGY ASSOCIATIONJESD8-22BAPRIL 2014JEDECSTANDARDHSUL_12 LPDDR2 and LPDDR3 I/O(Revision of JESD8-22A, October 2012)with Optional ODTNOTICEJEDEC standards and publications contain material that has been prepared, reviewed, and approved through the JEDEC Board of Directors level

2、 and subsequently reviewed and approved by the JEDEC legal counsel.JEDEC standards and publications are designed to serve the public interest through eliminating misunderstandings between manufacturers and purchasers, facilitating interchangeability and improvement of products, and assisting the pur

3、chaser in selecting and obtaining with minimum delay the proper product for use by those other than JEDEC members, whether the standard is to be used either domestically or internationally.JEDEC standards and publications are adopted without regard to whether or not their adoption may involve patent

4、s or articles, materials, or processes. By such action JEDEC does not assume any liability to any patent owner, nor does it assume any obligation whatever to parties adopting the JEDEC standards or publications.The information included in JEDEC standards and publications represents a sound approach

5、to product specification and application, principally from the solid state device manufacturer viewpoint. Within the JEDEC organization there are procedures whereby a JEDEC standard or publication may be further processed and ultimately become an ANSI standard.No claims to be in conformance with thi

6、s standard may be made unless all requirements stated in the standard are met.Inquiries, comments, and suggestions relative to the content of this JEDEC standard or publication should be addressed to JEDEC at the address below, or refer to www.jedec.org under Standards and Documents for alternative

7、contact information.Published byJEDEC Solid State Technology Association 20143103 North 10th StreetSuite 240 SouthArlington, VA 22201-2107This document may be downloaded free of charge; however JEDEC retains the copyright on this material. By downloading this file the individual agrees not to charge

8、 for or resell the resulting material.PRICE: Contact JEDECPrinted in the U.S.A. All rights reservedPLEASE!DONT VIOLATETHELAW!This document is copyrighted by JEDEC and may not bereproduced without permission.For information, contact:JEDEC Solid State Technology Association3103 North 10th StreetSuite

9、240 SouthArlington, VA 22201-2107or refer to www.jedec.org under Standards-Documents/Copyright Information.JEDEC Standard No. 8-22BPage 1HSUL_12 LPDDR2 and LPDDR3 I/O with Optional ODT(From JEDEC Board Ballot JCB-14-01, formulated uder the cognizance of the JC-16 Committee on Interface Technology.)1

10、 ScopeThis standard defines the input, output specifications and ac test conditions for devices that are designed to operate in the High Speed Unterminated Logic (HSUL_12) logic switching range, nominally 0 V to 1.2 V. The standard may be applied to ICs operating with separate VDD and VDDQ supply vo

11、ltages.1.1 Standard structureThe standard is defined in four clauses:The first clause defines absolute maximum DC rating requirements common to all compliant ICs.The second clause defines pertinent supply voltage requirements.The third clause defines the minimum dc and ac input parametric requiremen

12、ts and ac test conditions for inputs on compliant devices. The fourth clause specifies the minimum required output characteristics of, and ac test conditions for, compliant outputs targeted for various application environments. Input parametric requirements and Output specifications are devided into

13、 two classes where necessary, Class I for LPDDR2, and Class II for LPDDR3 which operates at higer frequency than LPDDR2. 1.2 Rationale and assumptionsThe HSUL_12 standard has been developed particularly with the objective of providing a relatively simple upgrade path from MOS push-pull interface des

14、igns. The standard is particularly intended to improve the bus power consumption when operating at higher speed. This bus is mainly for point-to-point unterminated bus topology.The standard defines both the ac and dc input signal values. Making this distinction is important for the design of the hig

15、h gain, differential receivers that are required.The ac values indicate the voltage levels at which the receiver must meet its timing specifications.The dc values indicate the voltage levels at which the final logic state of the receiver is unambiguously defined. Once the receiver input has crossed

16、the ac value, the receiver will change to the new logic state. The new logic state will then be maintained as long as the input stays beyond the dc threshold. This approach is intended to provide predictable receiver timing in the presence of input waveform.JEDEC Standard No. 8-22BPage 22 Absolute M

17、aximum Ratings2.1 Absolute Maximum DC RatingsStresses greater than those listed may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is n

18、ot implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Table 1 Absolute Maximum DC Ratings3 AC however, VREFDQ may be VDDQ provided that VREFDQ 300mV. NOTE 2 VREFCA 0.6 x VDDCA; however, VREFCA may be VDDCA provided that VREFCA 300mV. Symbol Min Typ M

19、ax DRAM UnitVDDCA 1.14 1.20 1.3 Input Buffer Power VVDDQ 1.14 1.20 1.3 I/O Buffer Power VX X X X JEDEC Standard No. 8-22BPage 34 AC and DC Input Measurement Levels4.1 AC and DC Logic Input Levels for Single-Ended Signals4.1.1 AC and DC Input Levels for Single-Ended CA and CS_n SignalsTable 3 Single-

20、Ended AC and DC Input Levels for CA and CS_n Inputs, Class ISymbol Parameter1066 to 466 Mbps 400 to 200 MbpsUnit NotesMin Max Min MaxVIHCA(AC) AC input logic high Vref + 0.220 Note 2 Vref + 0.300 Note 2 V 1, 2VILCA(AC) AC input logic low Note 2 Vref - 0.220 Note 2 Vref - 0.300 V 1, 2VIHCA(DC) DC inp

21、ut logic high Vref + 0.130 VDDCA Vref + 0.200 VDDCA V 1VILCA(DC) DC input logic low VSSCA Vref - 0.130 VSSCA Vref - 0.200 V 1VRefCA(DC) Reference Voltage for CA and CS_n inputs0.49 * VDDCA0.51 * VDDCA0.49 * VDDCA0.51 * VDDCAV3, 4NOTE 1 For CA and CS_n input only pins. Vref = VrefCA(DC).NOTE 2 See 5.

22、5, Overshoot and undershoot specificationsNOTE 3 The ac peak noise on VRefCAmay not allow VRefCAto deviate from VRefCA(DC)by more than +/-1% VDDCA (for reference: approx. +/- 12 mV).NOTE 4 For reference: approx. VDDCA/2 +/- 12 mV.Table 4 Single-Ended AC and DC Input Levels for CA and CS_n inputs, Cl

23、ass IISymbol Parameter1333/1600 1866/2133Unit NotesMin Max Min MaxVIHCA(AC) AC input logic high VRef+ 0.150 Note 2 VRef+ 0.135 Note 2 V 1, 2VILCA(AC) AC input logic low Note 2 VRef- 0.150 Note 2 VRef- 0.135 V 1, 2VIHCA(DC) DC input logic high VRef+ 0.100 VDDCAVRef+ 0.100 VDDCAV 1VILCA(DC) DC input l

24、ogic low VSSCAVRef- 0.100 VSSCAVRef- 0.100 V 1VRefCA(DC) Reference Voltage for CA and CS_n inputs0.49 * VDDCA0.51 * VDDCA0.49 * VDDCA0.51 * VDDCAV 3, 4NOTE 1 For CA and CS_n input only pins. VRef= VRefCA(DC).NOTE 2 See 5.5, Overshoot and undershoot specificationsNOTE 3 The ac peak noise on VRefCAmay

25、 not allow VRefCAto deviate from VRefCA(DC)by more than +/-1% VDDCA(for reference: approx. +/- 12 mV).NOTE 4 For reference: approx. VDDCA/2 +/- 12 mV.JEDEC Standard No. 8-22BPage 44.1 AC and DC Logic Input Levels for Single-Ended Signals4.1.2 AC and DC Input Levels for CKETable 5 Single-Ended AC and

26、 DC Input Levels for CKE,Class I4.1.3 AC and DC Input Levels for Single-Ended Data SignalsSymbol Parameter Min Max Unit NotesVIHCKECKE Input High Level 0.8 * VDDCA Note 1 V 1VILCKECKE Input Low Level Note 1 0.2 * VDDCA V 1NOTE 1 See 5.5, Overshoot and undershoot specificationsTable 6 Single-Ended AC

27、 and DC Input Levels for CKE,Class IISymbol Parameter Min Max Unit NotesVIHCKECKE Input High Level 0.65 * VDDCA Note 1 V 1VILCKECKE Input Low Level Note 1 0.35 * VDDCA V 1NOTE 1 See 5.5, Overshoot and undershoot specificationsTable 7 Single-Ended AC and DC Input Levels for DQ and DM,Class ISymbol Pa

28、rameter1066 to 466 Mbps 400 to 200 MbpsUnit NotesMin Max Min MaxVIHDQ(AC) AC input logic high Vref + 0.220 Note 2 Vref + 0.300 Note 2 V 1, 2VILDQ(AC) AC input logic low Note 2 Vref - 0.220 Note 2 Vref - 0.300 V 1, 2VIHDQ(DC) DC input logic high Vref + 0.130 VDDQ Vref + 0.200 VDDQ V 1VILDQ(DC) DC inp

29、ut logic low VSSQ Vref - 0.130 VSSQ Vref - 0.200 V 1VRefDQ(DC)Reference Voltage for DQ, DM inputs0.49 * VDDQ0.51 * VDDQ0.49 * VDDQ0.51 * VDDQV3, 4NOTE 1 For DQ input only pins. Vref = VrefDQ(DC).NOTE 2 See 5.5, Overshoot and undershoot specificationsNOTE 3 The ac peak noise on VRefDQmay not allow VR

30、efDQto deviate from VRefDQ(DC)by more than +/-1% VDDQ (for reference: approx. +/- 12 mV).NOTE 4 For reference: approx. VDDQ/2 +/- 12 mV.JEDEC Standard No. 8-22BPage 54.1 AC and DC Logic Input Levels for Single-Ended Signals (contd)4.1.3 AC and DC Input Levels for Single-Ended Data Signals (contd)Tab

31、le 8 Single-Ended AC and DC Input Levels for DQ and DM,Class IISymbol Parameter1333/1600 1866/2133Unit NotesMin Max Min MaxVIHDQ(AC) AC input logic high VRef+ 0.150 Note 2 VRef+ 0.135 Note 2 V 1, 2, 5VILDQ(AC) AC input logic low Note 2 VRef- 0.150 Note 2 VRef- 0.135 V 1, 2, 5VIHDQ(DC) DC input logic

32、 high VRef+ 0.100 VDDQVRef+ 0.100 VDDQV 1VILDQ(DC) DC input logic low VSSQVRef- 0.100 VSSQVRef- 0.100 V 1VRefDQ(DC)(DQ ODT disabled)Reference Voltage for DQ, DM inputs0.49 * VDDQ0.51 * VDDQ0.49 * VDDQ0.51 * VDDQV 3, 4VRefDQ(DC)(DQ ODT enabled)Reference Voltage for DQ, DM inputsVODTR/2 - 0.01 * VDDQV

33、ODTR/2 + 0.01 * VDDQVODTR/2 - 0.01 * VDDQVODTR/2 + 0.01 * VDDQV 3, 5, 6NOTE 1 For DQ input only pins. VRef= VRefDQ(DC).NOTE 2 See 5.5, Overshoot and undershoot specificationsNOTE 3 The ac peak noise on VRefDQmay not allow VRefDQto deviate from VRefDQ(DC)by more than +/-1% VDDQ(for reference: approx.

34、 +/- 12 mV).NOTE 4 For reference: approx. VDDQ/2 +/- 12 mV.NOTE 5 For reference: approx. VODTR/2 +/- 12 mV.NOTE 6 The nominal mode register programmed value for RODT and the nominal controller output impedance RON are used for the calculation of VODTR. For testing purposes a controller RONvalue of 5

35、0 W is used.VODTR2RON RTT+RON RTT+- VDDQ=JEDEC Standard No. 8-22BPage 64.2 Vref TolerancesThe dc-tolerance limits and ac-noise limits for the reference voltages VRefCAand VRefDQare illustrated in Figure 1. It shows a valid reference voltage VRef(t) as a function of time. (VRefstands for VRefCAand VR

36、efDQlikewise). VDD stands for VDDCA for VRefCAand VDDQ for VRefDQ. VRef(DC) is the linear average of VRef(t) over a very long period of time (e.g., 1 sec) and is specified as a fraction of the linear average of VDDQ or VDDCA also over a very long period of time (e.g., 1 sec). This average has to mee

37、t the min/max requirements in Table 3, Table 4, Table 7, and Table 8. Furthermore VRef(t) may temporarily deviate from VRef(DC)by no more than +/- 1% VDD. Vref(t) cannot track noise on VDDQ or VDDCA if this would send Vref outside these specifications.: The voltage levels for setup and hold time mea

38、surements VIH(AC), VIH(DC), VIL(AC)and VIL(DC)are dependent on VRef. “VRef“ shall be understood as VRef(DC), as defined in Figure 1. This clarifies that dc-variations of VRefaffect the absolute voltage a signal has to reach to achieve a valid high or low level and therefore the time to which setup a

39、nd hold is measured. System timing and voltage budgets need to account for VREFdeviations from the optimum position within the data-eye of the input signals. This also clarifies that the LPDDR2 and LPDDR3 setup/hold specification and derating values need to include time and voltage associated with V

40、Refac-noise. Timing and voltage effects due to ac-noise on VRefup to the specified limit (+/-1% of VDD) are included in LPDDR2 and LPDDR3 timings and their associated deratings.VDDVSSVRef(DC)nominalVRef(DC)VRefac-noisevoltagetimeVRef(DC)maxVRef(DC)minVRef(t)Figure 1 Illustration of VRef(DC)tolerance

41、 and VRefac-noise limitsJEDEC Standard No. 8-22BPage 74.3 Input SignalFigure 2 Input SignalVIH(AC)VIH(DC)0.600VVIL(DC)VIL(AC)0.600VMinimum VIL and VIH Levels1.200V0.000V-0.350VVIL and VIH Levels With RingbackVDD + 0.35V VDDVIH(AC)VIH(DC)VREF + AC noiseVREF + DC errorVREF - DC errorVREF - AC noiseVIL

42、(DC)VIL(AC)VSSVSS - 0.35VNOTE 1 Numbers reflect nominal values. NOTE 2 For CA0-9, CK_t, CK_c,and CS_n, VDD stands for VDDCA. For DQ, DM/DNV, DQS_t, and DQS_c, VDD stands for VDDQ.NOTE 3 For CA0-9, CK_t, CK_c, and CS_n, VSS stands for VSSCA. For DQ, DM/DNV, DQS_t, and DQS_c, VSS stands for VSSQ. JEDE

43、C Standard No. 8-22BPage 84.4 AC and DC Logic Input Levels for Differential Signals4.4.1 Differential signal definitionFigure 3 Definition of differential ac-swing and “time above ac-level” tDVACVIHDIFF(AC)MINVIHDIFF(DC)MINVILDIFF(DC)MAXVILDIFF(AC)MAX0.0CK_t - CK_cDQS_t - DQS_chalf cycletDVACtDVACdi

44、fferentialtimevoltageJEDEC Standard No. 8-22BPage 94.4 AC and DC Logic Input Levels for Differential Signals (contd)4.4.2 Differential swing requirements for clock (CK_t-CK_c) and strobe (DQS_t-DQS_c)Table 10 Allowed time before ringback (tDVAC) for CK_t-CK_c and DQS_t-DQS_c, Class ITable 9 Differen

45、tial AC and DC Input LevelsSymbol Parameter Min Max Unit NotesVIHdiff(dc)Differential input high 2 x (VIH(dc) - Vref)note 3 V 1VILdiff(dc)Differential input logic low Note 3 2 x (Vref - VIL(dc)V1VIHdiff(ac)Differential input high ac2 x (VIH(ac) - Vref)Note 3 V 2VILdiff(ac)Differential input low ac n

46、ote 32 x (Vref - VIL(ac)V2NOTE 1 Used to define a differential signal slew-rate.NOTE 2 For CK_t - CK_c use VIH/VIL(ac) of CA and VREFCA; for DQS_t - DQS_c, use VIH/VIL(ac) of DQs and VREFDQ; if a reduced ac-high or ac-low level is used for a signal group, then the reduced level applies also here.NOT

47、E 3 These values are not defined, however the single-ended signals CK_t, CK_c, DQS_t, and DQS_c need to be within the respective limits (VIH(dc) max, VIL(dc)min) for single-ended signals as well as the limitations for overshoot and undershoot. Refer to “Overshoot and undershoot specifications” on oa

48、ge 20.NOTE 4 For CK_t and CK_c, Vref = VrefCA(DC). For DQS_t and DQS_c, Vref = VrefDQ(DC). Slew Rate V/nstDVAC ps |VIH/Ldiff(ac)| = 440mVtDVAC ps |VIH/Ldiff(ac)| = 600mVmin min 4.0 175 754.0 170 573.0 167 502.0 163 381.8 162 341.6 161 291.4 159 221.2 155 131.0 150 08.0 58 - 48 - 40 - 34 -8.0 58 - 48

49、 - 40 - 34 -7.0 56 - 46 - 39 - 33 -6.0 53 - 43 - 36 - 30 -5.0 50 - 40 - 33 - 27 -4.0 45 - 35 - 29 - 23 -3.0 37 - 27 - 21 - 15 - 3.0 37 - 27 - 21 - 15 -JEDEC Standard No. 8-22BPage 114.4 AC and DC Logic Input Levels for Differential Signals (contd)4.4.3 Single-ended requirements for differential signalsEach individual component of a differential signal (CK_t, DQS_t, CK_c, or DQS_c) has also to comply with certain requirements for single-ended signals.CK_t and CK_c shall meet VSEH(ac)min / VSEL(ac)max