JEDEC JESD8-21B-2018 POD135 1 35 V Pseudo Open Drain I O.pdf

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1、JEDEC SOLID STATE TECHNOLOGY ASSOCIATIONJESD8-21BMARCH 2018JEDECSTANDARDPOD135 - 1.35 V Pseudo Open(Revision of JESD8-21A, SEPTEMBER 2013)Drain I/ONOTICEJEDEC standards and publications contain material that has been prepared, reviewed, and approved through the JEDEC Board of Directors level and sub

2、sequently reviewed and approved by the JEDEC legal counsel.JEDEC standards and publications are designed to serve the public interest through eliminating misunderstandings between manufacturers and purchasers, facilitating interchangeability and improvement of products, and assisting the purchaser i

3、n selecting and obtaining with minimum delay the proper product for use by those other than JEDEC members, whether the standard is to be used either domestically or internationally.JEDEC standards and publications are adopted without regard to whether or not their adoption may involve patents or art

4、icles, materials, or processes. By such action JEDEC does not assume any liability to any patent owner, nor does it assume any obligation whatever to parties adopting the JEDEC standards or publications.The information included in JEDEC standards and publications represents a sound approach to produ

5、ct specification and application, principally from the solid state device manufacturer viewpoint. Within the JEDEC organization there are procedures whereby a JEDEC standard or publication may be further processed and ultimately become an ANSI standard.No claims to be in conformance with this standa

6、rd may be made unless all requirements stated in the standard are met.Inquiries, comments, and suggestions relative to the content of this JEDEC standard or publication should be addressed to JEDEC at the address below, or refer to www.jedec.org under Standards and Documents for alternative contact

7、information.Published byJEDEC Solid State Technology Association 20183103 North 10th StreetSuite 240 SouthArlington, VA 22201-2107This document may be downloaded free of charge; however JEDEC retains the copyright on this material. By downloading this file the individual agrees not to charge for or

8、resell the resulting material.PRICE: Contact JEDECPrinted in the U.S.A. All rights reservedPLEASE!DONT VIOLATETHELAW!This document is copyrighted by JEDEC and may not bereproduced without permission.For information, contact:JEDEC Solid State Technology Association3103 North 10th StreetSuite 240 Sout

9、hArlington, VA 22201-2107or refer to www.jedec.org under Standards-Documents/Copyright Information.JEDEC Standard No. 8-21BPage 1POD135 - 1.35V PSEUDO OPEN DRAIN I/O(From JEDEC Board Ballot JCB-18-01, formulated uder the cognizance of the JC-16 Committee on Interface Technology.)1 ScopeThis standard

10、 defines the dc and ac single-ended (data) and differential (clock) operating conditions, I/O impedances, and the termination and calibration scheme for 1.35V Pseudo Open Drain I/Os. The 1.35V Pseudo Open Drain interface, also known as POD135, is primarily used to communicate with GDDR5 or GDDR5M SG

11、RAM devices.Multiple Classes of POD135 are expected to reside within the family of POD135 interfaces in order to accommodate various device and market applications. The various classes standardized within the context of POD135 are documented in the appendices of this document (e.g., POD135/Class A,

12、POD135/Class B, etc). The core of this standard defines documents the subset of values common to all Classes of POD135 and documents specification items left to definition within a specific Class as denoted by CDV which is defined as Class Dependent Value.The values specific to each particular class

13、 of POD135 are found in the annexes. See specific Class tables for further details. (Note it does not follow that all specification values defined in a given Class are necessarily different from the matching parameter in other Class within POD135. Multiple Classes may reuse a given specification val

14、ue if appropriate to the Class requirements.)Classes were not part of the original POD135 specification. With the addition of Classes the original POD135 values remain unchanged and grouped as POD135/Class A and POD135/Class C. The updates to the specification are included in POD135/Class B and POD1

15、35/Class D. As other devices or market applications are defined, they may use one of the already defined Class(es) or define a new Class. JEDEC Standard No. 8-21BPage 22 Core POD135 Interface StandardNOTE 1 GDDD5 SGRAM devices are designed to tolerate PCB designs with separate VDD and VDDQ power reg

16、ulators.NOTE 2 AC noise in the system is estimated at 50mV pk-pk for the purpose of DRAM design.NOTE 3 External VREFC is to be provided by the controller as there is no other alternative supply.NOTE 4 DQ/DBI_n input slew rate must be greater than or equal to 2.7V/ns. The slew rate is measured betwee

17、n VREFD crossing and VIHD(AC) or VILD(AC) or VREFD2 crossing and VIHD2(AC) or VILD2(AC).NOTE 5 ADD/CMD input slew rate must be greater than or equal to 2.7V/ns. The slew rate is measured between VREFC crossing and VIHA(AC) or VILA(AC).NOTE 6 Applicable to an interface with a single VREF for the devi

18、ce.NOTE 7 Applicable to an interface with multiple VREF pins and levelsTable 1 DC Operating ConditionsPOD135Parameter Symbol Min Typ Max Unit NoteDevice Supply Voltage VDD 1.3095 1.35 1.3905 V 1Output Supply Voltage VDDQ 1.3095 1.35 1.3905 V 1Reference Voltage VREF CDV CDV V 2, 6Reference Voltage fo

19、r DQ and DBI_n pins VREFD CDV CDV V 2, 7Reference Voltage for DQ and DBI_n pins VREFD2 CDV CDV V 2, 7External Reference Voltage for address and commandVREFC CDV CDV V 3, 7DC Input Logic HIGH Voltage VIH (DC) CDV V 6DC Input Logic LOW Voltage VIL (DC) CDV V 6DC Input Logic HIGH Voltage for address an

20、d commandVIHA (DC) CDV V 7DC Input Logic LOW Voltage for address and commandVILA (DC) CDV V 7DC Input Logic HIGH Voltage for DQ and DBI_n pins with VREFDVIHD (DC) CDV V 7DC Input Logic LOW Voltage for DQ and DBI_n pins with VREFDVILD (DC) CDV V 7DC Input Logic HIGH Voltage for DQ and DBI_n pins with

21、 VREFD2VIHD2 (DC) CDV V 7DC Input Logic LOW Voltage for DQ and DBI_n pins with VREFD2VILD2 (DC) CDV V 7Input Logic HIGH Voltage for RESET_n, SEN, MFVIHR CDV V 7Input Logic LOW Voltage for RESET_n, SEN, MFVILR CDV V 7Input logic HIGH voltage for EDC1/2 (x16 mode detect)VIHX CDV V 7Input logic LOW vol

22、tage for EDC1/2 (x16 mode detect)VILX CDV V 7Input Leakage CurrentAny Input 0V = VIN= VDDQ(All other pins not under test = 0V) Il AOutput Leakage Current (DQs are disabled; 0V = Vout = VDDQ)Ioz AOutput Logic LOW Voltage VOL (DC) 0.56 VJEDEC Standard No. 8-21BPage 32 Core POD135 Interface Standard (c

23、ontd)NOTE 1 Applicable to an interface with a single VREF for the device. See Class C in Annex A.NOTE 2 Applicable to an interface with multiple VREF pins and levels. See Class A and B in Annex A.Figure 1 Voltage WaveformTable 2 AC Operating ConditionsPOD135Parameter Symbol Min Typ Max Unit NoteAC I

24、nput Logic HIGH Voltage VIH (AC) CDV V 1AC Input Logic Low Voltage VIL (AC) CDV V 1AC Input Logic HIGH Voltage for address and commandVIHA (AC) CDV V 2AC Input Logic LOW Voltage for address and commandVILA (AC) CDV V 2AC Input Logic HIGH Voltage for DQ and DBI_n pins with VREFDVIHD (AC) CDV V 2AC In

25、put Logic LOW Voltage for DQ and DBI_n pins with VREFDVILD (AC) CDV V 2AC Input Logic HIGH Voltage for DQ and DBI_n pins with VREFD2VIHD2 (AC) VREFD2 + 0.36 V 2AC Input Logic LOW Voltage for DQ and DBI_n pins with VREFD2VILD2 (AC) VREFD2 - 0.36 V 2VIL (AC)VIL (DC)VREF - DC NoiseVREF - DC NoiseVREF +

26、 DC NoiseVREF + AC NoiseVIH (DC)VIH (AC)VOHVIN (AC) - Provides marginbetween VOL (MAX) andVIL (AC)VDDQVOL (MAX)System Noise Margin (Power/Ground, Crosstalk, Signal Integrity Attenuation)OutputInputNOTE VREF, VIH, VIL refer towhichever VREFxx (VREFD, VREFD2, or VREFC) is being used. JEDEC Standard No

27、. 8-21BPage 42 Core POD135 Interface Standard (contd)NOTE 1 This provides a minimum of 0.845V to a maximum of 1.045V, and is nominally 70% of VDDQ with POD135. DRAM timings relative to CK_t/CK_c cannot be guaranteed if these limits are exceeded.NOTE 2 For AC operations, all DC clock requirements mus

28、t be satisfied as well.NOTE 3 The value of VIXCK and VIXWCK is expected to equal 70% VDDQ for the transmitting device and must track variations in the DC level of the same.NOTE 4 VIDCK is the magnitude of the difference between the input level in CK_t and the input level on CK_c. The input reference

29、 level for signals other than CK_t and CK_c is VREFC.NOTE 5 VIDWCK is the magnitude of the difference between the input level in WCK_t and the input level on WCK_c. The input reference level for signals other than WCK_t and WCK_c is either VREFD, VREFD2 or the internal VREFD. S ee Class A and B for

30、the type of VREFD supported.NOTE 6 The CK_t and CK_c input reference level (for timing referenced to CK_t and CK_c) is the point at which CK_t and CK_c cross. NOTE 7. The WCK_t and WCK_c input reference level (for timing referenced to WCK_t and WCK_c) is the point at which WCK_t and WCK_c cross. NOT

31、E 8 VREFD is either VREFD, VREFD2 or the internal VREFD. See Class A and B for the type of VREFD supported.NOTE 9 The slew rate is measured between VREFC crossing and VIXCK(AC).NOTE 10 The slew rate is measured between VREFD crossing and VIXWCK(AC).NOTE 11 Figure 3 illustrates the exact relationship

32、 between (CK_t-CK_c) or (WCK_t-WCK_c) and VID(AC), VID(DC) and tDVACNOTE 12 Ringback below VID(DC) is not allowed.NOTE 13 tDVACis not measured in and of itself as a compliance specification, but is relied upon in measurement of clock operating conditions and clock related parameters.NOTE 14 Applicab

33、le to an interface with multiple VREF pins and levels (See Class A and B in Appendix A).Table 3 Clock Input Operating ConditionsPOD135Parameter Symbol Min Max Unit NoteClock Input Mid-Point Voltage; CK_t and CK_c VMP (DC) VREFC - 0.10 VREFC + 0.10 V 1, 6Clock Input Differential Voltage; CK_t and CK_

34、cVID or VIDCK (DC)CDV V 4, 6Clock Input Differential Voltage; CK_t and CK_c VID or VIDCK (AC)CDV V 2, 4, 6Clock Input Differential Voltage; WCK_t and WCK_c VIDWCK (DC) CDV V 5, 7, 14Clock Input Differential Voltage; WCK_t and WCK_c VIDWCK (AC) CDV2, 5, 7, 14Clock Input Voltage Level; CK_t, CK_c, WCK

35、_t and WCK_c single ended VIN -0.30 VDDQ + 0.30CK_t/CK_c Single ended slew rate CKslew 2.7 V/ns 9WCK_t/WCK_c Single ended slew rate WCKslew 2.7 V/ns 10, 14Clock Input Crossing Point Voltage; CK_t and CK_cVIX or VIXCK (AC)VREFC - 0.108 VREFC + 0.108 V 2, 3, 6Clock Input Crossing Point Voltage; WCK_t

36、and WCK_cVIXWCK (AC) VREFD - 0.09 VREFD + 0.09 V2, 3, 7, 8, 14Allowed time before ringback of CK/WCK below VIDCK/WCK(AC)tDVACps11, 12, 13, 14JEDEC Standard No. 8-21BPage 52 Core POD135 Interface Standard (contd)Figure 2 Clock WaveformFigure 3 Definition of differential ac-swing and “time above ac-le

37、vel” tDVACVIX(AC)CK_cCK_tMaximum Clock LevelMinimum Clock LevelVID (AC)VID (DC)VMP (DC)0VID (AC) MINtDVACtDVAChalf cycletimeDifferentialInput Voltage(i.e. WCK_t - WCK_c, CK_t- CK_c)VID (DC) MIN-(VID (DC) MIN)-(VID (AC) MIN)JEDEC Standard No. 8-21BPage 62 Core POD135 Interface Standard (contd)The Dri

38、ver and Termination impedances are derived from the following test conditions under worst case process corners:1. Nominal 1.35V (VDD/VDDQ)2. Power the DRAM device and calibrate the output drivers and termination to eliminate process variation at 25 C.3. Reduce temperature to 10 C recalibrate.4. Redu

39、ce temperature to 0 C and take the fast corner measurement.5. Raise temperature to 75 C and recalibrate6. Raise temperature to 85 C and take the slow corner measurement7. Reiterate 2 to 6 with VDD/VDDQ 1.3095V8. Reiterate 2 to 6 with VDD/VDDQ 1.3905V9. All obtained Driver and Termination IV characte

40、ristics have to be bounded by the specified MIN and MAX IV characteristicsThe following values (Ideal with +/- 10% min/max) are targets for the designer and are not required to be met. Vendor datasheets should be consulted for further details. It is expected that the characteristics of the real curv

41、es will have some non-linearity as shown in Figure 6 and Figure 7. This may help to reduce the overall capacitance and boost performance. It is up to the designer to find the optimum combination of lin-earity and capacitance for best Rx and Tx performance. Table 4 1.35V I/O ImpedancesPull-Down Chara

42、cteristic at 40 ohms Pull-Up/Termination Characteristic at 60 ohmsVoltage (V) MIN(mA) Ideal(mA) MAX(mA) Voltage (V) MIN(mA) Ideal(mA) MAX(mA)0.1 2.25 2.50 2.75 0.1 -1.50 -1.67 -1.830.2 4.50 5.00 5.50 0.2 -3.00 -3.33 -3.670.3 6.75 7.50 8.25 0.3 -4.50 -5.00 -5.500.4 9.00 10.00 11.00 0.4 -6.00 -6.67 -7

43、.330.5 11.25 12.50 13.75 0.5 -7.50 -8.33 -9.170.6 13.50 15.00 16.50 0.6 -9.00 -10.00 -11.000.7 15.75 17.50 19.25 0.7 -10.50 -11.67 -12.830.8 18.00 20.00 22.00 0.8 -12.00 -13.33 -14.670.9 20.25 22.50 24.75 0.9 -13.50 -15.00 -16.501.0 22.50 25.00 27.50 1.0 -15.00 -16.67 -18.331.1 24.75 27.50 30.25 1.1

44、 -16.50 -18.33 -20.171.2 27.00 30.00 33.00 1.2 -18.00 -20.00 -22.001.3 29.25 32.50 35.75 1.3 -19.50 -21.67 -23.831.35 30.15 33.75 37.12 1.35 -20.25 -22.50 -24.75JEDEC Standard No. 8-21BPage 72 Core POD135 Interface Standard (contd)Figure 4 Target Pull Down Characteristic at 40 ohmsFigure 5 Target Pu

45、ll Up/Termination Characteristic at 60 ohms45403530201510500.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3ideal MaxmAVolts25Min0-5-10mAVolts0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3-15-20-25-30idealMin MaxJEDEC Standard No. 8-21BPage 82 Core POD135 Interface Standard (contd)Figure 6 Ex

46、ample of Non-linearity, Pull Down Characteristic at 40 ohmsFigure 7 Example of Non-linearity, Pull Up/Termination Characteristic at 60 ohms45.0040.0035.0030.0020.0015.0010.005.000.000.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3ideal non-linearitymAVolts25.000.00-5.00-10.00ideal non-linearitymA

47、Volts0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3-15.00-20.00-25.00-30.00JEDEC Standard No. 8-21BPage 93 Additional Background InformationThe POD I/O system is optimized for small systems with data rates exceeding 2.0 Gbps. The system allows a single Master device to control one or two slaves

48、 in the case of GDDR5. The POD driver uses a 40/60 Ohm output impedance that drives into a 60 Ohm equivalent terminator tied to VDDQ. Single, dual and quad load systems are shown as follows:Figure 8 System ConfigurationsThe POD Master I/O cell is comprised of a 40/60 Ohm driver and a terminator of 6

49、0 Ohms. The Master POD cells terminator is disabled when the output driver is enabled. The basic cell is shown in Figure 9.Figure 9 Master I/O CellVDDQ120 Ohm40/60 Ohm120 OhmADD/CMDVDDQ60 Ohm40/60 OhmData Bit or ADD/CMD2 Slaves1 SlaveDQOutput DataOutput EnableVSSQVDDQ60 Ohm TerminatorEnabled when receiving60 Ohm pull-up and 40 Ohm pull-downwhen transmittingJEDEC Standard No. 8-21BPage 103 Additional Background Information (contd)The POD Slave I/O cell is comprised of a 40/60 ohm driver and programmable terminator of 60 or 120 ohms for GDDR5. The Slav