JEDEC JESD8-2-1993 Standard for Operating Voltages and Interface Levels for Low Voltage Emitter-Coupled Logic (ECL) Integrated Circuits《低压发射极耦合逻辑(ECL)集成电路的运行电压和接口水平标准》.pdf

《JEDEC JESD8-2-1993 Standard for Operating Voltages and Interface Levels for Low Voltage Emitter-Coupled Logic (ECL) Integrated Circuits《低压发射极耦合逻辑(ECL)集成电路的运行电压和接口水平标准》.pdf》由会员分享，可在线阅读，更多相关《JEDEC JESD8-2-1993 Standard for Operating Voltages and Interface Levels for Low Voltage Emitter-Coupled Logic (ECL) Integrated Circuits《低压发射极耦合逻辑(ECL)集成电路的运行电压和接口水平标准》.pdf（7页珍藏版）》请在麦多课文档分享上搜索。

1、Cu I ELECTRONIC IN DUSTRIES ASSOCIATION ENGINEERING DEPARTMENT EIA JESDB-2 73 3234600 0505484 087 Reproduced y GLOBAL ENGINEERING DOCUMENTS wj Tk hirrbn of EM Under Royalty Amem Output Load = 50 R to -2 V Output LOW Volta e Trackin per volt o vEJvE* 100% I 65 mV 65 va Output HIGH Volta e Tracking pe

2、r voit of 10% I V, 1 I 35 I mV I I 35 1 OOk oo c tc MIN -1 165 -1810 -1025 -1810 -1 380 -1 035 0.5 ECL 75 O c MAX -880 -1 475 -880 -1 620 -1 260 -1610 35 65 NOTE: VES is the internally generated Bias Voltage which is used to set the input and output thresholds and may be provided as an output on the

3、 device. The VBB output could be used to supply the input threshold level to one side of a differential input pair in a single ended reception mode. VIHmin and VILmax represent the guaranteed input HIGH and LOW threshold levels, respectively, for the device. VOH(C) anciV0uc) represent the output HIG

4、H and LOW threshold levels, respectively, with the inputs set to their respective threshold levels. See Appendix A for a graphic representation of these parameters. EIA JESDB-2 93 m 3234b00 0505490 380 m JEDEC Standard No. 8-2 Page 3 APPENDIX A Figure 1. NPICAL ECL TRANSFER CURVE AND TEST POINTS 7Test Points I Vi, (Input Voltage) Measurements are made at the Test Points under the conditions defined in Section 4 (Vi, = VILrnax OR VIHmin; Vout = VoL(c)rnax OR VoH(c)rnin) to ensure that VBB is centered on devices which do not provide a VBB Output Reference Voltage terminal.