JEDEC JESD51-31-2008 Thermal Test Environment Modifications for MultiChip Packages《用于多片包装的热试验环境改善》.pdf

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1、JEDEC STANDARD Thermal Test Environment Modifications for MultiChip Packages JESD51-31 JULY 2008 JEDEC SOLID STATE TECHNOLOGY ASSOCIATION NOTICE JEDEC standards and publications contain material that has been prepared, reviewed, and approved through the JEDEC Board of Directors level and subsequentl

2、y reviewed and approved by the JEDEC legal counsel. JEDEC standards and publications are designed to serve the public interest through eliminating misunderstandings between manufacturers and purchasers, facilitating interchangeability and improvement of products, and assisting the purchaser in selec

3、ting and obtaining with minimum delay the proper product for use by those other than JEDEC members, whether the standard is to be used either domestically or internationally. JEDEC standards and publications are adopted without regard to whether or not their adoption may involve patents or articles,

4、 materials, or processes. By such action JEDEC does not assume any liability to any patent owner, nor does it assume any obligation whatever to parties adopting the JEDEC standards or publications. The information included in JEDEC standards and publications represents a sound approach to product sp

5、ecification and application, principally from the solid state device manufacturer viewpoint. Within the JEDEC organization there are procedures whereby a JEDEC standard or publication may be further processed and ultimately become an ANSI standard. No claims to be in conformance with this standard m

6、ay be made unless all requirements stated in the standard are met. Inquiries, comments, and suggestions relative to the content of this JEDEC standard or publication should be addressed to JEDEC at the address below, or call (703) 907-7559 or www.jedec.org Published by JEDEC Solid State Technology A

7、ssociation 2008 3103 North 10thStreet Suite 240 South Arlington, VA 22201-2107 This document may be downloaded free of charge; however JEDEC retains the copyright on this material. By downloading this file the individual agrees not to charge for or resell the resulting material. PRICE: Please refer

8、to the current Catalog of JEDEC Engineering Standards and Publications online at http:/www.jedec.org/Catalog/catalog.cfm Printed in the U.S.A. All rights reserved PLEASE! DONT VIOLATE THE LAW! This document is copyrighted by JEDEC and may not be reproduced without permission. Organizations may obtai

9、n permission to reproduce a limited number of copies through entering into a license agreement. For information, contact: JEDEC Solid State Technology Association 3103 North 10thStreet Suite 240 South Arlington, Virginia 22201-2107 or call (703) 907-7559 JEDEC Standard No. 51-31 -i- THERMAL TEST ENV

10、IRONMENT MODIFICATIONS FOR MULTICHIP PACKAGES Foreword This document was prepared by the JEDEC JC15 committee to document appropriate modifications needed for Multi-Chip Packages using the thermal test environmental conditions specified in the JESD51 series of specifications. Multi-Chip Packages as

11、described in the overview document of this series of specifications are packages with more than one distinct heat source. Introduction Multi-Chip Packages as described in the overview document of this series of specifications are packages with more than one distinct heat source. Because the thermal

12、performance of the package can change with the proportion of heat dissipated in each source, more detailed information is required to specify the thermal performance of the packages than is required for a single chip package. Multi-Chip Packages can be separated into two general types: (1) packages

13、which are symmetrical in the x-y directions relative to the center, and (2) packages for which the chips or heat sources are distributed and there is no assumption of symmetry for the heat sources. JEDEC Standard No. 51-31 -ii- JEDEC Standard No. 51-31 Page 1 THERMAL TEST ENVIRONMENT MODIFICATIONS F

14、OR MULTICHIP PACKAGES (From JEDEC Board Ballot JCB-08-34, formulated under the cognizance of the JC-15 Committee on electrical and Thermal Characterization Techniques for Electronic packages and Interconnects.) 1 Scope This document specifies the appropriate modifications needed for Multi-Chip Packa

15、ges to the thermal test environmental conditions specified in the JESD51 series of specifications. The data obtained from methods of this document are the raw data used to document the thermal performance of the package. The use of this data will be documented in JESD51-XX, “Guideline to Support Eff

16、ective Use of MCP Thermal Measurements” which is being prepared. 2 Normative references The following normative documents contain provisions that, through reference in this text, constitute provisions of this standard. For dated references, subsequent amendments to, or revisions of, any of these pub

17、lications do not apply. However, parties to agreements based on this standard are encouraged to investigate the possibility of applying the most recent editions of the normative documents indicated below. For undated references, the latest edition of the normative document referred to applies. 1. JE

18、SD51, Methodology for the Thermal Measurement of Component Packages (Single Semiconductor Devices). This is the overview document for this series of specifications. 2. JESD51-1, Integrated Circuit Thermal Measurement Method - Electrical Test Method. 3. JESD51-2, Integrated Circuit Thermal Test Metho

19、d Environmental Conditions Natural Convection (Still Air). 4. JESD51-3, Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages. 5. JESD51-4, Thermal Test Chip Guideline (Wire Bond Type Chip). 6. JESD51-5, Extension of Thermal Test Board Standards for Packages with Direct The

20、rmal Attachment Mechanisms. 7. JESD51-6, Integrated Circuit Thermal Test Method Environmental Conditions Forced Convection (Moving Air). JEDEC Standard No. 51-31 Page 2 2 Normative references (contd) 8. JESD51-7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages. 9. JE

21、SD51-8, Integrated Circuit Thermal Test Method Environmental Conditions Junction-to-Board. 10. JESD51-9, Test Boards for Area Array Surface Mount Package Thermal Measurements. 11. JESD51-10, Test Boards for Through-Hole Perimeter Leaded Package Thermal. Measurements. 12. JESD51-11, Test Boards for T

22、hrough-Hole Area Array Leaded Package Thermal. Measurements. 13. JESD51-12, Guidelines for Reporting and Using Electronic Package Thermal Information. 3 Terms and definitions For the purposes of this standard, the terms and definitions given in JESD51 series of specifications1 13 and the following a

23、pply: MCP: Multi-Chip Package. A package containing more than one heat source. TJiA(P1,P2,Pn) or DeltaT-JiA(P1,P2,Pn): Temperature rise for each source, i, relative to the ambient temperature at the power dissipation of P1, P2, etc for source 1, 2, etc. TTA(x,y)(P1,P2,Pn) or DeltaT-JT(x,y) (P1,P2,Pn

24、): Temperature rise of the top of the package relative to the ambient temperature at the power dissipation of P1, P2, etc for source 1, 2, etc. Because the center of the package may not be the hottest spot on the package top, the location that the temperature was taken is given in x,y (horizontal, v

25、ertical) dimensions with the pin 1 or A1 location in the lower left corner. See Figure 1 for a sketch of the orientation. TBA(S,E,N,W)(P1,P2,Pn) or DeltaT-BA(P1,P2,Pn): Board temperature rise relative to ambient for each board temperature on the South, East, North, and West sides of the package with

26、 the pin 1 or A1 location in the lower left corner. The board temperature is measured on the top surface of the board as specified in JESD51-8. See Figure 1 for a sketch of the orientation. TJiX(P1,P2,Pn) or DeltaT-JiX(P1,P2,Pn): Temperature rise for each source, i, relative to a reference temperatu

27、re at the power dissipation of P1, P2, etc for source 1, 2, etc. JEDEC Standard No. 51-31 Page 3 3 Terms and definitions (contd) TTX(x,y)(P1,P2,Pn) or DeltaT-TX(x,y) (P1,P2,Pn): Temperature rise of the top of the package relative to a reference temperature at the power dissipation of P1, P2, etc for

28、 source 1, 2, etc. Because the center of the package may not be the hottest spot on the package top, the location that the temperature was taken is given in x,y (horizontal, vertical) dimensions with the pin 1 or A1 location in the lower left corner. See Figure 1 for a sketch of the orientation. TBX

29、(S,E,N,W)(P1,P2,Pn) or DeltaT-BX(P1,P2,Pn): Board temperature rise relative to a reference temperature for each board temperature on the South, East, North, and West sides of the package with the pin 1 or A1 location in the lower left corner. The board temperature is measured on the top surface of t

30、he board as specified in JESD51-8. 4 Junction-to-Ambient thermal measurement This section applies to the junction-to-ambient thermal dissipation using the environment specified by JESD51-2 and JESD51-6 for natural convection (still air) and forced convection respectively. 4.1 Test boards The test bo

31、ards are specified in JESD51 series of specifications4,6,8,10-12with an additional document being prepared which describes the changes that may be required for some MCP packages because of the additional connections required to power up all the heat sources and measure the junction temperatures. 4.2

32、 Power used for testing 4.2.1 Test chips with individual power control Because natural convection thermal performance depends on the surface temperature of the package, JESD51-2 recommends power levels based on a 30 C to 60 C temperature rise at the heat source. If the package can be assembled with

33、thermal die and wired to permit individual control of each heat source, it is recommended to use the power levels recommended in JESD51-2. The ideal way to test the package is to power each heat source individually at the recommended power level and measure the temperature rise of all the sources. T

34、his technique provides the full matrix of temperature rises that can be used to calculate performance with any arbitrary power distribution using superposition techniques. The amount of power applied to each source must be in a reasonable range for the size and characteristics of the source. If the

35、power distribution for the heat sources is known, the temperature rise of each source can be measured with that power distribution. Knowing the use conditions of the device will help determine a reasonable set of measurements to cover the expected range of use. JEDEC Standard No. 51-31 Page 4 4.2 Po

36、wer used for testing (contd) 4.2.2 Testing without individual power control. Because it may be impossible to control the power at each heat source, the alternative approach is to measure the performance of the package using the available range of power for each heat source with a temperature rise la

37、rge enough that the resolution of the temperature measurement of the heated sources using the temperature sensitive parameter is at least 1% of the temperature rise or 0.2 C, whichever is the larger value. 4.3 Test results 4.3.1 Steady state determination Steady state is defined when all of the meas

38、urement points are changing slow enough that waiting an additional time will not improve the accuracy of the measurement. The recommended method is documented in Section 3.6 of JESD51-1 with the measured temperature rise substituted for the thermal resistance. It should be noted that this procedure

39、will cause an early termination of the measurement unless the algorithm is started after the system is close to a steady state condition or “appears to have reached steady state.” It also should be noted that all the measurement points must reach steady state, not just the powered heat sources. 4.3.

40、2 Junction or source temperature rise The junction temperature rise, TJiA(P1,P2,Pn) .for each heat source, i, at each power distribution tested is reported relative to the ambient temperature. 4.3.3 Board temperature The board temperature rise, TBA(S,E,N,W)(P1,P2,Pn), may be reported at each side of

41、 the package for each of the power conditions tested. Figure 1 shows the location of the S, E, N, or W side of the package. For an MCP that has both x and y symmetry relative to the package center, only one board temperature rise is needed. The board temperature is measured as described in JESD51-8

42、9. 4.3.4 Top of package temperature A thermocouple reading on the top of the package is extremely useful for determining the junction temperatures in an application as described in JESD51-12 13. For simplicity in reporting the measurements, the temperature rise at the top of the package relative to

43、ambient is reported, TTA(x,y)(P1,P2,Pn) The location of the top of package thermocouple should be chosen to give the most accurate means of estimating the maximum junction temperature of the MCP. Typically, the hottest accessible location on the surface is chosen. JEDEC Standard No. 51-31 Page 5 4.3

44、 Test results (contd) 4.3.4 Top of package temperature (contd) The locations of the top of package measurement must be given as the x,y (horizontal, vertical) distance from the A1 corner of the package when the A1 corner is located in the lower left corner and the package is viewed from the top of t

45、he package as shown in Figure 1. The accuracy by which the junction temperatures of the heat sources can be derived from the top of package thermocouple reading will depend on the structure inside the package and the range of power values for which data is provided. As an example, when there is a co

46、oler die above the hotter die and the cooler die is closer to the surface where the package thermocouple is placed, the thermocouple will reflect the temperature of the closer heat source better than the hotter source below. The issue can be minimized by the choice of power combinations used when re

47、porting the data. More than one package thermocouple may be used provided that the number of thermocouples does not lower the temperature rise of the heat sources more than 2%. Thermistors can be used in place of thermocouples. Measurements using an IR camera will yield more data, especially for pac

48、kages with many heat sources. Figure 1 Illustration of the x,y location of two thermocouples and the N, E, S, or W side of the package. x y A1 or pin1 Thermocouple 1 Top View of Package Thermocouple 2 S N E W JEDEC Standard No. 51-31 Page 6 4.4 Test method summary The test method using the same proc

49、edures and methods specified in JESD51-2 and JESD51-6 except that heat sources must be powered and the results obtained for a matrix of powers for the various sources that will either match the power distributions of the MCP in the application or provide the data to allow calculation of the appropriate power distribution using superposition techniques. The use of superposition techniques will be documented in JESDXX, “Guideline to Support Effective Use of MCP Thermal Measurements” which is being prepared. 4.5 Example results table There are m