JEDEC JESD51-11-2001 Test Boards for Through-Hole Area Array Leaded Package Thermal Measurements《通孔区域排列有引线的封装热测量的测试板》.pdf

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1、 2500 Wilson Boulevard Arlington, Virginia 22201-3834 (703) 907-7559 FAX (703) 907-7583 June 28, 2001 ANNOUNCEMENT AVAILABILITY OF JEDEC STANDARD The JEDEC Solid State Technology Association (JEDEC) announces the release of JEDEC Standard No. 51-11 (JESD51-11) “Test Boards for Through-Hole Area Arra

2、y Leaded Package Thermal Measurements”. This standard covers the design of printed circuit boards (PCBs) used in the thermal characterization of Pin Grid Array (PGA) packages. It is intended to be used in conjunction with the JESD51 series of standards that cover the test methods and test environmen

3、ts. JESD51-11 was developed to give a figure-of-merit of thermal performance that allows for accurate comparisons of packages from different suppliers. It can be used to give a first order approximation of system performance and, in conjunction with the other JESD51 PCB standards, allows for compari

4、sons of the various package families. JESD51-11 helps complete the series of standards that now covers virtually all of the major package families. JESD51-11 was developed by the JC-15.1 Subcommittee on Thermal Characterization under the chairmanship of Bruce Guenin of Amkor Technologies and the aut

5、horship of Mr. Paul Hundt of Texas Instruments. To obtain copies of JESD51-11 ($40.00 ea.), contact Global Engineering Documents, 15 Inverness Way East, Englewood, CO 80112-5704 or call U.S.A. and Canada 1-800-854-7179, International (303) 397-7956. To download this document for free, access the JED

6、EC web site at www.jedec.org. JEDECSTANDARDTest Boards for Through-Hole AreaArray Leaded Package ThermalMeasurementsJESD51-11JUNE 2001JEDEC SOLID STATE TECHNOLOGY ASSOCIATIONNOTICEJEDEC standards and publications contain material that has been prepared, reviewed, andapproved through the JEDEC Board

7、of Directors level and subsequently reviewed and approvedby the EIA General Counsel.JEDEC standards and publications are designed to serve the public interest through eliminatingmisunderstandings between manufacturers and purchasers, facilitating interchangeability andimprovement of products, and as

8、sisting the purchaser in selecting and obtaining with minimumdelay the proper product for use by those other than JEDEC members, whether the standard is tobe used either domestically or internationally.JEDEC standards and publications are adopted without regard to whether or not their adoptionmay in

9、volve patents or articles, materials, or processes. By such action JEDEC does not assumeany liability to any patent owner, nor does it assume any obligation whatever to parties adoptingthe JEDEC standards or publications.The information included in JEDEC standards and publications represents a sound

10、 approach toproduct specification and application, principally from the solid state device manufacturerviewpoint. Within the JEDEC organization there are procedures whereby an JEDEC standard orpublication may be further processed and ultimately become an ANSI/EIA standard.No claims to be in conforma

11、nce with this standard may be made unless all requirements stated inthe standard are met.Inquiries, comments, and suggestions relative to the content of this JEDEC standard orpublication should be addressed to JEDEC Solid State Technology Association, 2500 WilsonBoulevard, Arlington, VA 22201-3834,

12、(703)907-7560/7559 or www.jedec.orgPublished byJEDEC Solid State Technology Association 20012500 Wilson BoulevardArlington, VA 22201-3834This document may be downloaded free of charge, however EIA retains thecopyright on this material. By downloading this file the individual agrees not tocharge for

13、or resell the resulting material.PRICE: Please refer to the currentCatalog of JEDEC Engineering Standards and Publications or call Global EngineeringDocuments, USA and Canada (1-800-854-7179), International (303-397-7956)Printed in the U.S.A.All rights reservedPLEASE!DONT VIOLATETHELAW!This document

14、 is copyrighted by the Electronic Industries Alliance and may not bereproduced without permission.Organizations may obtain permission to reproduce a limited number of copiesthrough entering into a license agreement. For information, contact:JEDEC Solid State Technology Association2500 Wilson Bouleva

15、rdArlington, Virginia 22201-3834or call (703) 907-7559JEDEC Standard No. 51-11-i-TEST BOARDS FOR THROUGH-HOLE AREA ARRAY LEADEDPACKAGE THERMAL MEASUREMENTSCONTENTSPageForeword ii1 Scope 12 Normative references 13 Stock material 24 Board outline 35 Trace design 35.1 Top trace layer layout (both 1s an

16、d 2s2p PCBs) 35.2 Trace widths for 1s and 2s2p PCBs 45.3 Plated through-hole vias 55.4 Trace layers and connection routing 55.5 Buried layer layout (2s2p PCB only) 65.6 PCB metalization characteristics for 1s and 2s2p PCBs 75.7 Solder masks for 1s and 2s2p PCBs 76 Hand wiring 77 Data presentation 8T

17、ables1 PCB sizes for packages 32 PCB buried plane sizes 63 Wire size current limits 74 Specified parameters and values used 8Figures1a Cross section of 1s PCB showing trace and dielectric thicknesses in package placement 2and trace fan-out regions1b Cross section of 2s2p PCB showing trace and dielec

18、tric thicknesses 22 BGA test board outer dimensions and edge connector design 33 Traces to outer ball row flared to perimeter 25 mm from package body 34 Flared PCB layout scheme 45 Nesting of 256 and 352 PBGA packages 66 Routing outside fan-out layer allowed in low conductivity PCB 67 Hand wiring te

19、st board suggestion 8JEDEC Standard No. 51-11-ii-ForewordThe measurement of the junction-to-ambient (RJA) thermal characteristics of an integrated circuit (IC)has historically been carried out using a number of test fixturing methods. The most prominent method isthe soldering of the packaged devices

20、 to a printed circuit board (PCB). The characteristics of the testPCBs can have a dramatic (60%) impact on the measured RJA. Due to this wide variability, it isdesirable to have an industry-wide standard for the design of PCB test boards to minimize discrepanciesin measured values between companies.

21、To obtain consistent measurements of RJAfrom one company to the next, the test PCB geometry andtrace layout must be completely specified for each package geometry tested. Such a completespecification would limit the flexibility of user companies who would like to design test boards for theirindividu

22、al needs. Thus, one characteristic of a test board specification is to allow some variability ofPCB test board design while minimizing measurement variability.This specification is intended for use with the thermal measurements and modeling specificationsgrouped under JEDEC EIA/JESD 51, 1. Specifica

23、lly, the electrical test procedures described in JEDECEIA/JESD 51-1, “Integrated Circuit Thermal Measurement Method - Electrical Test Method (SingleSemiconductor Device),” 2, and 51-2, “Integrated Circuit Thermal Test Method EnvironmentalConditions - Natural Convection (Still Air), 3, and 51-6, “Int

24、egrated Circuit Thermal Test MethodEnvironmental Conditions - Forced Convection (Moving Air), 4.JEDEC Standard No. 51-11Page 1TEST BOARDS FOR THROUGH-HOLE AREA ARRAY LEADEDPACKAGE THERMAL MEASUREMENTS(From JEDEC Board Ballot JCB-00-59, formulated under the cognizance of the JC-15.1 Subcommitteeon Th

25、ermal Characterization.)1ScopeThis specification covers through-hole area array leaded packages intended to be mounted on a PCB. Itdoes not cover area array packages that require sockets.2 Normative references1 JESD 51, Methodology for the Thermal Measurement of Component Packages (SingleSemiconduct

26、or Device).2 JESD 51-1, Integrated Circuit Thermal Measurement Method - Electrical Test Method (SingleSemiconductor Device).3 JESD 51-2, Integrated Circuit Thermal Test Method Environmental Conditions - NaturalConvection (Still Air).4 JESD 51-6, Integrated Circuit Thermal Test Method Environmental C

27、onditions - ForcedConvection (Moving Air).5 Electronics Engineers Handbook, 3rd Edition, Edited by D.G. Fink and D. Christiansen,McGraw-Hill Book Co., NY, 1989, p 6.166 MIL-W-5088L, Amdt. 1, Wiring, Aerospace Vehicle7 IPC-2222, Sectional Design Standard for Rigid Organic Printed Boards8 IPC-2221, Ge

28、neric Standard on Printed Board DesignJEDEC Standard No. 51-11Page 23 Stock materialThe PCB test board shall be made of FR-4 material. The finish size shall be 1.60 mm +/- 10% thick. Forhigh ambient or board temperature applications ( 125 C), use of other test board material is acceptableas long as

29、the thermal conductivity of the material is reported and measurement correlations have beenestablished between the substitute material and FR-4.Trace thickness is achieved by starting with standard copper stock and then plating to final thickness. Aconvention in PCB fabrication is to refer to copper

30、 thickness using the terminology ounces of copper persquare foot of board. An ounce of copper per square foot translates to a copper thickness of 35 m.The 1s test board has only a top trace layer in the component mounting and trace fan-out region (seefigure 1a). The copper trace thickness shall be 7

31、0 m (2 oz) +/- 20%. A bottom trace layer may be usedfor solder lands at the end of the fan-out traces and edge connection points. Connection to the edgeconnector outside the package fan-out region can be made with either the top or bottom signal traces.The 2s2p version of this test board is formed b

32、y embedding two 35 m (1 oz) +0/-20% copper planes inthe PCB (as shown in figure 1b), while maintaining the finished thickness at 1.60 mm.Figure 1a Cross section of 1s PCB showing trace and dielectric thicknesses in packageplacement and trace fan-out regionsFigure 1b Cross section of 2s2p PCB showing

33、 trace and dielectric thicknesses1.60 mmComponent Trace, 2 oz *Plane 1, 1 oz, solidPlane 2, 1 oz, solidBackside Trace, 2 oz *AA0.25 mm A 0.5 mm* = finished thickness:1 oz/ft2= 35 m2 oz/ft2= 70 m1.60 mmComponent Trace, 2 oz * = finished thickness:2 oz/ft2= 70 mJEDEC Standard No. 51-11Page 34 Board ou

34、tlineThe board shall be 101.5 mm x 114.5 mm +/- 0.25 mm in size for packages less than or equal to 40 mmon a side (see figure 2). A typical edge connector is depicted in figure 2. The edge connector can be pin-out and pitch modified for specific needs. Modification of the width dimension of the edge

35、 connector isallowed. Multiple rows of vias along the edge connector are allowed.For various package sizes, refer to table 1 for the appropriate PCB size.Table 1 PCB sizes for packagesPackage Length PCB Size (+/- 0.25 mm)Pkg. Length 40 mm 101.5 mm x 114.5 mm (4.0 in x 4.5 in)40 mm Pkg. Length 65 mm

36、127.0 mm x 139.5 mm (5.0 in x 5.5 in)65 mm Pkg. Length 90 mm 152.5 mm x 165.0 mm (6.0 in x 6.5 in)Figure 3 Traces to outer pin row flaredto perimeter 25 mm from package body.Figure 2 Example test board outerdimensions and edge connector designJEDEC Standard No. 51-11Page 45 Trace design5.1 Top trace

37、 layer layout (both 1s and 2s2p PCBs)Traces should be laid out such that the test device will be centered relative to a 101.5 mm x 101.5 mmsection towards the top of the board (away from the edge connector) for the smallest board. For largerboard sizes, locate the package at the top of the board in

38、the center of a square whose length is the widthdimension of the board. The traces connecting to the package must extend at least 25 mm out from theedge of the device body. Trace lengths longer than this amount are allowed. Traces must be routed in aradial fashion (flared) to meet the edges of a rec

39、tangle such that the terminal via locations are equallyspaced over 90% of the perimeter of the sides of this rectangle. Traces must be flared out to the 25 mmperimeter adjacent to the side of the package they are on. Corner-most lands flare to the perimeterclockwise of the corner (see figure 3). Sta

40、ggering of trace terminal soldering positions inward from thetrace termination rectangle is allowed to 2.5 mm off the perimeter of the square.Traces must short all pin rows on a given side of a package together as shown in figure 4. If the packageinterposer is designed so that two connections needed

41、 for the thermal test would be shorted when the pinrows are shorted together, the trace may be cut to eliminate the short (see figure 4a). No more than 10%of the total number of traces should be cut. Routing two traces per pin position is allowed (as shown infigure 4d) as long as the total trace wid

42、th per pin position in the fan-out region is as specified in 5.2. Therouting of figure 4d may require the use of traces that are narrower than specified in 5.2 in the pin arrayarea. This is allowed as long as the trace portion outside of the package body is in agreement with thewidth specified by 5.

43、2. A trace design that nests packages with equal pin pitches on the same PCB isallowed as long as the above conditions are met (see figure 5).Figure 4 Examples of trace routingJEDEC Standard No. 51-11Page 55 Trace design (contd)5.2 Trace widths for 1s and 2s2p PCBsFinished trace widths shall be from

44、 36% to 44% of the nominal pin pitch. For multiple trace per pinposition designs (e.g., figure 4d), the combined total trace width shall not be greater than 40% of the pinpitch and each trace shall be of equal width. Splitting of traces in two parts, e.g. in order to keep force(power) and sense (mea

45、sure) lines independent, is allows as long as their summed widths meets theabove specified total trace width. For staggered arrays, the trace width may be based on the staggeredpitch (see figure 4e) or on the inline pitch (see figure 4f). Achieving the finish size may require someoversize in design

46、to compensate for overetching of the copper traces during processing. Traces shouldterminate in plated through-holes for soldering interconnect purposes. See 5.3 for a description of theplated through-hole vias.5.3 Plated through-hole viasVias for package mounting: The finished (plated) diameter for

47、 all plated through-holes used for packagemounting shall be no less than the maximum pin diameter plus 0.15 mm and no more than the minimumpin diameter plus 0.60 mm 7. For rectangular pins, the diameter shall be calculated as equal to thediagonal of the rectangular cross-section of the lead. The via

48、 pad diameter is specified in reference 8.The nominal via pad diameter tolerance shall be +0.10/-0 mm.For example, for a PGA (e.g., JEDEC MO-066) with the following dimensions:Min. lead diameter: 0.25 mmMax. lead diameter: 0.50 mmThe plated through-hole vias are as follows:Min. finished hole diamete

49、r: 0.50 + 0.15 = 0.65 mm 7Max. finished hole diameter: 0.25 + 0.60 = 0.85 mm 7Via pad diameter: 0.85 + 0.20 + 0.10 = 1.15 +0.10/-0 mm 8The drill hole diameter shall be such as to yield the finished hole diameters specified above. An isolationclearance region with a diameter at least 0.2 mm larger than the drill hole diameter shall exist in theburied solid planes around each plated through-hole via. Other than this isolation clearance area, theburied planes are to be unbroken. Some buried plane copper must exist between