JEDEC JESD36-1996 Standard for Description of Low-Voltage TTL-Compatible 5 V-Tolerant CMOS Logic Devices《低压TTL兼容 5V容限CMOS逻辑器件描述规范》.pdf

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1、EIA JESD3b 96 W 3234600 0575640 TL4 m EINJEDEC STANDARD Standard for Description of Low-Voltage TTL-Compatible, 5 V-Tolerant CMOS Logic Devices EIA/JESD36 JUNE 1996 ELECTRONIC INDUSTRIES ASSOCIATION ENGINEERING DEPARTMENT NOTICE EWJEDEC Standards and Publications contain material that has been prepa

2、red, progressively reviewed, and approved through the JEDEC Council level and subsequently reviewed and approved by the EIA General Counsel. EINJEDEC Sgdards and Pubiications are designed to serve the public interest through eliminating misunderstanings between manufacturers and purchases, facilitat

3、ing interchangeabiliy and improvement of products, and assisting the purchaser is selecting and obtaining with minimum delay the proper product for his particular need. Existence of such standards shall not in any respect preclude any member or nonmember of JEDEC from manufacturing or selling produc

4、ts not donning to such standards, nor shall the existence of such standards preclude their voluntary use by those other than EIA members, whether the standard is to be used either domestically or internationally. EWJEDEC Standards and Publications are adopted without regard to whether their adoption

5、 may involve patents or articles, materials, or processes. By such action, EWJEDEC does not assume any liability to any patent owner, nor does it assume any obligation whatever to parties adopting the EWJEDEC Standards or Publications. The information included in EWJEDEC Standards and Pubiications r

6、epresents a sound approach to product specification and application, principally fiom the solid state device manufacturer viewpoint. Within the EINJEDEC organization there are procedures whereby an EWJEDEC Standard or Publication may be further processed and ultimately becomes an ANSEIA Standard. In

7、quiries, comments, and suggestions relative to the content of this EWJEDEC Standard or Publication should be addressed to the JEDEC Executive Secretary at EIA Headquarters, 2500 Wilson Boulevard, Arlington, VA 2220 1. Published by OELECTRONIC INDUSTR.IES ASSOCIATION 1996 Engineering Department 2500

8、Wilson Boulevard Arlington, VA 2220 1 “Copyright“ does not apply to JEDEC member companies as they are free to duplicate this document in accordance with the latest revision of the JEDEC Publication 2 1 “Manual of Organization and Procedure“. PRICE: Please refer to the current Catalog of EIA, JEDEC,

9、 and TIA STANDARDS and ENGINEERING PUBLICATIONS or call Global Engineering Documents, USA and Canada (1-800-854-7179) International (303-397-7956) Printed in U.S.A. All rights reserved EINJEDEC Standard No. 36 Standard for Description of Low-Voltage TTL-Compatible, 5 V-Tolerant CMOS Logic Devices CO

10、NTENTS Section 1 2 3 4 5 INTERFACE STANDARD 1.1 Purpose 1.2 Scope DEFINITIONS STANDARD SPECIFICATIONS 3.1 Absolute Maximum Continuous Ratings 3.2 Recommended Operating Conditions 3.3 dc Specifications TEST CIRCUITS AND SWITCHING WAVEFORMS REFERENCE TO OTHER APPLICABLE JEDEC STANDARDS AND PUBLICATION

11、S Page 1 4 8 - - - EIA JESD3b b 3234600 0575b44 bbT EINJEDEC Standard No. 36 -ii- EIA JESD3h h = 3234600 0575645 5Th EINJEDEC Standard No. 36 Page 1 Standard for Description of Low-Voltage TTLCompatible, 5 V-Tolerant CMOS Logic Devices (From JEDEC Council Ballot JCB-95-72, formulated under the cogni

12、zance of JC-40 Committee on Digital Logic.) 1 INTERFACE STANDARD 1.1 1.2 Purpose: To provide a standard for Low-Voltage 5 V -tolerant CMOS Logic series specifications for uniformity, multiplicity of sources, elimination of confusion, and ease of device specification and design by users. Scope: This

13、standard defines dc interface and switching parameters for a high-speed, low-voltage 5 V-tolerant CMOS digital logic family. This standard covers specifications for CMOS Logic series as defined in Section 2. 2 DEFINITIONS CMOS Series Includes devices that utilize CMOS technology. 5 V-tolerant define

14、d within this specification means that leakage current is negligible when inputs, or outputs in the high-impedance state are exposed to voltages exceeding VDD, guaranteed to 5.5 V. Includes devices whose input logic levels are TTL-compatible. Compliant with JEDEC standard 8-A. Prefix Prefix “74“ imm

15、ediately preceding family name indicate the operating temperature range. 74XXX refers to the Commercial (COML) version of devices which are specified over -40 OC to 85 OC. EIA JESD3b b m 3234600 0575646 432 m Symbol Parameter MIN VDD Supply voltage 2.7 VIN Input voltage O EINJEDEC Standard No. 36 Pa

16、ge 2 MAX Unit 3.6 V 5.5 V 3 STANDARD SPECIFICATIONS VOUT VOUT TA AVAv 3.1 Absolute Maximum Continuous Ratings (Notes 1 and 2): Supply Voltage, VDD . -0.5 V to 4.6 V dc input voltage, VIN (except I/O pins) -0.5 V to 6.0 V dc output voltage, VOUT (including I/O pins) output in high or low state 4.5 V

17、to VDD + 0.5 V dc output voltage, VOUT (including I/O pins) output in %state . -0.5 V to + 6.0 V dc input clamp current, IIK (Vi VDD) k50 mA dc current into any output in the low state, IOL 50 mA dc current into any output in the high state, IOH -50 mA dc supply current per supply pin fi O0 mA dc gr

18、ound current per ground pin f100 mA Storage temperature range -65 OC to 150 OC Output voltage outputs active O VDD V Output voltage outputs disabled O 5.5 V Operating free-air temperature -40 85 oc Input transition rise or fall rate (Note 1) O 10 nsN Note 1: Absolute maximum continuous ratings are t

19、hose values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute-maximum-rated conditions is not implied. Under transient conditions these ratings may be exceeded as

20、 defined elsewhere in this specification. Note 2: 3.2 Recommended Operating Conditions: EIA JESD36 96 = 3234600 0575647 379 EINJEDEC Standard No. 36 Page 3 3.3 dc Specifications: High-level output voltage Low-level output voltage Static supply current (Note 2) pA VDD = MAX, 3.6 V S (VI or Vo) I 5.5

21、V VI = VDD - 0.6 V, other inputs at VDD or GND, VDD = 2.7 V to 3.6 V (Note 3) 500 CiA Static supply current per input at a specified level *IDD Note 1 - For Il0 pins, loz includes the input leakage current. Note 2 - Refer to manufacturers data sheet. Note 3 - For bus-hold type pins refer to manufact

22、urers data sheet. EINJEDEC Standard NO. 36 Page 4 Generator I 4 TEST CIRCUITS AND SWITCHING WAVEFORMS = CL VDD Test tPLH tPHL tPZH Switch Open Open GND tPZL I 6V I tPHZ GND GND I I tPl2 6V CL = 50 pF or equivalent (includes jig and probe capacitance). RL = R1 = 500 Ror equivalent. RT = %UT of pulse

23、generator (typically 50 a). EIA JESD36 96 3234600 0575649 L4L 1 EINEDEC Standard No. 36 Page 5 PROPAGATION DELAY MEASUREMENTS PULSE DURATION (WIDTH) MEASUREMENTS I I I - 2.7 V Output requirements: Device must follow truth table VOL I VOL max VOH 2 VOH min tr = tf = 2.5 ns (or as fast as required) fr

24、om 10% to 90% of O V to 2.7 V. input Conditions: EIA JESD36 96 3234600 0575650 963 D EINJEDEC Standard No. 36 Page 6 SETUP AND HOLD TIME MEASUREMENTS ENABLE TIME MEASUREMENTS EIA JESD3b 96 3234b00 0575651 8TT = EINJEDEC Standard No. 36 Page 7 DISABLE TIME MEASUREMENTS Enable Input output LOW to High-Z I I 4 EINJEDEC Standard No. 36 Page 8 5 REFERENCE TO OTHER APPLICABLE JEDEC STANDARDS AND PUBLICATIONS JEDEC Standard No. &A Interface Standard for Nominal 3 VB.3 V Supply Digital Integrated Circuits EIA JESD3b i6 m 3234600 0575b53 b72 m