JEDEC JESD30G-2016 Descriptive Designation System for Semiconductor-device Packages.pdf

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1、JEDEC STANDARD Descriptive Designation System for Semiconductor-device Packages JESD30G (Proposed Revision of JESD30F, April 2013) JANUARY 2016 JEDEC SOLID STATE TECHNOLOGY ASSOCIATION NOTICE JEDEC standards and publications contain material that has been prepared, reviewed, and approved through the

2、 JEDEC Board of Directors level and subsequently reviewed and approved by the JEDEC legal counsel. JEDEC standards and publications are designed to serve the public interest through eliminating misunderstandings between manufacturers and purchasers, facilitating interchangeability and improvement of

3、 products, and assisting the purchaser in selecting and obtaining with minimum delay the proper product for use by those other than JEDEC members, whether the standard is to be used either domestically or internationally. JEDEC standards and publications are adopted without regard to whether or not

4、their adoption may involve patents or articles, materials, or processes. By such action JEDEC does not assume any liability to any patent owner, nor does it assume any obligation whatever to parties adopting the JEDEC standards or publications. The information included in JEDEC standards and publica

5、tions represents a sound approach to product specification and application, principally from the solid state device manufacturer viewpoint. Within the JEDEC organization there are procedures whereby a JEDEC standard or publication may be further processed and ultimately become an ANSI standard. No c

6、laims to be in conformance with this standard may be made unless all requirements stated in the standard are met. Inquiries, comments, and suggestions relative to the content of this JEDEC standard or publication should be addressed to JEDEC at the address below, or refer to www.jedec.org under Stan

7、dards and Documents for alternative contact information. Published by JEDEC Solid State Technology Association 2016 3103 North 10th Street Suite 240 South Arlington, VA 22201-2107 This document may be downloaded free of charge; however JEDEC retains the copyright on this material. By downloading thi

8、s file the individual agrees not to charge for or resell the resulting material. PRICE: Contact JEDEC Printed in the U.S.A. All rights reserved PLEASE! DONT VIOLATE THE LAW! This document is copyrighted by JEDEC and may not be reproduced without permission. For information, contact: JEDEC Solid Stat

9、e Technology Association 3103 North 10th Street Suite 240 South Arlington, VA 22201-2107 or refer to www.jedec.org under Standards-Documents/Copyright Information. JEDEC Standard No. 30G -i- DESCRIPTIVE DESIGNATION SYSTEM FOR SEMICONDUCTOR-DEVICE PACKAGES Contents Foreword ii 1 Scope 1 2 Terms and d

10、efinitions 1 3 Descriptive designation system for semiconductor-device packages 5 3.1 General . 5 3.2 Field descriptions 6 3.2.1 Package-outline-style codes . 6 3.2.2 Terminal-position prefix . 7 3.2.2 Terminal-position prefix (contd) 8 3.2 Field descriptions (contd) . 9 3.2.3 Package-body material

11、. 9 3.2.4 Lead-form (including terminal-shape) suffix 10 3.2.5 Terminal-count suffixes . 12 3.2.6 Package pitch 12 3.2.7 Supplemental-information field 12 4 Other part detail . 13 4.1 Part access direction . 13 4.2 Mounting preparation 14 4.3 Body Direction . 15 4.4 Part Entry UOM . 16 5 New descrip

12、tive codes 16 Annex A (normative) Derivation of basic package terminal positions 17 Annex B (informative) Package classification . 36 Annex C (informative) Differences between JESD30G and its predecessors 37 Figures Figure 1 Descriptive designation system for semiconductor-device packages 5 Figure 2

13、 Package View Representation . 13 Figure 3 Packages that are Straight Mounted as received from Supplier 14 Figure 4 Prepped Packages prior to Assembly 14 Figure 5 Horizontal Body Direction . 15 Figure 6 Vertical Body Direction . 15 Figure A.1 Example of Span-X and Span-Y . 26 Figure A.2 Illustration

14、s of lead form (or terminal shape) . 33 Figure A.3 Illustrations of some basic packages and their designators . 34 Tables Table 1 Package Outline Style Codes 6 Table 2 Prefixes for lead (terminal) position . 8 Table 3 Prefixes for predominant package-body material 9 Table 4 Codes for package-specifi

15、c features . 9 Table 5 Suffixes for lead form (or terminal shape) 11 Table 6 Pitch Code versus Pitch value . 12 Table A.1 Terminal position with additional definition . 17 Table A.2 Suffixes for lead form (or terminal shape) with additional definition . 24 Table A.3 Illustrations of lead form (or te

16、rminal shape) 26 JEDEC Standard No. 30G -ii- Foreword This standard establishes requirements for the generation of semiconductor-device package designators for the JEDEC Solid State Technology Association. The requirements herein are intended to ensure that such designators are presented in as unifo

17、rm a manner as practicable Example of how this standard can be used, is in defining the part in sufficient detail to enable process efficiencies during the part and product life cycles, i.e., design, purchasing, manufacturing, quality control, test, etc This release includes additional definition an

18、d clarification of the device to provide this support to the industry. The standard is designed to be scalable insofar that it should cover as many components as possible that are available in the market. It should also be scalable to encompass the emergence of new packages in the future. It is not

19、intended to provide standardization for a limited number of parts, or the perceived common parts in the market, since this is impracticable to measure. Although this standard is considered to have international standardization implications, a complete comparison between the JEDEC standard and the in

20、ternational documents has not been made. This revision of the standard incorporates many new table entries and text emendations compared to JESD30F. The material contained in this standard was formulated by the JEDEC JC-11 Committee on Mechanical (Package Outlines) Standardization and approved by th

21、e JEDEC Board of Directors. In the next release, this standard will incorporate a standard XML structure to support Component Manufacturers in providing part data to their customers, utilizing these definitions herein. This document will be made available under JEP95, as a Standard Process Procedure

22、, SPP-XXX, to be developed. JEDEC Standard No. 30G Page 1 DESCRIPTIVE DESIGNATION SYSTEM FOR SEMICONDUCTOR-DEVICE PACKAGES From JEDEC Board Ballots JCB-06-24, JCB-08-32, JCB-13-29 and JCB-15-59, formulated under the cognizance of the JC-11 Committee on Mechanical (Package outline) Standardization.)

23、1 Scope This standard describes a systematic method for generating descriptive designators for semiconductor-device packages. The descriptive designator is intended to provide a useful communication tool, but has no implied control for assuring package interchangeability. 2 Terms and definitions For

24、 the purpose of this standard, the following definitions shall apply: array type: A rectangular or square shaped body with or without chamfered corners with perpendicular sides. The sides do not taper outwards or inwards as in a Small Outline or a Flatpack Package Outline. body direction: this attri

25、bute is different to the “mounting direction” since it defines whether the part body is either vertical or horizontal, by comparing the cross-sectional area of the part in both the horizontal direction and the vertical direction. If the horizontal cross sectional area is greater than the vertical cr

26、oss sectional area, then the body direction is horizontal. can package: Generally, a cylindrical package whose terminals exit from one end parallel to the axis of the package. chip-scale package: A package whose area is generally no greater than 120% of the area of the semiconductor device it contai

27、ns. NOTE The package size does not necessarily change with decreases in the die size. clamped package: A package for high-current devices, in the form of a cylinder with a flat, circular high-current terminal on each end, that is intended to be clamped between two bus bars acting as heat sinks. conn

28、ector: A package that connects between the PCB and another component/PCB/interconnect structure, transferring electrical signals or current. die-size package: A chip-scale package whose area is generally equal to the area of the semiconductor device it contains. NOTE 1 Usually, but not necessarily,

29、some portion of the silicon IC is exposed. The device is then also an uncased device. NOTE 2 The package size will change with changes in the size of the die. discrete: A discrete device (or discrete component) is an electronic component with just one circuit element, either passive (resistor, capac

30、itor, inductor) or active (transistor or vacuum tube), other than an integrated circuit. JEDEC Standard No. 30G Page 2 2 Terms and definitions (contd) disk-button package: A package shaped like a disk or button whose terminals exit radially from the periphery of the package (like the spokes of a whe

31、el) or axially from the center of the disk. flange-mount package: A package having a flange mounted heat sink that is an integral part of the package and that extends beyond the package body to provide mechanical mounting to a packaging interconnect structure or cold plate. NOTE The terminals may ex

32、it from, or be attached to, any surface of the package. flatpack package: A package whose leads project parallel to, and are designed primarily to be attached parallel to, the seating plane. A surface-mount package whose terminals are on three or four sides and consist of metal pad surfaces (on lead

33、less versions) or leads emerging from the package. NOTE 1 The package leads may be formed to facilitate surface mounting. NOTE 2 The small-outline package is similar except for having terminals on only one or two opposite sides of the package. footprint (of a package): The pattern of package leads t

34、hat is used to define the land patterns on a mating printed circuit board. NOTE The footprint may include features necessary for mechanical mounting of the package. grid-array package: A package whose terminals are located on one surface in a matrix of at least three rows and three columns. NOTE Ter

35、minals may be missing from some row-column intersections. hardware: A component package used solely for performing auxiliary activities such as heat or light conduction, support, elevation, anchoring, etc. The component has no electrical activity, except for grounding as in a shield, or to support a

36、 component in which electrical current must pass through the hardware support. in-line module: A microelectronic assembly whose terminals consist of metal pad surfaces located on one or both sides of a circuit board designed for insertion into a connector. in-line package: A package having a single

37、row or parallel rows of leads designed primarily for insertion (through-hole) mounting perpendicular to the seating plane. NOTE The leads may emerge from a single side or from two parallel sides with the leads formed to produce parallel rows. lead: A lead is the portion on the part that makes contac

38、t with the PCB. The term includes Terminals and Pin, but it also includes extrusions from the part body for which holes are required in the PCB, in order for the Part to be assembled to the PCB. The term lead is often used when discussing the physical details of the part JEDEC Standard No. 30G Page

39、3 2 Terms and definitions (contd) lead group: A part can have multiple leads of different shapes, forms, position, and size. The term group is used to define a grouping of leads that have a uniform layout and which have a common set of lead types and lead dimensions. As an example a layout of multip

40、le leads would be a set of 16 leads organized into 2 columns of 8 where the spacing in the vertical direction is the same for all leads and the spacing in the horizontal direction is the same for all leads. lead group lead form: A single-letter suffix that identifies the standard form or shape of th

41、e lead belonging to a specific group of leads on a package. When there is a single lead group on a package, then the package lead form is the same as the lead group lead form. lead group lead position: A single-letter prefix that identifies the physical terminal positions specific to a group of lead

42、s on a package. When there is a single lead group on a package, then the package lead position is the same as the lead group lead position. lead mount: The method or technology employed in mounting the lead to the pcb land pattern. There are 5 types available SMT, Through-hole, Non-board, Hole, or P

43、ress-fit long-form package: A cylindrical or elliptical tubular package having terminal endcaps or axial leads. microelectronic assembly: An assembly of unpackaged (uncased) microcircuits and/or packaged microcircuits so constructed on a packaging interconnect structure that it is considered to be a

44、n indivisible component for the purpose of specification, testing, commerce, and maintenance. NOTE The assembly may also include discrete devices. These and the microelectronic devices may be mounted on either one or two sides of the packaging interconnect structure, and the external terminals typic

45、ally exit from one side of the assembly. Various package sizes, shapes, and external terminal forms may be used. Mounting preparation: The majority of parts are mounted onto the pcb, without the need to preform (prep) the part. This is defined as “straight” mounting, since the part is placed on the

46、pcb in the way intended by the component manufacturer. When the part is pre-formed before assembly, and the body direction is changed to enable an alternative assembly mounting, then this is called “Prepped” part access direction: Various parts require additional clearance around the part, typically

47、 in one direction post assembly on the PCB. This may be a once off access to the part as the PCB is mounted into its enclosure, or it may require continuous access over the life of the product. Part access can come in any of the following directions Topside, Underside, Front, Back, Right side, Left

48、side package lead form: Package lead form is a one character code that indicates the lead form of the leads on the package (see 3.2.4 for how this is calculated) package lead position: Package lead position is a one character code that indicates the position of the leads on the package (see 3.2.2 fo

49、r how this is calculated) JEDEC Standard No. 30G Page 4 2 Terms and definitions (contd) pin: A pin is one type of Terminal that can be soldered or press-fit into the pcb structure, when used in the context of a physical description of the part. In the case of an electrical context as in schematic, electrical design, or simulation, the pin represents all terminals. post-mount package: A package, intended for mounting to an interconnect structure or cold plate, that incorporates a threaded stud, threaded hole, or post for that purpose. NOTE A variety of package sizes,