JEDEC JESD22B113A-2012 Board Level Cyclic Bend Test Method for Interconnect Reliability Characterization of SMT ICs for Handheld Electronic Products.pdf

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1、JEDEC STANDARD Board Level Cyclic Bend Test Method for Interconnect Reliability Characterization of SMT ICs for Handheld Electronic Products JESD22B113A (revision of JESD22-B113, March 2006) SEPTEMBER 2012 JEDEC SOLID STATE TECHNOLOGY ASSOCIATION NOTICE JEDEC standards and publications contain mater

2、ial that has been prepared, reviewed, and approved through the JEDEC Board of Directors level and subsequently reviewed and approved by the JEDEC legal counsel. JEDEC standards and publications are designed to serve the public interest through eliminating misunderstandings between manufacturers and

3、purchasers, facilitating interchangeability and improvement of products, and assisting the purchaser in selecting and obtaining with minimum delay the proper product for use by those other than JEDEC members, whether the standard is to be used either domestically or internationally. JEDEC standards

4、and publications are adopted without regard to whether or not their adoption may involve patents or articles, materials, or processes. By such action JEDEC does not assume any liability to any patent owner, nor does it assume any obligation whatever to parties adopting the JEDEC standards or publica

5、tions. The information included in JEDEC standards and publications represents a sound approach to product specification and application, principally from the solid state device manufacturer viewpoint. Within the JEDEC organization there are procedures whereby a JEDEC standard or publication may be

6、further processed and ultimately become an ANSI standard. No claims to be in conformance with this standard may be made unless all requirements stated in the standard are met. Inquiries, comments, and suggestions relative to the content of this JEDEC standard or publication should be addressed to JE

7、DEC at the address below, or refer to www.jedec.org under Standards and Documents for alternative contact information. Published by JEDEC Solid State Technology Association 2012 3103 North 10th Street Suite 240 South Arlington, VA 22201-2107 This document may be downloaded free of charge; however JE

8、DEC retains the copyright on this material. By downloading this file the individual agrees not to charge for or resell the resulting material. PRICE: Contact JEDEC Printed in the U.S.A. All rights reserved PLEASE! DONT VIOLATE THE LAW! This document is copyrighted by JEDEC and may not be reproduced

9、without permission. For information, contact: JEDEC Solid State Technology Association 3103 North 10th Street Suite 240 South Arlington, VA 22201-2107 or refer to www.jedec.org under Standards-Documents/Copyright Information. JEDEC Standard No. 22B113A -i- Test Method B113A (Revision of B113) BOARD

10、LEVEL CYCLIC BEND TEST METHOD FOR INTERCONNECT RELIABILITY CHARACTERIZATION OF SMT ICS FOR HANDHELD ELECTRONIC PRODUCTS Background Printed circuit board assemblies experience various mechanical loading conditions during assembly and use. The repeated flexing (cyclic bending) of board during various

11、assembly and test operations and in actual use can cause electrical failures due to circuit board and trace cracks, solder interconnects cracks, and the SMT IC cracks. Although the number of repeated bend cycles are small during assembly (e.g., handling between various assembly operations, In-circui

12、t Testing, final assembly in product casing), the magnitude of flexure can be very significant. On the other hand, the actual use conditions such as repeated key-presses in mobile phone can result in a large number of repeated bend cycles during the life of the product, albeit at a lower magnitude.

13、Since SMT IC manufacturers and suppliers cannot evaluate their package performance on actual final products, a board level test method is needed to evaluate the performance of SMT ICs due to repeated bending of board and compare their performance with other SMT ICs. JEDEC Standard No. 22B113A Test M

14、ethod B113A -ii- (Revision of B113) JEDEC Standard No. 22B113A Page 1 Test Method B113A (Revision of B113) BOARD LEVEL CYCLIC BEND TEST METHOD FOR INTERCONNECT RELIABILITY CHARACTERIZATION OF SMT ICS FOR HANDHELD ELECTRONIC PRODUCTS (From JEDEC board Ballot, JCB-12-37, formulated under the cognizanc

15、e of the JC-14.1 Subcommittee on Reliability Test Methods for Packaged Devices.) 1 Scope The Board Level Cyclic Bend Test Method is intended to evaluate and compare the performance of SMT ICs in an accelerated test environment for handheld electronic products applications. The purpose is to standard

16、ize the test methodology to provide a reproducible performance assessment of SMT ICs while duplicating the failure modes normally observed during product level test. This is not a SMT IC qualification test and is not meant to replace any product level test that may be needed to qualify a specific pr

17、oduct and assembly. Correlation between test and field conditions is not yet fully established. Consequently, the test procedure is presently more appropriate for relative SMT IC performance than for use as a pass/fail criterion. However, to do comparisons care must be taken to have the same test va

18、riables used, such as SMT IC configuration and size. This publication assumes a surface mount device such as BGAs, LGAs (excluding sockets and connectors), TSOP, and CSPs. Discrete SMT devices, e.g., capacitors, resistors, etc., are outside the scope of this test method. Furthermore, this test metho

19、d is only applicable for handheld products applications where cyclic bending due to repeated key-press operations is a concern. The size of surface mount device is limited to 15 mm x 15 mm maximum. 2 Apparatus - Any cyclic bend test apparatus that can cause a repeated bending of printed wiring board

20、s at 1 to 3 Hz cyclic frequency for up to 200,000 cycles with maximum cross-head displacement of 4 mm. The cross-head displacement accuracy shall be +/- 5% of the maximum displacement. - Strain monitoring equipment with minimum sample rate of at least 10 times the cyclic bending frequency with simul

21、taneous sampling of all channels. The specific requirements for data recording are described in section 10.3. The strain monitoring equipment shall be as per IPC/JEDEC-9704 guidelines. - Resistance monitoring equipment able to detect electrical failures as per the criteria defined in this standard.

22、The sample rate of resistance monitoring equipment shall be at least 10 times the cyclic bending frequency with simultaneous sampling of all channels. - A system which monitors both PCB strain and electrical resistance of daisy chain nets at the same sampling rate is preferred, but not required. JED

23、EC Standard No. 22B113A Page 2 Test Method B113A (Revision of B113) 3 Terms and definitions For purposes of this standard, the following definitions shall apply anvil: A four-point assembly fixture support with a rounded contact surface. average strain rate: The change in strain divided by the time

24、interval during which this change is measured. crosshead assembly: A clamping/attachment assembly of a universal tester that moves relative to the base of the test equipment and creates the forces necessary for specimen testing. cycle frequency: The number of times a test vehicle undergoes complete

25、loading and unloading sequences in one second. data logger: A high-speed resistance measurement equipment capable of measuring resistance of up to 36 channels simultaneously at a sampling rate of at least 30 hertz per channel. Dynamic mechanical analysis (DMA): A technique used to characterize mater

26、ials by applying a sinusoidal stress to measure the strain, allowing one to determine the complex modulus and viscoelastic behavior. NOTE 1 “Dynamic mechanical analysis” is also known as “dynamic mechanical spectroscopy”. NOTE 2 The temperature of the sample or the frequency of the stress are often

27、varied, leading to variations in the complex modulus; this approach can be used to locate the glass transition temperature of the material, as well as to identify transitions corresponding to other molecular motions. event: An electrical discontinuity of resistance greater than the threshold resista

28、nce lasting for a period of 1 microsecond. event detector: A continuity test instrument capable of detecting an electrical discontinuity of resistance greater than the threshold resistance and lasting for a period of 1 microsecond. four-point bending fixture: A test assembly that supports a specimen

29、 on two anvils or rollers and symmetrically loads the specimen on the opposite surface with two anvils or rollers. global PWB strain: The four-point bending strain of a printed wiring board measured between the edge of the component and the anvil as described in Figure 4. handheld electronic product

30、: An electronic product that can conveniently be stored in a pocket (of sufficient size) and operated when held in the users hand. NOTE Included in the concept of “handheld electronic products” are cameras, calculators, cell phones, pagers, palm-size PCs (formerly called “pocket organizers”), PCMCIA

31、 cards, smart cards, mobile phones, personal digital assistants (PDAs), and other communication devices. load span: The distance between the two anvils or rollers that load the test specimen. JEDEC Standard No. 22B113A Page 3 Test Method B113A (Revision of B113) 3 Terms and definitions (contd) micro

32、strain value: A dimensionless quantification of strain calculated as 106times the change in length divided by the original length. peak displacement: The maximum displacement applied to a printed wiring board by load anvils during cyclic bending. roller: A four-point assembly fixture support that in

33、corporates a cylindrical bar as the contact surface. single-sided PCB assembly: A printed circuit board assembly with components mounted on only one side of the board. SMT IC: Abbreviation for “surface-mount-technology integrated circuit”. strain: The deformation of a material body under the action

34、of an applied force. strain gage: A planar foil pattern that is adhered to an underlying surface and exhibits a change in resistance when subjected to a strain. strain gage element: The sensing area of a strain gage defined by the active serpentine grid pattern. strain value: A dimensionless quantif

35、ication of strain calculated as the change in length divided by the original length. support span: The distance between the two anvils or rollers that support the test specimen. thermomechanical analysis (TMA): A technique used to characterize materials by varying temperature, force, atmosphere, and

36、 measuring the change in properties, e.g. dimensions. threshold resistance: 1000 ohms or five times the initial resistance of the daisy chain net and associated wiring to the event detector/data logger, whichever is greater. uniaxial strain gage: A strain gage incorporating a single strain gage elem

37、ent, which means it is capable of detecting strain along a single axis only. universal tester: A piece of test equipment capable of tensile/compressive loading using controlled linear motion of a crosshead assembly. JEDEC Standard No. 22B113A Page 4 Test Method B113A (Revision of B113) 4 Applicable

38、documents JESD22-B111 Subassembly Mechanical Shock IPC-SMT-782 Surface Mount Design and Land Pattern Standard J-STD-020 Moisture/Reflow Sensitivity Classification for Non-hermetic Solid State Surface Mount Devices J-STD-033 Standard for Handling, Packing, Shipping and Use of Moisture/Reflow Sensitiv

39、e Surface Mount Devices IPC-9701 Performance Test Methods and Qualification Requirements for Surface Mount Solder Attachments IPC/JEDEC-9702 Monotonic Bend Characterization of Board-Level Interconnects IPC/JEDEC-9704 PWB Strain Gage Test Standard 5 Test method This publication standardizes 4-point b

40、end method for cyclic bend performance characterization of SMT ICs. The cyclic bending is achieved by resting the printed wiring board assembly on two support anvils while deflecting the board in the downward direction by displacing the load anvils. This is schematically depicted in Figure 1. The 4-

41、Point bend method is specified as it results in constant curvature of the board in between the two inner anvils if there are no SMT ICs on the board. With SMT ICs mounted, the local strain in the SMT IC region will be different from the global PWB strain. Due to large number of cycles for this test,

42、 the board may move on the anvils in the plane of the board (right / left). It is recommended that this movement is controlled to 1 mm max in each direction from the absolute center position of the roller anvil by designing some constraining features in the test fixture. Figure 1 Schematic showing 4

43、-Point bend setup Figure 1 describes the parameters needed to setup the cyclic bend test machine and the values of these parameters are specified in Table 1. The table lists the recommended value as well as optional values for some of the parameters. Wherever there is a choice, the optional paramete

44、rs should only be used if an acceleration factor has already been established and proven between the recommended and optional setting of a parameter. The parameter values listed under optional setting should not be exceeded as it may result in a change of failure mechanism. For cyclic bend test, the

45、 primary failure mechanism is solder fatigue in bulk solder. FixedAnvilsFixedAnvilsMoveableAnvilsMoveableAnvilsSupport SpanLoad SpanIC PackagesPrintedWiringBoardJEDEC Standard No. 22B113A Page 5 Test Method B113A (Revision of B113) 5 Test method (contd) Table 1 Recommended and Optional Parameters fo

46、r Cyclic 4-Point Bend Test Parameter Recommended Optional Span for support Anvils (mm) 110 N/A Span of Load Anvils (mm) 75 N/A Load Anvil to SMT IC Keep-out (the minimum distance from load anvil centerline to edge of closest SMT ICs) (mm) 10 N/A Minimum Anvil radius (mm) 3 N/A Load Anvil vertical di

47、splacement (mm) 2 Up to 4 mm Load profile Sinusoidal Triangular Cyclic Frequency (Hz) 1 Up to 3 6 SMT ICs This standard covers all area arrays and perimeter leaded surface mountable packaged semiconductor devices such as BGAs, LGAs (excluding connectors and sockets), CSPs, TSOPs, and QFNs or any sur

48、face mounted package. All SMT ICs used for this testing must be daisy chained. The daisy chain should either be done at the die level or by providing daisy chain links at the lead-frame or substrate level. In case of non-daisy chain die (i.e., when daisy chain is done at the substrate level), a mech

49、anical dummy die must be used inside the package to simulate the actual structure of the package. The die size and thickness should be similar to the functional die size to be used in application. The SMT IC materials, dimensions, and assembly processes shall be representative of typical production device. JEDEC Standard No. 22B113A Page 6 Test Method B113A (Revision of B113) 7 Test Board and SMT IC locations This standard recommends the use of drop test board as defined by JESD22-B111. The suggested board resembles the boards used in actual applications in material and constructio