JEDEC JESD229-2011 Wide I O Single Data Rate (Wide I O SDR).pdf

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1、JEDEC SOLID STATE TECHNOLOGY ASSOCIATIONDECEMBER 2011JEDECSTANDARDWide I/O Single Data RateJESD229(Wide I/O SDR)NOTICEJEDEC standards and publications contain material that has been prepared, reviewed, and approved through the JEDEC Board of Directors level and subsequently reviewed and approved by

2、the JEDEC legal counsel.JEDEC standards and publications are designed to serve the public interest through eliminating misunderstandings between manufacturers and purchasers, facilitating interchangeability and improvement of products, and assisting the purchaser in selecting and obtaining with mini

3、mum delay the proper product for use by those other than JEDEC members, whether the standard is to be used either domestically or internationally.JEDEC standards and publications are adopted without regard to whether or not their adoption may involve patents or articles, materials, or processes. By

4、such action JEDEC does not assume any liability to any patent owner, nor does it assume any obligation whatever to parties adopting the JEDEC standards or publications.The information included in JEDEC standards and publications represents a sound approach to product specification and application, p

5、rincipally from the solid state device manufacturer viewpoint. Within the JEDEC organization there are procedures whereby a JEDEC standard or publication may be further processed and ultimately become an ANSI standard.No claims to be in conformance with this standard may be made unless all requireme

6、nts stated in the standard are met.Inquiries, comments, and suggestions relative to the content of this JEDEC standard or publication should be addressed to JEDEC at the address below, or call (703) 907-7559 or www.jedec.orgPublished byJEDEC Solid State Technology Association 20113103 North 10th Str

7、eetSuite 240 SouthArlington, VA 22201-2107This document may be downloaded free of charge; however JEDEC retains thecopyright on this material. By downloading this file the individual agrees not tocharge for or resell the resulting material.PRICE: Please refer to twww.jedec.orgPrinted in the U.S.A. A

8、ll rights reservedPLEASE!DONT VIOLATETHELAW!This document is copyrighted by the JEDEC Solid State Technology Association and may not bereproduced without permission.Organizations may obtain permission to reproduce a limited number of copies through entering into a license agreement. For information,

9、 contact:JEDEC Solid State Technology Association3103 North 10th Street, Suite 240 SouthArlington, Virginia 22201-2107or call (703) 907-7559JEDEC Standard No. 229Page 1WIDE I/O SINGLE DATA RATE (WIDE I/O SDR)(From JEDEC Board Ballot JCB-11-79, formulated under the cognizance of the JC-42.6 Subcommit

10、tee on Low Power Memories.)1ScopeThis standard defines the Wide I/O specification, including features, functionality, AC and DC characteristics, packages, and micropillar signal assignments. This standard covers the following technologies: Wide I/O. The purpose of this standard is to define the mini

11、mum set of requirements for JEDEC compliant, 1 Gb through 32 Gb SDRAM (monolithic density) devices with 4, 128b wide channels using direct chip-to-chip attach methods between 1 to 4 memory devices and a controller device. This standard was created using aspects of the following standards: DDR2 (JESD

12、79-2), DDR3 (JESD79-3), LPDDR (JESD209), and LPDDR2 (JESD209-2). Each aspect of the standard was considered and approved by committee ballot(s). The accumulation of these ballots was then incorporated to prepare the Wide I/O standard. 2 General Description2.1 Terms and DefinitionsWithin the Wide I/O

13、 standard, these terms have particular meanings:Stack: All memory chips in the memory system taken together in one assembly. NOTE This Wide I/O standard supports memory stacks that include up to 4 memory chips.Slice: One memory chip in the stack of memory chips.Rank: That portion of memory from one

14、memory die that is logically connected to a single channel within the memory stack.Channel: Both a set of physically discrete connections within the Wide I/O interface and a logically discrete, independently controlled partition of the Wide I/O interface. NOTE The Wide I/O interface supports 4 physi

15、cal and 4 logical channels. Each physical channel contains all the control, data and clock signals necessary to independently control each of the 4 logical channels in the Wide I/O interface. Aside from a few global configuration options, each logical channel has its own set of mode registers, can h

16、ave different DRAM pages open, can be independently clocked and can even be in different power states. The physical channel also contains power and ground signals but all power and ground signals on all physical channels must be at their appropriate levels for any portion of the Wide I/O device to o

17、perate correctly. The physical channel also contains a reset signal but the Wide I/O interface defines reset to be per slice rather than per channel.2.2 Micropillar-out2.2.1 Key Features- 128 Data Bits per channel- Support for up to 32 Gbit monolithic density- micropillars allocated for differential

18、 CK/DQS for future DDR extension- 5 Serial Scan connections/channel + 1 overall serial enable- Per byte write masks- 1 “must be routed through substrate” Direct Access micropillar per channel- 2 missing row vertical channel spacing, 6 missing column horizontal channel spacing- Power micropillar coun

19、t supports current requirements of low-power memory spaceJEDEC Standard No. 229Page 22.2.2 Micropillar DefinitionsNOTE 1 All views are the bottom views looking down upon the memory micropillars, i.e., with the memory micropillars facing out of the page. In the anticipated mounting orientation, this

20、will be looking up from the board.NOTE 2 There are 10 NC micropillars in channel B and 9 NC micropillars in channel A, C and D. The NC micropillar will be with micro bump and the missing micropillar will be without micropillar and microbump.Table 1 Micropillar DefinitionsMicropillar Type Count Descr

21、iptionVDD1 6 Core PowerVDD2 20 Core PowerVDDQ 16 I/O PowerVSS 24 Core GroundVSSQ 16 I/O GroundDQ 128 DataDQS 16 Data Strobe DQS_t, DQS_c (unused in current definition)DM 16 Data MaskADDR 19 Address (0-16), Bank (0-1)CMD 4 RAS_n, CAS_n, WE_n, RESETCK 2 CK_t, CK_c (unused in current definition)CS 4 Ch

22、ip (Rank) SelectCKE 4 Clock EnableTEST 1/0Memory DA Test Mode Enable (only on channel A, location is DA(o) on other channels)SER 5 Serial Boundary Scan micropillars (uses CS to select rank)KEY 1Vendor Specific micropillar in channel A, n/c in channel B, Scan Enable in channel C, missing micropillar

23、in channel D.NC 9 no connectDA 1Direct Access (all SoC vendors will provide direct connection to memory through substrate)DA(o) 8/9Direct Access (optional, SoC vendors may or may not provide direct connections to memory through substrate)Total 300JEDEC Standard No. 229Page 32.2.3 Left Side of Array

24、Showing Two of Four ChannelsFigure 1 Left Side of Array Showing Two of Four ChannelsJEDEC Standard No. 229Page 42.2.4 Channel A Micropillar LocationsFigure 2 Channel A Micropillar LocationsJEDEC Standard No. 229Page 52.2.5 Center Area of 4-Channel MapFigure 3 Center Area of 4-Channel MapNote the cha

25、nnel spacing and the micropillar assignments are reflections of Channel A.The overall array size is (5.25mm + 1 micropillar diameter) x (0.52mm + 1 micropillar diameter). The pitch (center to center) is 40 microns in the vertical dimension and 50 microns in the horizontal dimension.JEDEC Standard No

26、. 229Page 62.3 Input/Output Functional Description2.3.1 Micropillar Definition and DescriptionNote on nomenclature: unless otherwise designated, each channel is independent and implements independent sets of the designated micropillars. The channels are designated “a” to “d”. Additionally, unless ot

27、herwise designated, all signals are directly connected to all ranks (0 to 3) in the stack.Table 2 Micropillar Definition and DescriptionName Type DescriptionCK_ta:d Input Clock: CK_t is a single-ended clock input. All Control, Address and Write Data (DQ) inputs are sampled on the positive edge of CK

28、_t. The positive clock edge is defined by CK_t crossing 50% VDDQ. CKE0:3a:d Input Clock Enable: CKE HIGH activates and CKE LOW deactivates internal clock signals and therefore device input buffers and output drivers. Power savings modes are entered and exited through CKE transitions. CKE is consider

29、ed part of the command code. See Command Truth Table for command code descriptions. Each of CKE0:3a:d address a single rank (0 to 3) on each of the channels (a to d).CS0:3_na:d Input Chip Select: CS_n is considered part of the command code. See Command Truth Table for command code descriptions. Each

30、 of CS0:3_na:d address a single rank (0 to 3) on each of the channels (a to d).RAS_na:d, CAS_na:d, WE_na:dInput Command Inputs: Uni-directional command inputs. RAS_n, CAS_n and WE_n define the command being selected. See Command Truth Table for command code descriptions.A0:16a:d Input Address Inputs

31、: Uni-directional address inputs. These provide the Row Address inputs for activate commands, the Column Address and Auto Precharge inputs for Read and Write commands, the Short Preamble inputs for Read commands, and the opcode for the Mode Register Set commands.A10/APa:d Input Autoprecharge: A10 is

32、 sampled during Read/Write commands to determine whether Autoprecharge should be performed to the accessed bank after the Read/Write operation.(High:Autoprecharge, Low: No Autoprecharge)A11/SPa:d Input Short Preamble: The controller indicate read with short preamble by driving A11 high when signalli

33、ng a read command.BA0:1a:d Input Bank Inputs: Uni-directional bank select inputs. These provide the Bank Select inputs for activate, read, write and precharge commands.RST0:3_n Input Reset Input: Uni-directional reset input. Each reset line resets all channels in a single slice. RST0_n appears on ch

34、annel a and resets slice 0 (corresponding to CKE0/CS0_n) RST1_n appears on channel b and resets slice 1, RST2_n appears on channel c and resets slice 2, RST3_n appears on channel d and resets slice 3. DQ0:127 a:d I/O Data Inputs/Output: Bi-directional data busDQS0:7_t a:dOutput (possibly I/O in futu

35、re)Data Strobe: Data strobe (DQS_t) is output only in the current definition. Memories generate DQS_t such that a positive or a negative edge of DQS_t occurs in the middle of the read data eye with DQ providing a setup and a hold time to the DQS edge. Each DQS_t strobes two bytes of data. For timing

36、 purposes, the DQS edge is defined by DQS_t crossing 50% VDDQ. Note: write data is sampled on the positive edge of CK_t. In future extensions, DQS_t may be bidirectional.DM0:15a:d Input Input Data Mask: DM is the input mask signal for write data. Input data is masked when DM is sampled HIGH coincide

37、nt with that input data during a Write access. DM is sampled on the rising edge of CK_t coincident with the write data. Although DM is for input only, the DM loading shall match DQ, DQS_t and DQS_c. DM0 is the input data mask signal for the data on DQ0-7. DM1 is the input data mask signal for the da

38、ta on DQ8-DQ15, and so on, i.e., DM15 is the input data mask signal for data on DQ120-DQ127.TEST Input Test: This input makes memory DA test mode enable. It may be routed through a controller I/O buffer before driving the memory I/O pad. Its function is defined by each individual memory vendor.SDIa:

39、d, SCKa:d, SOE_na:d, SSH_na:dInput Boundary Scan Inputs: These inputs provide the necessary connections for the memory boundary scan functionality as defined in Section 5.JEDEC Standard No. 229Page 72.4 AddressingWide I/O has 4 channels and total x512 bit I/Os. Each channel has 4 Banks and x128 bit

40、I/Os. Table 3 Wide I/O AddressingDeviceDensityDensity / ChannelAddressBA Row Column1Gb256MbBA0 - BA1 RA0 - RA11 CA0 - CA62Gb512MbBA0 - BA1 RA0 - RA12 CA0 - CA64Gb 1Gb BA0 - BA1 RA0 - RA13 CA0 - CA68Gb 2Gb BA0 - BA1 RA0 - RA14 CA0 - CA616Gb 4Gb BA0 - BA1 RA0 - RA14 CA0 - CA732Gb 8Gb TBD TBD TBD3 Func

41、tional Description3.1 Wide I/O State DiagramWide I/O DRAM device state diagram provides a simplified illustration of allowed state transitions and the related commands to control them. Unless otherwise specified, the state diagram describes the state and commands for only one channel in a slice.For

42、a complete definition of the device behavior, the information provided by the state diagram should be integrated with the truth tables and timing specification.SDOa:d Output Boundary Scan Outputs: This output provides the necessary connection for the memory boundary scan functionality as defined in

43、Section 5. DAa:d Input/OutputDirect Access Input/Output: This I/O is used by memory for direct access test functionality. It must be routed directly to an external package I/O pad. Its function is defined by each individual memory vendor.DA(o)0:7 a:dDA(o)8b:dInput/OutputDirect Access Input/Output: T

44、his I/O is used by memory for direct access test functionality. It may be routed through a controller I/O buffer before driving an external package I/O pad. Their functions are defined by each individual memory vendor.KEY This is a missing micropillar in the array used to indicate array orientation.

45、 It appears only in channel D.VPIN Input This micropillar is used to select vendor specific features. It appears only in channel A.SSEN Input This micropillar is used to set the entire DRAM to boundary scan mode (high) or normal operation mode (low). It appears only on channel C.CK_ca:d This is the

46、compliment of CK_t. It is not currently used by the Wide I/O standard. It is included only for future extension.DQS0:7_c a:dThese are the compliments of DQS_t. They are not currently used by the Wide I/O standard. They are included only for future extension.NC No connect pads.VDD1Supply Core Power S

47、upply 1: Core power supply.VDD2Supply Core Power Supply 2: Core and input buffer power supply. VDDQSupply I/O Power Supply: Power supply for Data input/output buffers. VSSSupply GroundVSSQSupply I/O GroundName Type DescriptionJEDEC Standard No. 229Page 83.1 Wide I/O State Diagram (contd)The truth ta

48、bles provide complementary information to the state diagram, they clarify the device behavior and the applied restriction when considering the actual state of the banks.SelfIdle *1PrechargeWriteACTRD,RSPSREFREFAPDPDXPDXPDWRAutomatic SequenceCommand SequenceRDA,RSPAWRARefreshRefreshPowerDownActivewit

49、h ReadwithActiveReadWritePR(A) = Precharge (All)MRS = Mode Register SetSREF = Enter Self RefreshPD = Enter Power DownPDX = Exit Power DownACT = ActivateWR(A) = Write (with Autoprecharge)RD(A) = Read (with Autoprecharge)SREFXRD,RSPBSTAutoprechargeAutoprechargeDeep *2PowerReset *2PowerDownRampBSTWRBST = Burst TerminateSRR = Status Register ReadSREFX = Exit Self RefreshDPD = Enter Deep Power DownREFA = Auto RefreshMRSDPD *3PowerAppliedRD*2Reset Reset = Reset ProcedureRDA,RSPAWRAInitializationDownPower