JEDEC JESD229-2-2014 Wide I O 2 (WideIO2).pdf

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1、JEDEC SOLID STATE TECHNOLOGY ASSOCIATIONAUGUST 2014JEDECSTANDARDWide I/O 2 (WideIO2)JESD229-2PLEASE!DONT VIOLATETHELAW!This document is copyrighted by the JEDEC and may not bereproduced without permission.For information, contact:JEDEC Solid State Technology Association3103 North 10th Street, Suite

2、240 SouthArlington, Virginia 22201-2107or refer to www.jedec.org under Standards-Documents/Copyright InformationJEDEC Standard No.229-2Page 1WIDE I/O 2 (WideIO2) STANDARD (From JEDEC Board Ballot JCB-14-40, formulated under the cognizance of the JC-42.6 Subcommittee on Low Power Memories.)1 ScopeThi

3、s standard defines Wide I/O 2 (WideIO2), including features, functionality, AC and DC characteristics, packages, and micropillar signal assignments. The purpose of this standard is to define the minimum set of requirements for JEDEC compliant, 8 Gb through 32 Gb SDRAM devices with 4 or 8 64-bit wide

4、 channels using direct chip-to-chip attach methods for between 1 and 4 memory devices and a controller/buffer device. This standard was created using aspects of the following standards: DDR2 (JESD79-2), DDR3 (JESD79-3), LPDDR (JESD209), LPDDR2 (JESD209-2), LPDDR3 (JESD209-3) and WIO (JESD229-1). Eac

5、h aspect of the standard will require approval by committee ballot(s). The accumulation of these ballots will then be incorporated into the WideIO2 standard.The WideIO2 architecture is an evolution of the WIO architecture to enable bandwidth scaling with capacity.2 General Description2.1 Terms and D

6、efinitionsWithin the WideIO2 standard, these terms have particular meanings:Stack: All memory chips in the memory system taken together in one assembly. The WideIO2 standard supports memory stacks of up to 4 memory chips.Slice: One memory chip in the stack of memory chips as shown in Figure 1.Quadra

7、nt: A single memory chip is divided into 4 quadrants as shown in Figure 8.Micropillar: An electrical connection between two stacked die. The connection is made between the lower dies top metal layer and an upper dies pad by cutting a hole in the passivation on the lower die and inserting a conductin

8、g pillar.Rank: Multiple slices can be connected to a single channel in a multidrop fashion within the memory stack. The DRAM array connected to the channel is referred to as a rank. WideIO2 supports single and dual rank configurations.Channel: A set of physically discrete connections within the Wide

9、IO2 interface that independently control a partition of the WideIO2 device. (see Figure 1).NOTE The WideIO2 interface supports 4 or 8 physical channels. Each channel contains all the control, data, and clock signals necessary to independently control a partition of the WideIO2 device. Each channel c

10、an have different DRAM pages open, can be independently clocked, and can be in different power states. The physical channel also includes I/O power and ground signals. All power and ground signals for all channels must be at their appropriate levels for any portion of the WideIO2 device to operate c

11、orrectly. The physical channel also contains a reset signal but the WideIO2 interface defines reset to be per slice rather than per channel.JEDEC Standard No. 229-2Page 22.1 Terms and Definitions (contd)Figure 1 Definition of Terms for WideIO2 stack2.2 Key Features. Support for 800MT/s and 1067MT/s

12、data rates. 25.6GB/s and 34.1GB/s with four 64b channels (4x64 die). 51.2GB/s and 68.3GB/s with eight 64b channels (8x64 die). DRAM core frequencies of 200MHz and 266MHz. Configurable with1, 2, or 4 stacked die for bandwidth and capacity scaling. 4KB page size with 8 banks per channel for 4x64 die.

13、2KB page size with 4 banks per channel for 8x64 die. 64 Data Bits per channel. Support for burst lengths of 4 and 8. Complementary data strobe for every 16 data bits. Double Data Rate for command and data. Unterminated CMOS I/O signaling. No PLL or DLL in the DRAM. Per byte write data mask and data

14、bus inversion. Multiplexed Command Address (11 CA signals over 2 UI). Each rank in each channel will have its own set of Mode Registers. Each channel is independent. Support for 8, 16, and 32Gb DRAM die density. Per slice scan chain. Per slice Reset. Support for supplier specific Direct Access Mode

15、test feature with 10 digital and 1 analog signals per quadrant. Support for GPIO Mode test access. Support for Post Package Repair. Power micropillar count supports current requirements of low-power memory space. VDDQ = VDD2 = 1.1V. VDD1 = 1.8VJEDEC Standard No.229-2Page 32.3 Bandwidth vs. Capacity

16、Relationship The WideIO2 device is targeted to operate up to 800 or 1067MT/s with 64b per channel. The per die density will be either 8, 16, or 32 Gb. Depending on the configuration, the bandwidth and capacity scale as shown in Table 1. The bandwidth is calculated by the transfers x bytes/channel x

17、number of channels. P22P configurations will double the capacity while the bandwidth stays constant.Table 1 Capacity vs. Bandwidth (8 - 32Gb Die Density)DieConfigurationCapacity800 MT/s Band-width1067 MT/s Band-widthFigure4x64 Die1 Slice, 4 Channel1 - 4GB 25.6GB/s 34.1GB/s Figure 22 Slice, 8 Channel

18、2 - 8GB 51.2GB/s 68.3GB/s Figure 34 Slice, 8 Channel, P22P Dual Rank4 - 16GB 51.2GB/s 68.3GB/s Figure 48x64 Die1 Slice, 8 Channel1 - 4GB 51.2GB/s 68.3GB/s Figure 52 Slice, 8 Channel, P22P Dual Rank2 - 8GB 51.2GB/s 68.3GB/s Figure 62.4 WideIO2 TopologiesWideIO2 topologies require a shifting of signal

19、s through the stack. This shifting is done in the metal layers ofthe lower die. The WideIO2 topologies shown in this section are from an SOC point of view (SOC at bottom ofstack). A 4 channel topology will only have a single channel (channel 0) for each of the 4 quadrant (A-D).The 4 channels will be

20、 referred to as: 0A, 0B, 0C, and 0D. An 8 channel topology will have a channel 0 andchannel 1 for each of the 4 quadrants (A-D). The 8 channels will be referred to as: 0A, 1A, 0B, 1B, 0C, 1C,0D, and 1D. All of the figures in this section will show one of the channels in a magenta color.2.4.1 WideIO2

21、 Topologies with 4x64 Die2.4.1.1 1-High 4Ch x 64bFigure 2 shows the baseline WideIO2 1 slice, 4 channel P2P topology. There are a total of 128 DQs perquadrant with only 64 being used in this topology.Figure 2 P2P WideIO2: 1 Slice, 4 ChannelJEDEC Standard No. 229-2Page 42.4.1.2 2-High 8Ch x 64b Capac

22、ity and Bandwidth ScalingFigure 3 shows a WideIO2 2 slice, 8 channel P2P topology. Since this is an 8 channel, P2P topology, eachchannel from the second slice increases the overall bandwidth with a constant capacity per channel.Figure 3 P2P WideIO2: 2 Slice, 8 Channel2.4.1.3 4-High, 8Ch x 64b, P22P

23、Capacity and Bandwidth ScalingFigure 4 shows a WideIO2 4 slice, 2 rank, 8 channel P22P topology with separate CA buses to avoid P24Ploading on CA. This configuration scales both capacity and bandwidth.Figure 4 P22P WideIO2: 4 Slice, 2 Rank, 8 Channel2.4.2 WideIO2 Topologies with 8x64 Die2.4.2.1 1-Hi

24、gh 8Ch x 64bFigure 5 shows a WideIO2 1-slice, 8-channel P2P topology.Figure 5 P2P WideIO2: 1 Slice, 8 ChannelsJEDEC Standard No.229-2Page 52.4.2.2 2-High 8Ch x 64bFigure 6 shows a WideIO2 2-slice, 8-channel, P22P topology. The CS and CKE signals are staggered in pairs. CS2/CKE2 is connected to CS0/C

25、KE0 on upper die and CS3/CKE3 is connected to CS1/CKE1 on upper die.Figure 6 P22P WideIO2: 2 Slice, 8 ChannelsJEDEC Standard No. 229-2Page 62.5 Micropillar-out2.5.1 Micropillar Definition and DescriptionNote on nomenclature: unless otherwise designated, each channel is independent and implements ind

26、ependent sets of the designated micropillars. Signal naming convention designates quadrant and channel within each quadrant as follows:1:0D:Amsb:lsb. 1:0 denotes which channel within the quadrant. D:A denotes which quadrant. msb:lsb denotes index of bus. _n for active low, _t for true, and _c for co

27、mplement polarityFor example DQ1A13 would be DQ13 in quadrant A channel 1.Table 2 Micropillar Definition and DescriptionNameSignalChQuadbitTypeDescriptionCK1:0D:A_t, CK1:0D:A_cInputClock: CK_t and CK_c are Complementary clock inputs to each channel. All Command signals are sampled on the positive ed

28、ges of CK_t and CK_c providing a double rate com-mand bus. The clocks are not free running, they will toggle as commands are latched into the device and long enough after the command is latched to allow the command to com-plete. Clock is defined as the complementary pair CK_t and CK_c.CA1:0D:A10:0In

29、putCommand/Address: There are 11 command/address signals per channel and a command packet is 2UI in length giving a payload of 22 bits of information. The CA bus will be clocked by CK_t/CK_c clocks.CSD:A3:0_nInputChip Select: CS_n is considered part of the command code. Each of CSD:A3:0_n address a

30、single rank on each of the channels. See Table 20 - Command Truth Table for command code descriptions. See Table 6 for CS_n signal mapping.CKED:A3:0InputClock Enables: CKE HIGH activates and CKE LOW deactivates internal clock signals, device input buffers and output drivers. Power savings modes are

31、entered and exited through CKE transitions. CKE is considered part of the command code. See Table 21 - Command Truth Table for command code descriptions. See Table 6 for CKE signal map-ping.DQ1:0D:A63:0 I/OData Inputs/Output: Bi-directional data bus. 64 DQs per channel.DQS1:0D:A3:0_tDQS1:0D:A3:0_cI/

32、OData Strobe (Bi-directional, Complementary): The data strobe is bidirectional (used for read and write data) and complimentary (DQS_t and DQS_c). It is output with read data and input with write data. DQS_t and DQS_c are edge-aligned to read data and cen-tered with write data. Each DQS pair strobes

33、 16 DQ I/Os.DMI1:0D:A7:0I/OData Mask and Data Bus Inversion: DMI is a bidirectional signal sampled on the rising edges of DQS_t and DQS_c. See section 3.3.RST3:0_nInputReset: Unidirectional reset inputs. These are per slice reset signals.SEN2:0InputBoundary Scan Enable: Used to enable normal operati

34、on, boundary scan, or 1 of 6 ven-dor specific scan chains. Boundary scan modes may be operational in all normal and test modes, as defined by each individual memory vendor.SSH_nInputBoundary Scan Shift: There is one SSH_n provided to all slices in the WideIO2 stack using Through routing.SDIInputBoun

35、dary Scan Serial Data In: There is one SDI provided to all slices in the WideIO2 stack using Through routing.SCKInputBoundary Scan Clock: There is one SCK provided to all slices in the WideIO2 stack using Through routing.JEDEC Standard No.229-2Page 7NOTE 1 All DA pins must be ESD harden, in the Wide

36、IO2 device, up to 2KV HBM (Human Body Model) level or 200V for MM (Machine Model) level, as stated in ANSI/ESDA/JEDEC JS-001-2012 spec.SCS3:0_nInputBoundary Scan Chip Selects: There is a one SCS3:0_n per slice using Staggered rout-ing.SDO3:0OutputBoundary Scan Output: There is one SDO output per sli

37、ce using Staggered routing.TESTInputTEST: This input enables memory GPIO test mode. It may be routed through a controller I/O buffer before driving the memory I/O pad.DAAD:AI/ODirect Access Analog: This is a vendor specific test feature. These I/Os provide an ana-log direct access path to DRAM core

38、signals for test/debug purposes. They must be routed directly to external package I/O pads to allow unbuffered visibility to an internal analog signal. They can be connected through the vertical stack in a multidrop topology as defined by each individual memory vendor. There is one DAA per quadrant.

39、 DAA pins may be operational in all normal and test modes, as defined by each individual memory vendor.DAD:A9:0I/ODirect Access: This is a vendor specific test feature. These I/Os provide digital direct access to internal DRAM core signals for test/debug purposes. They can be connected through the v

40、ertical stack in a multidrop topology as defined by each individual memory vendor. There are 10 digital DAs per quadrant. One of these I/Os may be used to enabled Direct Access test mode. If DA Mode is supported by an SOC design, they must be routed directly to external package I/O pads to allow unb

41、uffered access to these signals. When not in DA mode each DA pin on the device will either be left floating or have a keeper to pull it low. The SOC is not required to pull up or pull down any of the DA pins and should leave these signals floating. The device must account for up to 5uA of SOC leakag

42、e current on these signals.NCNANo Connection: This micropillar is a spare and not connected in the WideIO2 device.VDD1SupplyCore Voltage Supply 1: Core power supply.VDD2SupplyCore Voltage Supply 2: Core power supply. VDDQSupplyI/O Voltage Supply: Power supply for the DQ, DQS, and DMI I/O buffers. VS

43、SSupplyGroundVSSQSupplyI/O GroundTable 2 Micropillar Definition and DescriptionNameSignalChQuadbitTypeDescriptionJEDEC Standard No. 229-2Page 82.5.2 Quadrant Micropillars NOTE 1 The power and ground signal counts remain the same for both 4 channel and 8 channel configurations (all power and grounds

44、need to be connected for all configurations).NOTE 2 For configurations with 4 channels the SOC will need to connect their unused signals to a known value.2.5.3 Channel Interface SignalsTable 3 Micropillar Definitions (Per Quadrant)Micropillar TypeCountDescriptionVDD112Core Voltage 1VDD260Core Voltag

45、e 2VSS72Core GroundVDDQ42I/O VoltageVSSQ42I/O GroundDQ128DataDMI16Data Mask and Data Bus InversionDQS16Complementary Data Strobe: DQS_t, DQS_cCA22Encoded address and commandCS_n4Chip SelectCKE4Clock EnableCK4Complementary Clock: CK_t, CK_cMisc5Miscellaneous (RST_n, Serial Port, TEST (average. per qu

46、adrant)DAA/DA11Direct Access for Test (1 analog, 10 digital)Total438Per QuadrantTable 4 Channel Interface SignalsMicropillar TypeCountDescriptionDQ64DataDMI8Data Mask and Data Bus InversionDQS8Complementary Data Strobe: DQS_t, DQS_cCA11Encoded address and commandCKE2Clock EnableCS_n2Chip SelectCK2Co

47、mplementary Clock: CK_t, CK_cTotal97Per QuadrantTable 5 DQS and DMI MappingDQ SignalDQS MappingDMI MappingDQ7:0DQS0_t, DQS0_cDMI0DQ15:8DQS0_t, DQS0_cDMI1DQ23:16DQS1_t, DQS1_cDMI2DQ31:24DQS1_t, DQS1_cDMI3DQ39:32DQS2_t, DQS2_cDMI4DQ47:40DQS2_t, DQS2_cDMI5DQ55:48DQS3_t, DQS3_cDMI6DQ63:56DQS3_t, DQS3_cD

48、MI7JEDEC Standard No.229-2Page 92.5.3 Channel Interface Signals (contd)NOTE 1 The table does not show quadrant and slice information. For example, the DQS true signal for DQ39, Channel 1, Quadrant C would be DQS1C2 (Micropillar Definition and Description ).Table 6 CKE and CS MappingConfiguration4x64

49、8x641 High P2PCKE0, CS0 for Ch. 0CKE0, CS0 for Ch. 0CKE1, CS1 for Ch. 12 High P2PCKE0, CS0 for Ch. 0CKE1, CS1 for Ch. 1NA2 High P22PNACKE0, CS0 for Ch. 0 of Rank 0CKE1, CS1 for Ch. 1 of Rank 0CKE2, CS2 for Ch. 0 of Rank 1CKE3, CS3 for Ch. 1 of Rank 14 High P22PCKE0, CS0 for Ch. 0 of Rank 0CKE1, CS1 for Ch. 1 of Rank 0CKE2, CS2 for Ch. 0 of Rank 1C