JEDEC JESD22-A111B-2018 Evaluation Procedure for Determining Capability to Bottom Side Board Attach by Full Body Solder Immersion of Small Surface Mount Solid State Devices.pdf
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1、 JEDEC STANDARD Evaluation Procedure for Determining Capability to Bottom Side Board Attach by Full Body Solder Immersion of Small Surface Mount Solid State Devices JESD22-A111B (Revision of JESD22-A111A, November 2010) MARCH 2018 JEDEC SOLID STATE TECHNOLOGY ASSOCIATION NOTICE JEDEC standards and p
2、ublications contain material that has been prepared, reviewed, and approved through the JEDEC Board of Directors level and subsequently reviewed and approved by the JEDEC legal counsel. JEDEC standards and publications are designed to serve the public interest through eliminating misunderstandings b
3、etween manufacturers and purchasers, facilitating interchangeability and improvement of products, and assisting the purchaser in selecting and obtaining with minimum delay the proper product for use by those other than JEDEC members, whether the standard is to be used either domestically or internat
4、ionally. JEDEC standards and publications are adopted without regard to whether or not their adoption may involve patents or articles, materials, or processes. By such action JEDEC does not assume any liability to any patent owner, nor does it assume any obligation whatever to parties adopting the J
5、EDEC standards or publications. The information included in JEDEC standards and publications represents a sound approach to product specification and application, principally from the solid state device manufacturer viewpoint. Within the JEDEC organization there are procedures whereby a JEDEC standa
6、rd or publication may be further processed and ultimately become an ANSI standard. No claims to be in conformance with this standard may be made unless all requirements stated in the standard are met. Inquiries, comments, and suggestions relative to the content of this JEDEC standard or publication
7、should be addressed to JEDEC at the address below, or refer to www.jedec.org under Standards and Documents for alternative contact information. Published by JEDEC Solid State Technology Association 2018 3103 North 10th Street Suite 240 South Arlington, VA 22201-2107 This document may be downloaded f
8、ree of charge; however JEDEC retains the copyright on this material. By downloading this file the individual agrees not to charge for or resell the resulting material. PRICE: Contact JEDEC Printed in the U.S.A. All rights reserved PLEASE! DONT VIOLATE THE LAW! This document is copyrighted by JEDEC a
9、nd may not be reproduced without permission. For information, contact: JEDEC Solid State Technology Association 3103 North 10th Street Suite 240 South Arlington, VA 22201-2107 or refer to www.jedec.org under Standards-Documents/Copyright Information. JEDEC Standard No. 22-A111B -i- Test Method A111B
10、 (Revision of Test Method A111A) EVALUATION PROCEDURE FOR DETERMINING CAPABILITY TO BOTTOM SIDE BOARD ATTACH BY FULL BODY SOLDER IMMERSION OF SMALL SURFACE MOUNT SOLID STATE DEVICES Introduction Frequently, small Surface Mount Devices (SMDs) are attached to the bottom side of a printed circuit board
11、 by passing them through a wave solder (full body immersion) while simultaneously soldering devices with pins on the top of the board (plated through hole attach). As a result, these small SMDs may be exposed to temperatures as high as 265 C during this type of board attach method. If sufficient moi
12、sture exists in the package, exposure to the molten solder causes the moisture to turn to vapor, resulting in increased pressure within the package which in turn may cause quality and/or reliability degradation. The test method in this document will address the issues related to the determination of
13、 the capability of a solid state device to withstand the stresses of full body wave solder immersion and subsequent field use. JEDEC Standard No. 22-A111B Test Method A111B -ii- (Revision of Test Method A111A) JEDEC Standard No. 22-A111B Page 1 Test Method A111B (Revision of Test Method A111A) EVALU
14、ATION PROCEDURE FOR DETERMINING CAPABILITY TO BOTTOM SIDE BOARD ATTACH BY FULL BODY SOLDER IMMERSION OF SMALL SURFACE MOUNT SOLID STATE DEVICES (From JEDEC Board Ballot JCB-18-13, formulated under the cognizance of the JC-14.1 Subcommittee on Reliability Test Methods for Packaged Devices.) 1 Scope T
15、his evaluation procedure is written to provide users of ICs of small surface mount packages with a method to evaluate the capability of a device to withstand full wave solder immersion. This document lists procedures for two solder pot, nominal temperatures, 245C and 260C. The 260C condition can cov
16、er both SnPb and Pb-free solders. Typically packages capable of full body solder immersion (wave solder immersion) board attach have a lead pitch greater than 0.5 mm. There is only limited demonstrated capability to survive full body (wave solder) immersion attach for QFPs and packages with bodies l
17、arger than 5.5 mm x 12.5 mm (or die paddle sizes greater than 2.5 mm x 3.5 mm). Devices in packages with limited or no data for capability demonstration should not be wave soldered. The capability of a device for full body immersion is strongly affected by its package structure. Devices with large b
18、ody packages may have reliability and/or quality problems induced by such a board attach method. Die and paddle sizes, as well as wavesolder conditions (board size, package profile, speed, part density, etc.), are some of the factors that modulate quality and reliability problems. Package styles wit
19、h bottom terminations, such as Ball Grid Array (BGA), Land Grid Array (LGA), and Quad/Dual Flatpack No lead (QFN/DFN) are not suitable for full body solder immersion board attach. If wave solder immersion results in a different Moisture Sensitivity Level than the J-STD-020 solder reflow level specif
20、ied by the supplier, the user must take appropriate precautions to ensure that the new floor life is not exceeded during the users manufacturing processes. The purpose of this test method is to identify the potential wave solder classification level of small plastic Surface Mount Devices (SMDs) that
21、 are sensitive to moisture-induced stress so that they can be properly packaged, stored, and handled per J-STD-033 to avoid subsequent mechanical damage during the assembly wave solder attachment and/or repair operations. This test method also provides a reliability preconditioning sequence for smal
22、l SMDs that are wave soldered using full body immersion. This test method, may be used by users to determine what classification level should be used for initial board level reliability qualification. 2 Applicable documents JESD22-A113, Preconditioning Procedures of Plastic Surface Mount Devices Pri
23、or to Reliability Testing JESD47, Stress Test Driven Qualification Specification JESD625, Requirements for handling Electrostatic Discharge Sensitive (ESD) Devices J-STD-020, Moisture/Reflow Sensitivity Classification for Non-Hermetic Solid State Surface Devices J-STD-033, Standard for Handling, Pac
24、king, Shipping and Use of Moisture/Reflow Sensitive Surface Mount Devices J-STD-035, Acoustic Microscopy for Non-Hermetic Encapsulated Electronic Components JEDEC Standard No. 22-A111B Page 2 Test Method A111B (Revision of Test Method A111A) 3 Apparatus 3.1 Bake oven Ovens capable of operating at 12
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