JEDEC JESD22-A111B-2018 Evaluation Procedure for Determining Capability to Bottom Side Board Attach by Full Body Solder Immersion of Small Surface Mount Solid State Devices.pdf

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1、 JEDEC STANDARD Evaluation Procedure for Determining Capability to Bottom Side Board Attach by Full Body Solder Immersion of Small Surface Mount Solid State Devices JESD22-A111B (Revision of JESD22-A111A, November 2010) MARCH 2018 JEDEC SOLID STATE TECHNOLOGY ASSOCIATION NOTICE JEDEC standards and p

2、ublications contain material that has been prepared, reviewed, and approved through the JEDEC Board of Directors level and subsequently reviewed and approved by the JEDEC legal counsel. JEDEC standards and publications are designed to serve the public interest through eliminating misunderstandings b

3、etween manufacturers and purchasers, facilitating interchangeability and improvement of products, and assisting the purchaser in selecting and obtaining with minimum delay the proper product for use by those other than JEDEC members, whether the standard is to be used either domestically or internat

4、ionally. JEDEC standards and publications are adopted without regard to whether or not their adoption may involve patents or articles, materials, or processes. By such action JEDEC does not assume any liability to any patent owner, nor does it assume any obligation whatever to parties adopting the J

5、EDEC standards or publications. The information included in JEDEC standards and publications represents a sound approach to product specification and application, principally from the solid state device manufacturer viewpoint. Within the JEDEC organization there are procedures whereby a JEDEC standa

6、rd or publication may be further processed and ultimately become an ANSI standard. No claims to be in conformance with this standard may be made unless all requirements stated in the standard are met. Inquiries, comments, and suggestions relative to the content of this JEDEC standard or publication

7、should be addressed to JEDEC at the address below, or refer to www.jedec.org under Standards and Documents for alternative contact information. Published by JEDEC Solid State Technology Association 2018 3103 North 10th Street Suite 240 South Arlington, VA 22201-2107 This document may be downloaded f

8、ree of charge; however JEDEC retains the copyright on this material. By downloading this file the individual agrees not to charge for or resell the resulting material. PRICE: Contact JEDEC Printed in the U.S.A. All rights reserved PLEASE! DONT VIOLATE THE LAW! This document is copyrighted by JEDEC a

9、nd may not be reproduced without permission. For information, contact: JEDEC Solid State Technology Association 3103 North 10th Street Suite 240 South Arlington, VA 22201-2107 or refer to www.jedec.org under Standards-Documents/Copyright Information. JEDEC Standard No. 22-A111B -i- Test Method A111B

10、 (Revision of Test Method A111A) EVALUATION PROCEDURE FOR DETERMINING CAPABILITY TO BOTTOM SIDE BOARD ATTACH BY FULL BODY SOLDER IMMERSION OF SMALL SURFACE MOUNT SOLID STATE DEVICES Introduction Frequently, small Surface Mount Devices (SMDs) are attached to the bottom side of a printed circuit board

11、 by passing them through a wave solder (full body immersion) while simultaneously soldering devices with pins on the top of the board (plated through hole attach). As a result, these small SMDs may be exposed to temperatures as high as 265 C during this type of board attach method. If sufficient moi

12、sture exists in the package, exposure to the molten solder causes the moisture to turn to vapor, resulting in increased pressure within the package which in turn may cause quality and/or reliability degradation. The test method in this document will address the issues related to the determination of

13、 the capability of a solid state device to withstand the stresses of full body wave solder immersion and subsequent field use. JEDEC Standard No. 22-A111B Test Method A111B -ii- (Revision of Test Method A111A) JEDEC Standard No. 22-A111B Page 1 Test Method A111B (Revision of Test Method A111A) EVALU

14、ATION PROCEDURE FOR DETERMINING CAPABILITY TO BOTTOM SIDE BOARD ATTACH BY FULL BODY SOLDER IMMERSION OF SMALL SURFACE MOUNT SOLID STATE DEVICES (From JEDEC Board Ballot JCB-18-13, formulated under the cognizance of the JC-14.1 Subcommittee on Reliability Test Methods for Packaged Devices.) 1 Scope T

15、his evaluation procedure is written to provide users of ICs of small surface mount packages with a method to evaluate the capability of a device to withstand full wave solder immersion. This document lists procedures for two solder pot, nominal temperatures, 245C and 260C. The 260C condition can cov

16、er both SnPb and Pb-free solders. Typically packages capable of full body solder immersion (wave solder immersion) board attach have a lead pitch greater than 0.5 mm. There is only limited demonstrated capability to survive full body (wave solder) immersion attach for QFPs and packages with bodies l

17、arger than 5.5 mm x 12.5 mm (or die paddle sizes greater than 2.5 mm x 3.5 mm). Devices in packages with limited or no data for capability demonstration should not be wave soldered. The capability of a device for full body immersion is strongly affected by its package structure. Devices with large b

18、ody packages may have reliability and/or quality problems induced by such a board attach method. Die and paddle sizes, as well as wavesolder conditions (board size, package profile, speed, part density, etc.), are some of the factors that modulate quality and reliability problems. Package styles wit

19、h bottom terminations, such as Ball Grid Array (BGA), Land Grid Array (LGA), and Quad/Dual Flatpack No lead (QFN/DFN) are not suitable for full body solder immersion board attach. If wave solder immersion results in a different Moisture Sensitivity Level than the J-STD-020 solder reflow level specif

20、ied by the supplier, the user must take appropriate precautions to ensure that the new floor life is not exceeded during the users manufacturing processes. The purpose of this test method is to identify the potential wave solder classification level of small plastic Surface Mount Devices (SMDs) that

21、 are sensitive to moisture-induced stress so that they can be properly packaged, stored, and handled per J-STD-033 to avoid subsequent mechanical damage during the assembly wave solder attachment and/or repair operations. This test method also provides a reliability preconditioning sequence for smal

22、l SMDs that are wave soldered using full body immersion. This test method, may be used by users to determine what classification level should be used for initial board level reliability qualification. 2 Applicable documents JESD22-A113, Preconditioning Procedures of Plastic Surface Mount Devices Pri

23、or to Reliability Testing JESD47, Stress Test Driven Qualification Specification JESD625, Requirements for handling Electrostatic Discharge Sensitive (ESD) Devices J-STD-020, Moisture/Reflow Sensitivity Classification for Non-Hermetic Solid State Surface Devices J-STD-033, Standard for Handling, Pac

24、king, Shipping and Use of Moisture/Reflow Sensitive Surface Mount Devices J-STD-035, Acoustic Microscopy for Non-Hermetic Encapsulated Electronic Components JEDEC Standard No. 22-A111B Page 2 Test Method A111B (Revision of Test Method A111A) 3 Apparatus 3.1 Bake oven Ovens capable of operating at 12

25、5 C +5/-0 C, for use in drying(baking) the SMDs. 3.2 Temperature humidity chambers Moisture chamber(s), capable of operating at 85 C/85% RH, 85 C/60% RH, 60 C/60% RH, and 30 C/60% RH. Within the chamber working area, temperature tolerance must be 2 C and the RH tolerance must be 3%. 3.3 Wave solder

26、equipment Wave solder equipment with preheat; capable of up to 260 C (+5/-0 C) solder temperature. The equipment shall be capable of maintaining this temperature within the flowing solder wave, which is at the location where the body of the device under test contacts the solder. 3.4 Solder dip machi

27、ne The solder pot in the solder dip machine shall be capable of up to 260 C (+5/-0 C) solder temperature for full body immersion evaluation. The equipment shall be capable of maintaining this temperature at the location where the body of the device under test contacts the solder. If a mechanical dip

28、ping apparatus is used, it shall be capable of controlling the rates of immersion and emersion of the device under test and ensuring the immersion depth and dwell time specified in 5.6.2. 3.5 Optical microscope Optical microscope should be capable of 40x magnification for external visual examination

29、 and 100X magnification for cross-section examination. 3.6 Electrical test equipment Electrical test equipment should be capable of performing at least room temperature DC and functional tests. 3.7 Scanning acoustic microscope Scanning acoustic microscope should be capable of C-Mode and Through Tran

30、smission mode and capable of measuring a minimum delamination of 5% of the area being evaluated. NOTE 1 The scanning acoustic microscope is used to detect cracking and delamination. However, the presence of delamination does not necessarily indicate a pending reliability problem. The reliability imp

31、act of delamination must be established for a particular die/package system. NOTE 2 Refer to IPC/JEDEC J-STD-035 for operation of the scanning acoustic microscope. JEDEC Standard No. 22-A111B Page 3 Test Method A111B (Revision of Test Method A111A) 4 Classification This test method provides four pos

32、sible classifications with two solder temperature classifications (245 C and 260 C) and two dip conditions (single dip and dual dip). The test conditions must be reported with the classification results. Two types of solder procedures are allowed, wave solder and manual dip soldering. Table 1 Wave s

33、older simulation conditions Test conditions Reflow method Wave solder Solder dip Preheat Temperature (device body temperature) 25 to 140 C 145 C Preheat Time 80 seconds min 40 seconds min Ramp-up Rate (preheat only) 3 C/second max 3 C/second max Solder Temperature (wave or pot) 245 C Classification

34、(SnPb solder) 245C +5/-0 C 245C +5/-0 C 260 C Classification (SnPb and Pb-free solder) 260C +5/-0 C 260C +5/-0 C Solder Immersion Time Single Wave Simulation 5 +2/-01 seconds 5 +2/-0 seconds Extended Single Wave Simulation 10 +2/-0 seconds 10 +2/-0 seconds Preheat Temperature Dual Wave Simulation Fi

35、rst Wave + Second Wave = 10 +2/-0 seconds 10 +2/-0 seconds Ramp-down Rate 6 C/second max 6 C/second max NOTE Bottom side board attach of small surface mount devices by full immersion in wave solder requires special evaluation of the packages. The profile elements such as preheat, dwell and peak temp

36、eratures vary from process to process. Yet the ability of small packages to be exposed to such treatment depends on these parameters. Assessment by dipping in a solder pot usually exposes devices to higher stresses than the wave solder procedure, which results in induced failures. In summation packa

37、ges that would be attached by wave solder immersion require special evaluations by the USER due to the wave solder process differences. Figure 1 Classification profile for solder dip JEDEC Standard No. 22-A111B Page 4 Test Method A111B (Revision of Test Method A111A) 4 Classification (contd) Figure

38、2 Classification profile for single wave Figure 3 Classification profile for dual wave JEDEC Standard No. 22-A111B Page 5 Test Method A111B (Revision of Test Method A111A) 5 Moisture classification procedure 5.1 Requirements for floor life The recommended soak condition and soak time for determining

39、 the desired floor life is shown in Table 2. 5.1.1 Sample requirements Select a minimum sample of 22 units for each moisture sensitivity level to be tested. Sample groups may be run concurrently on one or more moisture sensitivity levels. Table 2 Moisture sensitivity levelsLEVEL FLOOR LIFE4SOAK REQU

40、IREMENTS STANDARD ACCELERATED EQUIVALENT1eV 0.40-0.48eV 0.30-0.39 TIME CONDITION TIME (hours)CONDITION TIME (hours)TIME (hours) CONDITION 1 Unlimited 30C/85% RH 168 +5/-0 85C/85% RH NA NA NA 2 1 year 30C/60% RH 168 +5/-0 85C/60% RH NA NA NA 2a 4 weeks 30C/60% RH 6962 +5/-0 30C/60% RH 120 +1/-0 168 +

41、1/-0 60C/60% RH 3 168 hours 30C/60% RH 1922 +5/-0 30C/60% RH 40 +1/-0 52 +1/-0 60C/60% RH 4 72 hours 30C/60% RH 962 +2/-0 30C/60% RH 20 +0.5/-0 24 +0.5/-0 60C/60% RH 5 48 hours 30C/60% RH 722 +2/-0 30C/60% RH 15 +0.5/-0 20 +0.5/-0 60C/60% RH 5a 24 hours 30C/60% RH 482+2/-0 30C/60% RH 10 +0.5/-0 13 +

42、0.5/-0 60C/60% RH 6 Time on Label (TOL) 30C/60% RH TOL 30C/60% RH NA NA NA NOTE 1 CAUTION To use the “accelerated equivalent” soak conditions, correlation of damage response (including electrical, after soak and reflow), should be established with the “standard” soak conditions. Alternatively, if th

43、e known activation energy (eV) for moisture diffusion of the package materials is in the range of 0.40 - 0.48 eV or 0.30 0.39 eV, the “accelerated equivalent” may be used. Accelerated soak times may vary due to material properties (e.g., mold compound, encapsulant, etc.). JEDEC document JESD22-A120

44、provides a method for determining the eV. NOTE 2 The standard soak time includes a default value of 24 hours for semiconductor manufacturers exposure time (MET) between bake and bag and includes the maximum time allowed out of the bag at the distributors facility. If the actual MET is less than 24 h

45、ours, the soak time may be reduced. For soak conditions of 30C/60% RH, the soak time is reduced by 1 hour for each hour the MET is less than 24 hours. For soak conditions of 60C/60% RH, the soak time is reduced by 1 hour for every 5 hours the MET is less than 24 hours. If the actual MET is greater t

46、han 24 hours, the soak time must be increased. If soak conditions are 30C/60% RH, the soak time is increased 1 hour for each hour that the actual MET exceeds 24 hours. If soak conditions are 60C/60% RH, the soak time is increased 1 hour for every 5 hours that the actual MET exceeds 24 hours. NOTE 3

47、Supplier may extend the soak times at their own risk. NOTE 4 “Floor Life” only relates to moisture/reflow related failures and does not take into consideration other failure mechanisms or “shelf life” issues due to long term storage. NOTE 5 Table 5-1 accelerated soak requirements may not apply to mo

48、ld compounds that do not contain fillers. JEDEC Standard No. 22-A111B Page 6 Test Method A111B (Revision of Test Method A111A) 5.2 Initial electrical test Test appropriate electrical parameters (e.g., Data sheet values, in house specifications, etc.). Replace any devices that fail to meet tested par

49、ameters. 5.3 Initial inspection Perform an initial external visual and scanning acoustic microscope examination to establish a baseline for the cracking/delamination criteria in 6.3.1. NOTE This standard does not consider or establish any time zero requirements for delamination. 5.4 Bake requirements Bake the sample for 24 hours minimum at 125 +5/-0 C. This step is intended to remove moisture from the package so that it will be “dry.“ NOTE This time/temperature may be modified if desorption data on the par