JEDEC JESD209-4B-2017 Low Power Double Date Rate 4 (LPDDR4).pdf

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1、JEDEC STANDARD Low Power Double Date Rate 4 (LPDDR4) JESD209-4B (Revision of JESD209-4A, November 2015) FEBRUARY 2017 JEDEC SOLID STATE TECHNOLOGY ASSOCIATION NOTICE JEDEC standards and publications contain material that has been prepared, reviewed, and approved through the JEDEC Board of Directors

2、level and subsequently reviewed and approved by the JEDEC legal counsel. JEDEC standards and publications are designed to serve the public interest through eliminating misunderstandings between manufacturers and purchasers, facilitating interchangeability and improvement of products, and assisting t

3、he purchaser in selecting and obtaining with minimum delay the proper product for use by those other than JEDEC members, whether the standard is to be used either domestically or internationally. JEDEC standards and publications are adopted without regard to whether or not their adoption may involve

4、 patents or articles, materials, or processes. By such action JEDEC does not assume any liability to any patent owner, nor does it assume any obligation whatever to parties adopting the JEDEC standards or publications. The information included in JEDEC standards and publications represents a sound a

5、pproach to product specification and application, principally from the solid state device manufacturer viewpoint. Within the JEDEC organization there are procedures whereby a JEDEC standard or publication may be further processed and ultimately become an ANSI standard. No claims to be in conformance

6、 with this standard may be made unless all requirements stated in the standard are met. Inquiries, comments, and suggestions relative to the content of this JEDEC standard or publication should be addressed to JEDEC at the address below, or refer to www.jedec.org under Standards and Documents for al

7、ternative contact information. Published by JEDEC Solid State Technology Association 2017 3103 North 10th Street Suite 240 South Arlington, VA 22201-2107 This document may be downloaded free of charge; however JEDEC retains the copyright on this material. By downloading this file the individual agre

8、es not to charge for or resell the resulting material. PRICE: Contact JEDEC Printed in the U.S.A. All rights reserved PLEASE! DONT VIOLATE THE LAW! This document is copyrighted by JEDEC and may not be reproduced without permission. For information, contact: JEDEC Solid State Technology Association 3

9、103 North 10th Street Suite 240 South Arlington, VA 22201-2107 or refer to www.jedec.org under Standards-Documents/Copyright Information. JEDEC Standard No. 209-4BPage 1LOW POWER DOUBLE DATA RATE (LPDDR) 4From JEDEC Board Ballot JCB-16-51, formulated under the cognizance of the JC-42.6 Subcommittee

10、on Low Power Memories.)1 ScopeThis document defines the LPDDR4 standard, including features, functionalities, AC and DC characteristics, packages, and ball/signal assignments. The purpose of this specification is to define the minimum set of requirements for a JEDEC compliant 16 bit per channel SDRA

11、M device with either one or two channels. LPDDR4 dual channel device density ranges from 4 Gb through 32 Gb and single channel density ranges from 2 Gb through 16 Gb. This document was created using aspects of the following standards: DDR2 (JESD79-2), DDR3 (JESD79-3), DDR4 (JESD79-4), LPDDR (JESD209

12、), LPDDR2 (JESD209-2) and LPDDR3 (JESD209-3).Each aspect of the standard was considered and approved by committee ballot(s). The accumulation of these ballots was then incorporated to prepare the LPDDR4 standard.JEDEC Standard No. 209-4BPage 22 Package ballout and Pin definition2.1 Pad Order 2.1.1 P

13、ad Order for dual channelNOTE 1 Applications are recommended to follow bit/byte assignments. Bit or Byte swapping at the application level requires review of MR and calibration features assigned to specific data bits/bytes.NOTE 2 Additional pads are allowed for DRAM mfg-specific pads (“DNU”), or add

14、itional power pads as long as the extra pads are grouped with like-named pads.Ch. A Top Ch. B Top1 VDD2 41 VDD2 101 VDD2 141 VDD22 VSS 42 CKE_A 102 VSS 142 CKE_B3 VDD1 43 CS_A 103 VDD1 143 CS_B4 VDD2 44 VSS 104 VDD2 144 VSS5 VSS 45 CA1_A 105 VSS 145 CA1_B6 VSSQ 46 CA0_A 106 VSSQ 146 CA0_B7 DQ8_A 47

15、VDD2 107 DQ8_B 147 VDD28 VDDQ 48 ODT(ca)_A 108 VDDQ 148 ODT(ca)_B9 DQ9_A 49 VSS 109 DQ9_B 149 VSS10 VSSQ 50 VDD1 110 VSSQ 150 VDD111 DQ10_A 51 VSSQ 111 DQ10_B 151 VSSQ12 VDDQ 52 DQ7_A 112 VDDQ 152 DQ7_B13 DQ11_A 53 VDDQ 113 DQ11_B 153 VDDQ14 VSSQ 54 DQ6_A 114 VSSQ 154 DQ6_B15 DQS1_t_A 55 VSSQ 115 DQ

16、S1_t_B 155 VSSQ16 DQS1_c_A 56 DQ5_A 116 DQS1_c_B 156 DQ5_B17 VDDQ 57 VDDQ 117 VDDQ 157 VDDQ18 DMI1_A 58 DQ4_A 118 DMI1_B 158 DQ4_B19 VSSQ 59 VSSQ 119 VSSQ 159 VSSQ20 DQ12_A 60 DMI0_A 120 DQ12_B 160 DMI0_B21 VDDQ 61 VDDQ 121 VDDQ 161 VDDQ22 DQ13_A 62 DQS0_c_A 122 DQ13_B 162 DQS0_c_B23 VSSQ 63 DQS0_t_

17、A 123 VSSQ 163 DQS0_t_B24 DQ14_A 64 VSSQ 124 DQ14_B 164 VSSQ25 VDDQ 65 DQ3_A 125 VDDQ 165 DQ3_B26 DQ15_A 66 VDDQ 126 DQ15_B 166 VDDQ27 VSSQ 67 DQ2_A 127 VSSQ 167 DQ2_B28 ZQ 68 VSSQ 128 RESET_n 168 VSSQ29 VDDQ 69 DQ1_A 129 VDDQ 169 DQ1_B30 VDD2 70 VDDQ 130 VDD2 170 VDDQ31 VDD1 71 DQ0_A 131 VDD1 171 D

18、Q0_B32 VSS 72 VSSQ 132 VSS 172 VSSQ33 CA5_A 73 VSS 133 CA5_B 173 VSS34 CA4_A 74 VDD2 134 CA4_B 174 VDD235 VDD2 75 VDD1 135 VDD2 175 VDD136 CA3_A 76 VSS 136 CA3_B 176 VSS37 CA2_A 77 VDD2 137 CA2_B 177 VDD238 VSS Ch. A Bottom 138 VSS Ch. B Bottom39 CK_c_A 139 CK_c_B40 CK_t_A 140 CK_t_BJEDEC Standard N

19、o. 209-4BPage 32.1 Pad Order (contd)2.1.2 Pad Order for single channelNOTE 1 Applications are recommended to follow bit/byte assignments. Bit or Byte swapping at the application level requires review of MR and calibration features assigned to specific data bits/bytes.NOTE 2 Additional pads are allow

20、ed for DRAM mfg-specific pads (“DNU”), or additional power pads as long as the extra pads are grouped with like-named pads.NOTE 3 A RESET_n pad is added. The RESET_n pad location is vendor specific. See vendor device datasheets for details about RESET_n pad location.TOP1 VDD2 40 CK_c2 VSS 41 CK_t3 V

21、DD1 42 VDD24 VDD2 43 CKE5 VSS 44 CS6 VSSQ 45 VSS7DQ8 46 CA18 VDDQ 47 CA09DQ9 48 VDD210 VSSQ 49 ODT(ca)11 DQ10 50 VSS12 VDDQ 51 VDD113 DQ11 52 VSSQ14 VSSQ 53 DQ715 DQS1_t 54 VDDQ16 DQS1_c 55 DQ617 VDDQ 56 VSSQ18 DMI1 57 DQ519 VSSQ 58 VDDQ20 DQ12 59 DQ421 VDDQ 60 VSSQ22 DQ13 61 DMI023 VSSQ 62 VDDQ24 D

22、Q14 63 DQS0_c25 VDDQ 64 DQS0_t26 DQ15 65 VSSQ27 VSSQ 66 DQ328 ZQ 67 VDDQ29 VDDQ 68 DQ230 VDD2 69 VSSQ31 RESET_n 70 DQ132 VDD1 71 VDDQ33 VSS 72 DQ034 CA5 73 VSSQ35 CA4 74 VSS36 VDD2 75 VDD237 CA3 76 VDD138 CA2 77 VSS39 VSS 78 VDD2BottomJEDEC StandardNo. 209-4BPage 42.2 Package Ballout2.2.1 272 ball 1

23、5 mm x 15 mm 0.4 mm pitch, Quad-Channel POP FBGA (top view) Using Variation VFFCDB for MO-2731 2 3456 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36ADNU VSS VDD1 CA4_a VDDQ ZQ1_a VDDQ DQ15_a VDD2 DQ13_a VDD2 DMI1_a VDDQ DQS1_c_a VDDQ DQ10_a VSS DQ8_a DQ0_c VDD

24、1 DQ2_c VDDQ DQS0_c_c VDDQ DQ4_c VDD2 DQ5_c VDD2 DQ7_c VDDQ CA0_c VDDQ CS1_c VDD1 VSS DNUBVSS VDD2 CA3_a VSS CA5_a VSS ZQ0_a VSS DQ14_a VSS DQ12_a VSS DQS1_t_a VSS DQ11_a VSS DQ9_a VDD2 VSS DQ1_c VSS DQ3_c VSS DQS0_t_c VSS DMI0_c VSS DQ6_c VSS ODTca_c VSS CA1_c VSS CS0_c VDD2 VSSCCA2_a CK_c_a CKE0_c

25、 CKE1_cDVDD2 CK_t_a CK_t_c VDD2ECKE0_a VSS VSS CK_c_cFCKE1_a CS0_a CA2_c CA3_cGVDD2 CS1_aVDD1CA4_c VDD2HCA1_a VSSVDD2VSS CA5_cJCA0_a ODTca_aVDDQZQ0_c ZQ1_cKVDDQ DQ7_aVSSDQ15_c VDDQLDQ6_a VSSCK_t, CK_cVSS DQ14_cMDQ5_a DQ4_aDMIDQ12_c DQ13_cNVDDQ DMI0_a DQ, CA, CS, DMI1_c VDDQPDQS0_c_a VSSDNU, NCVSS DQ

26、S1_c_cRDQ3_a DQS0_t_aDQS_t, DQS_cDQS1_t_c DQ11_cTVDDQ DQ2_a RESET_n, ZQ, DQ10_c VDDQUDQ1_a VSS VSS DQ9_cVVDD1 DQ0_a DQ8_c VDD1WDQ0_b VDD2 VDD2 DQ8_dYDQ1_b VSS VSS DQ9_dAAVDDQ DQ2_b DQ10_d VDDQABDQ3_b DQS0_t_b DQS1_t_d DQ11_dACDQS0_c_b VSS VSS DQS1_c_dADVDDQ DMI0_b DMI1_d VDDQAEDQ5_b DQ4_b DQ12_d DQ1

27、3_dAFDQ6_b VSS VSS DQ14_dAGVDDQ DQ7_b DQ15_d VDDQAHCA0_b ODTca_b NC NCAJCA1_b VSS VSS CA5_dAKVDD2 CS1_b CA4_d VDD2ALCKE1_b CS0_b CA2_d CA3_dAMCKE0_b VSS VSS CK_c_dANVDD2 CK_t_b CK_t_d VDD2APCA2_b CK_c_b CKE0_d CKE1_dARVSS VDD2 CA3_b VSS CA5_b VSS RESET_n VSS DQ14_b VSS DMI1_b VSS DQS1_t_b VSS DQ11_b

28、 VSS DQ9_b VDD2 VSS DQ1_d VSS DQ3_d VSS DQS0_t_d VSS DQ4_d VSS DQ6_d VSS ODTca_d VSS CA1_d VSS CS0_d VDD2 VSSATDNU VSS VDD1 CA4_b VDDQ NC VDDQ DQ15_b VDD2 DQ13_b VDD2 DQ12_b VDDQ DQS1_c_b VDDQ DQ10_b VSS DQ8_b DQ0_d VDD1 DQ2_d VDDQ DQS0_c_d VDDQ DMI0_d VDD2 DQ5_d VDD2 DQ7_d VDDQ CA0_d VDDQ CS1_d VDD

29、1 VSS DNUNOTE 1 15 mm x 15 mm, 0.4 mm pitch.NOTE 2 272 ball count, 36 rows.NOTE 3 Top View, A1 in top left corner.NOTE 4 ODT(ca)_x balls are wired to ODT(ca)_x pads of Rank 0 DRAM die. ODT(ca)_x pads for other ranks (if present) are disabled in the package.NOTE 5 Package Channel a and Channel c shal

30、l be assigned to die Channel A of different DRAM die.NOTE 6 Die pad VSS and VSSQ signals are combined to VSS package balls.NOTE 7 Package requires dual channel die or functional equivalent of single channel die-stack.JEDEC Standard No. 209-4BPage52.2.2 LPDDR4 34x34 Quad x16 Channel (Fits 14x14 0.4 m

31、m pitch) - Using MO-317A123 45678910112131415161718192021223242526272829303132334A NC VDD2 DQ3_A VSS DQ5_A ODT(ca)_A CA0_A CS1_A CKE1_A CA2_A VSS VSS DQ13_A VDD2 VDD1 DQ10_A ZQ1_A ZQ1_D DQ10_C VDD1 VDD2 DQ13_C VSS VSS CA2_C CKE1_C CS1_C CA0_C ODT(ca)_C DQ5_C VSS DQ3_C VDD2 NC AB VSS DQ2_A VDDQ DMI0_

32、A VDDQ DQ7_A VDD2 CS0_A CKE0_A VDD2 CA4_A DQ15_A VDDQ DMI1_A DQ11_A VSS ZQ0_A ZQ0_D VSS DQ11_C DMI1_C VDDQ DQ15_C CA4_C VDD2 CKE0_C CS0_C VDD2 DQ7_C VDDQ DMI0_C VDDQ DQ2_C VSS BC DQ0_A VDDQ VSS VSS DQ4_A VDDQ CA1_A VDD2 VSS CA3_A VSS VDDQ DQ12_A VSS VDDQ DQ9_A RESET_n RFU DQ9_C VDDQ VSS DQ12_C VDDQ

33、VSS CA3_C VSS VDD2 CA1_C VDDQ DQ4_C VSS VSS VDDQ DQ0_C CD VDD1 DQ1_A DQS0_t_A DQS0_c_A VSS DQ6_A VSS CK_t_A CK_c_A VSS CA5_A DQ14_A VSS DQS1_c_A DQS1_t_A VDDQ DQ8_A DQ8_C VDDQ DQS1_t_C DQS1_c_C VSS DQ14_C CA5_C VSS CK_c_C CK_t_C VSS DQ6_C VSS DQS0_c_C DQS0_t_C DQ1_C VDD1 DE VDD2 VSS VSS VDD2 EF VDD2

34、 VDD2 VDD2 VDD2 FG VSS VSS VSS VSS GH RFU RFU RFU RFU HJ RFU RFU RFU RFU JK RFU RFU RFU RFU KL RFU RFU RFU RFU LM RFU RFU RFU RFU MN RFU RFU RFU RFU NP RFU RFU RFU RFU PR RFU RFU RFU RFU RT RFU RFU RFU RFU TU RFU RFU RFU RFU UV RFU RFU RFU RFU VW RFU RFU RFU RFU WY RFU RFU RFU RFU YAA RFU RFU RFU RF

35、U AAAB RFU RFU RFU RFU ABAC RFU RFU RFU RFU ACAD RFU RFU RFU RFU ADAE RFU RFU RFU RFU AEAF RFU RFU RFU RFU AFAG RFU RFU RFU RFU AGAH VSS VSS VSS VSS AHAJ VDD2 VDD2 VDD2 VDD2 AJAK VDD2 VSS VSS VDD2 AKAL VDD1 DQ1_B DQS0_t_B DQS0_c_B VSS DQ6_B VSS CK_t_B CK_c_B VSS CA5_B DQ14_B VSS DQS1_c_B DQS1_t_B VD

36、DQ DQ8_B DQ8_D VDDQ DQS1_t_D DQS1_c_D VSS DQ14_D CA5_D VSS CK_c_D CK_t_D VSS DQ6_D VSS DQS0_c_D DQS0_t_D DQ1_D VDD1 ALAM DQ0_B VDDQ VSS VSS DQ4_B VDDQ CA1_B VDD2 VSS CA3_B VSS VDDQ DQ12_B VSS VDDQ DQ9_B VDD2 VDD2 DQ9_D VDDQ VSS DQ12_D VDDQ VSS CA3_D VSS VDD2 CA1_D VDDQ DQ4_D VSS VSS VDDQ DQ0_D AMAN

37、VSS DQ2_B VDDQ DMI0_B VDDQ DQ7_B VDD2 CS0_B CKE0_B VDD2 CA4_B DQ15_B VDDQ DMI1_B DQ11_B VSS RFU RFU VSS DQ11_D DMI1_D VDDQ DQ15_D CA4_D VDD2 CKE0_D CS0_D VDD2 DQ7_D VDDQ DMI0_D VDDQ DQ2_D VSS ANAP NC VDD2 DQ3_B VSS DQ5_BODT(ca)_BCA0_B CS1_B CKE1_B CA2_B VSS VSS DQ13_B VDD2 VDD1 DQ10_B RFU RFU DQ10_D

38、 VDD1 VDD2 DQ13_D VSS VSS CA2_D CKE1_D CS1_D CA0_DODT(ca)_DDQ5_D VSS DQ3_D VDD2 NC AP123 45678910112131415161718192021223242526272829303132334NOTE 1 14 mm x 14 mm, 0.4 mm pitch.NOTE 2 376 ball count, 34 rows.NOTE 3 Top View, A1 in top left corner.NOTE 4 ODT(ca)_x balls are wired to ODT(ca)_x pads of

39、 Rank 0 DRAM die. ODT(ca)_x pads for other ranks (if present) are disabled in the package.NOTE 5 Package Channel a and Channel d shall be assigned to die Channel A of different LPDDR4 die.NOTE 6 DRAM die pad VSS and VSSQ signals are combined to VSS package balls.NOTE 7 Package requires dual channel

40、die or functional equivalent of single channel die-stack.JEDEC Standard No. 209-4BPage 62.2.3 144 ball ePoP MCP One-Channel FBGA (top view) using MO-323ANOTE 1 0.4 mm pitch, 2 rows.NOTE 2 Top View, A1 in top left corner.NOTE 3 Body size: 8 mm x 9.5 mmNOTE 4 ODT(ca)_A balls are wired to ODT(ca)_A pad

41、s of Rank 0 DRAM die. ODT(ca) pads for other ranks (if present) are disabled in the package.NOTE 5 DRAM die pad VSS and VSSQ signals are combined to VSS package balls.NOTE 6 The flash ball-out supports eMMC 5.xNOTE 7 Vendor specific function (VSF) - this terminal should not have any external electri

42、cal connections, but it may have an internal connection. The terminal may be routed to provide accessibility and may be used for general purpose vendor specific operations.1 2 3 4 567 8 9 1011121314 15161718 19A DNU VSSm VSSm VCCQm VSSm VSSm DAT5m VCCQm DAT0m CLKm VCCm DAT6m VCCQm DAT7m VCCQm VSSm R

43、STm VSSm DNUeMMCVCCmB VSSm VSSm VCCm VSSm VDDI VCCm DAT1m DAT4m VSSm VCCQm VSSm DAT2m DAT3m VSSm DSm VSSm CMDm VCCm VSSm VCCQmC VSSm VCCm VSSm VSSm VSSmD VSF1 VSF3 VSF5 VSF8E VSF2 VSF4 VSF6 VSF9F RESET_n VSS VSF7 RFUDRAMVDDQG ZQ1_A ZQ0_A RFU RFU VDD1H VSS VSS VSS VSS VDD2J VDD1 VDD1 VDD1 VDD1 VSSK V

44、DD2 VDD2 VDD2 VDD2L VSS VDDQ VDDQ VSSM DQ8_A DQ9_A DQ1_A DQ0_AN VDD2 DQ10_A DQ2_A VDD2P DQ11_A VSS VSS DQ3_AR DQS1_t_A DQS1_c_A DQS0_c_A DQS0_t_AT VSS VDDQ VDDQ VSSU DM1_A VSS VSS DM0_AV VDD2 VDDQ VDDQ VDD2W DQ12_A DQ13_A DQ5_A DQ4_AY VSS VDD2 DQ14_A VDD1 CA5_A VSS CA2_A VDD2 CK_c_A VSS CKE0_A CS0_A

45、 CA1_A VDD2 VSS DQ7_A DQ6_A VDD2 VSSAA DNU VSS VDDQ DQ15_A VDD2 CA4_A CA3_A VSS CK_t_A CKE1_A CS1_A VSS CA0_A ODT(ca)_A VDD1 VDDQ VSS VSS DNUeMCP 144FBGA19x21JEDEC Standard No. 209-4BPage 72.2.4 200 ball x32 Discrete Package, 0.80 mm x 0.65 mm using MO-311NOTE 1 0.8 mm pitch (X-axis), 0.65 mm pitch

46、(Y-axis), 22 rows.NOTE 2 Top View, A1 in top left corner.NOTE 3 ODT(ca)_x balls are wired to ODT(ca)_x pads of Rank 0 DRAM die. ODT(ca)_x pads for other ranks (if present) are dis-abled in the package.NOTE 4 ZQ2, CKE2_A, CKE2_B, CS2_A, and CS2_B balls are reserved for 3-rank package. For 1-rank and

47、2-rank package those balls are NC.NOTE 5 Die pad VSS and VSSQ signals are combined to VSS package balls.NOTE 6 Package requires dual channel die or functional equivalent of single channel die-stack.0.80 mm Pitch12345678910112A DNU DNU VSS VDD2 ZQ0 ZQ1 VDD2 VSS DNU DNUB DNU DQ0_A VDDQ DQ7_A VDDQ VDDQ

48、 DQ15_A VDDQ DQ8_A DNUC VSS DQ1_A DMI0_A DQ6_A VSS VSS DQ14_A DMI1_A DQ9_A VSSD VDDQ VSS DQS0_t_A VSS VDDQ VDDQ VSS DQS1_t_A VSS VDDQE VSS DQ2_A DQS0_c_A DQ5_A VSS VSS DQ13_A DQS1_c_A DQ10_A VSSF VDD1 DQ3_A VDDQ DQ4_A VDD2 VDD2 DQ12_A VDDQ DQ11_A VDD1G VSS ODT(ca)_A VSS VDD1 VSS VSS VDD1 VSS ZQ2 VSS

49、0.65mm PitchH VDD2 CA0_A CS1_A CS0_A VDD2 VDD2 CA2_A CA3_A CA4_A VDD2J VSS CA1_A VSS CKE0_A CKE1_A CK_t_A CK_c_A VSS CA5_A VSSK VDD2 VSS VDD2 VSS CS2_A CKE2_A VSS VDD2 VSS VDD2LMN VDD2 VSS VDD2 VSS CS2_B CKE2_B VSS VDD2 VSS VDD2P VSS CA1_B VSS CKE0_B CKE1_B CK_t_B CK_c_B VSS CA5_B VSSR VDD2 CA0_B CS1_B CS0_B VDD2 VDD2 CA2_B CA3_B CA4_B VDD2T VSS ODT(ca)_B VSS VDD1 VSS VSS VDD1 VSS RESET_n VSSU VDD1 DQ3_B VDDQ DQ4_B VDD2 VDD2 DQ12_B VDDQ DQ11_B VDD1V VSS DQ2_B DQS0_c_B DQ5_B VSS VSS DQ13_B DQS1_c_B DQ10_B VSSW VDDQ VSS DQS0_t_B VSS VDDQ VDDQ VSS DQS1_t_B VSS VDDQY