JEDEC JESD208-2007 SPECIALITY DDR2-1066 SDRAM.pdf

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1、JEDEC SOLID STATE TECHNOLOGY ASSOCIATIONJESD208NOVEMBER 2007JEDECSTANDARDSPECIALITY DDR2-1066 SDRAMNOTICE JEDEC standards and publications contain material that has been prepared, reviewed, and approved through the JEDEC Board of Directors level and subsequently reviewed and approved by the JEDEC le

2、gal counsel. JEDEC standards and publications are designed to serve the public interest through eliminating misunderstandings between manufacturers and purchasers, facilitating interchangeability and improvement of products, and assisting the purchaser in selecting and obtaining with minimum delay t

3、he proper product for use by those other than JEDEC members, whether the standard is to be used either domestically or internationally. JEDEC standards and publications are adopted without regard to whether or not their adoption may involve patents or articles, materials, or processes. By such actio

4、n JEDEC does not assume any liability to any patent owner, nor does it assume any obligation whatever to parties adopting the JEDEC standards or publications. The information included in JEDEC standards and publications represents a sound approach to product specification and application, principall

5、y from the solid state device manufacturer viewpoint. Within the JEDEC organization there are procedures whereby a JEDEC standard or publication may be further processed and ultimately become an ANSI standard. No claims to be in conformance with this standard may be made unless all requirements stat

6、ed in the standard are met. Inquiries, comments, and suggestions relative to the content of this JEDEC standard or publication should be addressed to JEDEC at the address below, or call (703) 907-7559 or www.jedec.org Published by JEDEC Solid State Technology Association 2007 2500 Wilson Boulevard A

7、rlington, VA 22201-3834 This document may be downloaded free of charge; however JEDEC retains the copyright on this material. By downloading this file the individual agrees not to charge for or resell the resulting material. PRICE: Please refer to the current Catalog of JEDEC Engineering Standards a

8、nd Publications online at http:/www.jedec.org/Catalog/catalog.cfm Printed in the U.S.A. All rights reserved PLEASE! DONT VIOLATE THE LAW! This document is copyrighted by JEDEC and may not be reproduced without permission. Organizations may obtain permission to reproduce a limited number of copies th

9、rough entering into a license agreement. For information, contact: JEDEC Solid State Technology Association 2500 Wilson Boulevard Arlington, Virginia 22201-3834 or call (703) 907-7559 JEDEC Standard No. 208Page 1SPECIALITY DDR2-1600 SDRAM(From JEDEC Board Ballot JCB-07-64, JCB-07-69, and JCB-07-98,

10、formulated under the cognizance of the JC-42.3 Subcommittee on RAM Memories.)ScopeThis document defines the Specialty DDR2-1066 SDRAM specification, including features, functionalities, AC and DC characteristics, packages, and ball/signal assignments. The purpose of this Specification is to define t

11、he minimum set of requirements for JEDEC compliant 256 Mb through 4 Gb for x4, x8, and x16 Specialty DDR2-1066 SDRAM devices. This specification was created based on the DDR2 specification (JESD79-2) and some aspects of the DDR specification (JESD79). Each aspect of the changes for Specialty DDR2-10

12、66 SDRAM operation were considered and balloted. The accumulation of these ballots were then incorporated to prepare this JESD208 specification, replacing whole sections and incorporating the changes into Functional Description and Operation.JEDEC Standard No. 208Page 21 Package ballout UDQS corresp

13、onds to the data on DQ8-DQ15. For the x8, an RDQS option using DM pin can be enabled via the EMR(1) to simplify read timing. The data strobes DQS, LDQS, UDQS, and RDQS may be used in single ended mode or paired with optional complementary signals DQS, LDQS, UDQS, and RDQS to provide differen-tial pa

14、ir signaling to the system during both reads and writes. A control bit at EMR(1)A10 enables or disables all complementary data strobe signals.In this data sheet, “differential DQS signals“ refers to any of the following with EMR(1)A10 = 0x4 DQS/DQSx8 DQS/DQS if EMR(1)A11 = 0x8 DQS/DQS, RDQS/RDQS, if

15、 EMR(1)A11 = 1x16 LDQS/LDQS and UDQS/UDQS “single-ended DQS signals“ refers to any of the following with EMR(1)A10 = 1x4 DQSx8 DQS if EMR(1)A11 = 0x8 DQS, RDQS, if EMR(1)A11 = 1x16 LDQS and UDQSNC No Connect: No internal electrical connection is present.VDDQSupply DQ Power Supply: 1.8 V +/- 0.1 VVSS

16、QSupply DQ GroundVDDLSupply DLL Power Supply: 1.8 V +/- 0.1 V1 Package ballout accesses start at a selected location and continue for a burst length of four or eight in a programmed sequence. Accesses begin with the registration of an Active command, which is then followed by a Read or Write command

17、. The address bits registered coincident with the active command are used to select the bank and row to be accessed (BA0-BA2 select the bank; A0-A15 select the row). The address bits registered coincident with the Read or Write command are used to select the starting column location for the burst ac

18、cess and to determine if the auto precharge command is to be issued.Prior to normal operation, the DDR2 SDRAM must be initialized. The following sections provide detailed information covering device initialization, register definition, command descriptions and device operation.2.3 Power-up and initi

19、alizationDDR2 SDRAMs must be powered up and initialized in a predefined manner. Operational procedures other than those specified may result in undefined operation.For DDR2 SDRAMs, both bits BA0 and BA1 must be decoded for Mode/Extended Mode Register Set (MRS/EMRS) commands. Users must initialize al

20、l four Mode Registers. The registers may be initialized in any order.2.3.1 Power-up and initialization sequenceThe following sequence is required for Power-up and Initialization.a) Either one of the following sequence is required for Power-up.a1) While applying power, attempt to maintain CKE below 0

21、.2 x VDDQ and ODT*1at a LOW state (all other inputs may be undefined.) The VDD voltage ramp time must be no greater than 200 ms from when VDD ramps from 300 mV to VDD min; and during the VDD voltage ramp, |VDD-VDDQ| 0.3 volts. Once the ramping of the supply voltages is complete (when VDDQ crosses VD

22、DQ min), the supply voltage specifications provided in section 5, Table 16 Recommended DC operating conditions (SSTL_1.8), prevail.- VDD, VDDL and VDDQ are driven from a single power converter output, AND- VTT is limited to 0.95 V max, AND- Vref tracks VDDQ/2, VREF must be within +/- 300 mV with res

23、pect to VDDQ/2 during supply ramp time.- VDDQ VREF must be met at all times.a2) While applying power, attempt to maintain CKE below 0.2 x VDDQ and ODT*1at a LOW state, all other inputs may be undefined, voltage levels at I/Os and outputs must be less than VDDQ during voltage ramp time to avoid DRAM

24、latch-up. During the ramping of the supply voltages, VDD VDDL VDDQ must be maintained and is applicable to both AC and DC levels until the ramping of the supply voltages is complete, which is when VDDQ crosses VDDQ min. Once the ramping of the supply voltages is complete, the supply voltage specific

25、ations provided in section 5, Table 16 Recommended DC operating conditions (SSTL_1.8), prevail.- Apply VDD/VDDL before or at the same time as VDDQ.- VDD/VDDL voltage ramp time must be no greater than 200 ms from when VDD ramps from 300 mV to VDD min- Apply VDDQ before or at the same time as VTT.- Th

26、e VDDQ voltage ramp time from when VDD min is achieved on VDD to when VDDQ min is achieved on VDDQ must be no greater than 500 ms.(Note: While VDD is ramping, current may be supplied from VDD through the DRAM to VDDQ.)- Vref must track VDDQ/2, Vref must be within +/- 300 mv with respect to VDDQ/2 du

27、ring supply ramp time.- VDDQ VREF must be met at all times.- Apply VTT.- The VTT voltage ramp time from when VDDQ min is achieved on VDDQ to when VTT min is achieved on VTT must be no greater than 500 ms.b) Start clock and maintain stable condition.c) For the minimum of 200 us after stable power (VD

28、D, VDDL, VDDQ, VREF and VTT are between their minimum and maximum values as stated in section 5, Table 16 Recommended DC operating conditions (SSTL_1.8) and stable clock (CK, CK), then apply NOP or Deselect maintain setting0 0 1 Drive(1) 0 1 0 Drive(0)100Adjust mode*2111OCD Calibration default *3OCD

29、 program1 DQSRttRtt A1Output Driver Impedance Control0 Full strength1 Reduced strengthA10 DQS 0 Enable1 DisableA11RDQS Enable*50 Disable1 EnableBA10BA1 BA0 MRS mode00 MR01 EMR(1)10 EMR(2)11 EMR(3)BA20*1QoffA12A12Qoff (Optional)*40 Output buffer enabled1 Output buffer disabled A11(RDQS Enable)A10(DQS

30、 Enable)Strobe Function MatrixRDQS/DM RDQS DQS DQS0 (Disable) 0 (Enable) DM Hi-z DQS DQS0 (Disable) 1 (Disable) DM Hi-z DQS Hi-z1 (Enable) 0 (Enable) RDQS RDQS DQS DQS1 (Enable) 1 (Disable) RDQS Hi-z DQS Hi-zNOTE 1 BA2 and A13-A15 are reserved for future use and must be set to 0 when programming the

31、 EMR(1).NOTE 2 When Adjust mode is issued, AL from previously set value must be applied.NOTE 3 After setting to default, OCD calibration mode needs to be exited by setting A9-A7 to 000. Refer to section 2.4.3 for detailed information.NOTE 4 Output disabled - DQs, DQSs, DQSs, RDQS, RDQS. This feature

32、 is used in conjunction with DIMM IDD measurements when IDDQ is not desired to be included.NOTE 5 If RDQS is enabled, the DM function is disabled. RDQS is active for reads and dont care for writes.2.4.2 DDR2 SDRAM extended mode registers (EMR(#) (contd)2.4.2.3 EMR(1) programming (contd)JEDEC Standar

33、d No. 208Page 182.4.2.4 EMR(2)The extended mode register(2) controls refresh related features. The default value of the extended mode register(2) is not defined, therefore the extended mode register(2) must be programmed during initialization for proper operation. The extended mode register(2) is wr

34、itten by asserting LOW on CS, RAS, CAS, WE, HIGH on BA1 and LOW on BA0, while controlling the states of address pins A0 - A15. The DDR2 SDRAM should be in all bank precharge state with CKE already HIGH prior to writing into the extended mode register(2). The mode register set command cycle time (tMR

35、D) must be satisfied to complete the write operation to the extended mode register(2). Mode register contents can be changed using the same command and clock cycle requirements during normal operation as long as all banks are in the precharge state.2.4.2.5 EMR(2) programmingFigure 16 shows the EMR(2

36、) programming.2.4.2 DDR2 SDRAM extended mode registers (EMR(#) (contd)JEDEC Standard No. 208Page 19Figure 16 EMR(2) programmingA7 High Temperature Self-Refresh Rate Enable0 Disable1 Enable (Optional)*2Address FieldExtended Mode Register(2)0*1BA0 A15 A13 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A00BA11BA20

37、*1A120*1SRFA2 A1 A0Partial Array Self Refresh for 4 Banks (Optional)0 0 0 Full array0 0 1 Half Array(BA1:0=00 DQS LOWTestEMRS :Enter Adjust ModeBL=4 code input to all DQsInc, Dec, or NOPEMRS: Drive(0)DQ DQS HIGHTestEMRS :Enter Adjust ModeBL=4 code input to all DQsInc, Dec, or NOPEMRS: OCD calibratio

38、n mode exitEndALL OK ALL OKNeed CalibrationNeed CalibrationEMRS: OCD calibration mode exitEMRS: OCD calibration mode exitEMRS: OCD calibration mode exitEMRS: OCD calibration mode exitEMRS: OCD calibration mode exitAll MR shoud be programmed before entering OCD impedance adjustment and ODT should be

39、carefully controlled depending on system environmentFigure 12 OCD impedance adjustment2.4.2 DDR2 SDRAM extended mode registers (EMR(#) (contd)JEDEC Standard No. 208Page 21characteristics for OCD calibration default are specified in Tables 30 and 31. OCD applies only to normal full strength output dr

40、ive setting defined by EMR(1) and if reduced strength is set, OCD default output driver characteristics are not applicable. When OCD calibration adjust mode is used, OCD default output driver characteristics are not applicable. After OCD calibration is completed or driver strength is set to default,

41、 subsequent EMRS commands not intended to adjust OCD characteristics must specify A9-A7 as 000 in order to maintain the default or calibrated value.2.4.3.2 OCD impedance adjustTo adjust output driver impedance, controllers must issue the ADJUST EMRS command along with a 4bit burst code to DDR2 SDRAM

42、 as in Table 8. For this operation, Burst Length has to be set to BL = 4 via MRS command before activating OCD and controllers must drive this burst code to all DQs at the same time. DT0 in table 8 means all DQ bits at bit time 0, DT1 at bit time 1, and so forth. The driver output impedance is adjus

43、ted for all DDR2 SDRAM DQs simultaneously and after OCD calibration, all DQs and DQSs of a given DDR2 SDRAM will be adjusted to the same driver strength setting. The maximum step count for adjustment is 16 and when the limit is reached, further increment or decrement code has no effect. The default

44、setting may be any step within the 16 step range. When Adjust mode command is issued, AL from previously set value must be applied.For proper operation of adjust mode, WL = RL - 1 = AL + CL - 1 clocks and tDS/tDH should be met as shown in Figure 13. For input data pattern for adjustment, DT0 - DT3 i

45、s a fixed order and is not affected by burst type (i.e. sequential or interleave).Table 7 OCD drive mode programA9 A8 A7 Operation0 0 0 OCD calibration mode exit0 0 1 Drive(1) DQ, DQS, (RDQS) HIGH and DQS LOW0 1 0 Drive(0) DQ, DQS, (RDQS) LOW and DQS HIGH1 0 0 Adjust mode 1 1 1 OCD calibration defau

46、ltTable 8 OCD adjust mode program4bit burst code inputs to all DQs OperationDT0 DT1 DT2 DT3 Pull-up driver strength Pull-down driver strength0000NOP (No operation) NOP (No operation)0 0 0 1 Increase by 1 step NOP0010Decrease by 1 step NOP0100NOP Increase by 1 step1000NOP Decrease by 1 step0101Increa

47、se by 1 step Increase by 1 step0110Decrease by 1 step Increase by 1 step1001Increase by 1 step Decrease by 1 step1010Decrease by 1 step Decrease by 1 stepOther Combinations Reserved 2.4.3 Off-chip driver (OCD) impedance adjustment (contd)2.4.3.1 Extended mode register for OCD impedance adjustment (c

48、ontd)JEDEC Standard No. 208Page 222.4.3.3 Drive modeDrive mode, both Drive(1) and Drive(0), is used for controllers to measure DDR2 SDRAM Driver impedance. In this mode, all outputs are driven out tOIT after “enter drive mode” command and all output drivers are turned-off tOIT after “OCD calibration

49、 mode exit” command as shown in Figure 142.4.4 ODT (on-die termination)On Die Termination (ODT) is a feature that allows a DRAM to turn on/off termination resistance for each DQ, DQS/DQS, RDQS/RDQS, and DM signal for x4/x8 configurations via the ODT control pin. For x16 configuration ODT is applied to each DQ, UDQS/UDQS, LDQS/LDQS, UDM, and LDM signal via the ODT control pin. The ODT feature is designed to improve signal integrity of the memory channel by allowing the DRAM controller to independently turn on/off termination resistance for