JEDEC JESD208-2007 SPECIALITY DDR2-1066 SDRAM.pdf
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1、JEDEC SOLID STATE TECHNOLOGY ASSOCIATIONJESD208NOVEMBER 2007JEDECSTANDARDSPECIALITY DDR2-1066 SDRAMNOTICE JEDEC standards and publications contain material that has been prepared, reviewed, and approved through the JEDEC Board of Directors level and subsequently reviewed and approved by the JEDEC le
2、gal counsel. JEDEC standards and publications are designed to serve the public interest through eliminating misunderstandings between manufacturers and purchasers, facilitating interchangeability and improvement of products, and assisting the purchaser in selecting and obtaining with minimum delay t
3、he proper product for use by those other than JEDEC members, whether the standard is to be used either domestically or internationally. JEDEC standards and publications are adopted without regard to whether or not their adoption may involve patents or articles, materials, or processes. By such actio
4、n JEDEC does not assume any liability to any patent owner, nor does it assume any obligation whatever to parties adopting the JEDEC standards or publications. The information included in JEDEC standards and publications represents a sound approach to product specification and application, principall
5、y from the solid state device manufacturer viewpoint. Within the JEDEC organization there are procedures whereby a JEDEC standard or publication may be further processed and ultimately become an ANSI standard. No claims to be in conformance with this standard may be made unless all requirements stat
6、ed in the standard are met. Inquiries, comments, and suggestions relative to the content of this JEDEC standard or publication should be addressed to JEDEC at the address below, or call (703) 907-7559 or www.jedec.org Published by JEDEC Solid State Technology Association 2007 2500 Wilson Boulevard A
7、rlington, VA 22201-3834 This document may be downloaded free of charge; however JEDEC retains the copyright on this material. By downloading this file the individual agrees not to charge for or resell the resulting material. PRICE: Please refer to the current Catalog of JEDEC Engineering Standards a
8、nd Publications online at http:/www.jedec.org/Catalog/catalog.cfm Printed in the U.S.A. All rights reserved PLEASE! DONT VIOLATE THE LAW! This document is copyrighted by JEDEC and may not be reproduced without permission. Organizations may obtain permission to reproduce a limited number of copies th
9、rough entering into a license agreement. For information, contact: JEDEC Solid State Technology Association 2500 Wilson Boulevard Arlington, Virginia 22201-3834 or call (703) 907-7559 JEDEC Standard No. 208Page 1SPECIALITY DDR2-1600 SDRAM(From JEDEC Board Ballot JCB-07-64, JCB-07-69, and JCB-07-98,
10、formulated under the cognizance of the JC-42.3 Subcommittee on RAM Memories.)ScopeThis document defines the Specialty DDR2-1066 SDRAM specification, including features, functionalities, AC and DC characteristics, packages, and ball/signal assignments. The purpose of this Specification is to define t
11、he minimum set of requirements for JEDEC compliant 256 Mb through 4 Gb for x4, x8, and x16 Specialty DDR2-1066 SDRAM devices. This specification was created based on the DDR2 specification (JESD79-2) and some aspects of the DDR specification (JESD79). Each aspect of the changes for Specialty DDR2-10
12、66 SDRAM operation were considered and balloted. The accumulation of these ballots were then incorporated to prepare this JESD208 specification, replacing whole sections and incorporating the changes into Functional Description and Operation.JEDEC Standard No. 208Page 21 Package ballout UDQS corresp
13、onds to the data on DQ8-DQ15. For the x8, an RDQS option using DM pin can be enabled via the EMR(1) to simplify read timing. The data strobes DQS, LDQS, UDQS, and RDQS may be used in single ended mode or paired with optional complementary signals DQS, LDQS, UDQS, and RDQS to provide differen-tial pa
14、ir signaling to the system during both reads and writes. A control bit at EMR(1)A10 enables or disables all complementary data strobe signals.In this data sheet, “differential DQS signals“ refers to any of the following with EMR(1)A10 = 0x4 DQS/DQSx8 DQS/DQS if EMR(1)A11 = 0x8 DQS/DQS, RDQS/RDQS, if
15、 EMR(1)A11 = 1x16 LDQS/LDQS and UDQS/UDQS “single-ended DQS signals“ refers to any of the following with EMR(1)A10 = 1x4 DQSx8 DQS if EMR(1)A11 = 0x8 DQS, RDQS, if EMR(1)A11 = 1x16 LDQS and UDQSNC No Connect: No internal electrical connection is present.VDDQSupply DQ Power Supply: 1.8 V +/- 0.1 VVSS
16、QSupply DQ GroundVDDLSupply DLL Power Supply: 1.8 V +/- 0.1 V1 Package ballout accesses start at a selected location and continue for a burst length of four or eight in a programmed sequence. Accesses begin with the registration of an Active command, which is then followed by a Read or Write command
17、. The address bits registered coincident with the active command are used to select the bank and row to be accessed (BA0-BA2 select the bank; A0-A15 select the row). The address bits registered coincident with the Read or Write command are used to select the starting column location for the burst ac
18、cess and to determine if the auto precharge command is to be issued.Prior to normal operation, the DDR2 SDRAM must be initialized. The following sections provide detailed information covering device initialization, register definition, command descriptions and device operation.2.3 Power-up and initi
19、alizationDDR2 SDRAMs must be powered up and initialized in a predefined manner. Operational procedures other than those specified may result in undefined operation.For DDR2 SDRAMs, both bits BA0 and BA1 must be decoded for Mode/Extended Mode Register Set (MRS/EMRS) commands. Users must initialize al
20、l four Mode Registers. The registers may be initialized in any order.2.3.1 Power-up and initialization sequenceThe following sequence is required for Power-up and Initialization.a) Either one of the following sequence is required for Power-up.a1) While applying power, attempt to maintain CKE below 0
21、.2 x VDDQ and ODT*1at a LOW state (all other inputs may be undefined.) The VDD voltage ramp time must be no greater than 200 ms from when VDD ramps from 300 mV to VDD min; and during the VDD voltage ramp, |VDD-VDDQ| 0.3 volts. Once the ramping of the supply voltages is complete (when VDDQ crosses VD
22、DQ min), the supply voltage specifications provided in section 5, Table 16 Recommended DC operating conditions (SSTL_1.8), prevail.- VDD, VDDL and VDDQ are driven from a single power converter output, AND- VTT is limited to 0.95 V max, AND- Vref tracks VDDQ/2, VREF must be within +/- 300 mV with res
23、pect to VDDQ/2 during supply ramp time.- VDDQ VREF must be met at all times.a2) While applying power, attempt to maintain CKE below 0.2 x VDDQ and ODT*1at a LOW state, all other inputs may be undefined, voltage levels at I/Os and outputs must be less than VDDQ during voltage ramp time to avoid DRAM
24、latch-up. During the ramping of the supply voltages, VDD VDDL VDDQ must be maintained and is applicable to both AC and DC levels until the ramping of the supply voltages is complete, which is when VDDQ crosses VDDQ min. Once the ramping of the supply voltages is complete, the supply voltage specific
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