JEDEC JESD15-1-2008 Compact Thermal Model Overview.pdf

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1、JEDEC STANDARD Compact Thermal Model Overview JESD15-1 OCTOBER 2008 JEDEC SOLID STATE TECHNOLOGY ASSOCIATION NOTICE JEDEC standards and publications contain material that has been prepared, reviewed, and approved through the JEDEC Board of Directors level and subsequently reviewed and approved by th

2、e JEDEC legal counsel. JEDEC standards and publications are designed to serve the public interest through eliminating misunderstandings between manufacturers and purchasers, facilitating interchangeability and improvement of products, and assisting the purchaser in selecting and obtaining with minim

3、um delay the proper product for use by those other than JEDEC members, whether the standard is to be used either domestically or internationally. JEDEC standards and publications are adopted without regard to whether or not their adoption may involve patents or articles, materials, or processes. By

4、such action JEDEC does not assume any liability to any patent owner, nor does it assume any obligation whatever to parties adopting the JEDEC standards or publications. The information included in JEDEC standards and publications represents a sound approach to product specification and application,

5、principally from the solid state device manufacturer viewpoint. Within the JEDEC organization there are procedures whereby a JEDEC standard or publication may be further processed and ultimately become an ANSI standard. No claims to be in conformance with this standard may be made unless all require

6、ments stated in the standard are met. Inquiries, comments, and suggestions relative to the content of this JEDEC standard or publication should be addressed to JEDEC at the address below, or call (703) 907-7559 or www.jedec.org Published by JEDEC Solid State Technology Association 2008 3103 North 10

7、th Street Suite 240 South Arlington, VA 22201-2107 This document may be downloaded free of charge; however JEDEC retains the copyright on this material. By downloading this file the individual agrees not to charge for or resell the resulting material. PRICE: Please refer to the current Catalog of JE

8、DEC Engineering Standards and Publications online at http:/www.jedec.org/Catalog/catalog.cfm Printed in the U.S.A. All rights reserved PLEASE! DONT VIOLATE THE LAW! This document is copyrighted by JEDEC and may not be reproduced without permission. Organizations may obtain permission to reproduce a

9、limited number of copies through entering into a license agreement. For information, contact: JEDEC Solid State Technology Association 3103 North 10th Street Suite 240 South Arlington, VA 22201-2107 or call (703) 907-7559 JEDEC Standard No. 15-1 Page 1 COMPACT THERMAL MODEL OVERVIEW DOCUMENT (From J

10、EDEC Board Ballot JCB-08-28, formulated under the cognizance of the JC-15.1 Committee on Thermal Characterization.) 1 Scope This document should be used in conjunction with the master document, “Methodology for the Thermal Modeling of Component Packages1”, the “Terms and Definitions document2”, and

11、subsidiary documents as they become available. This document is intended to function as an OVERVIEW to support the effective use of Compact Thermal Model (CTM) methodologies as specified in the companion methods documents. At present, there are two such documents: “Two-Resistor Compact Thermal Model

12、 Guideline3” and “DELPHI Compact Thermal Model Guideline4.” The planned structure for this set of documents is indicated in Figure 1. Figure 1 Diagram indicating modular structure of CTM documents This OVERVIEW is intended to provide a context for the comparison of CTM methods by defining a number o

13、f qualitative criteria. A procedure for quantifying the relative accuracy of different CTM methods by the calculation of Boundary Condition Independence (BCI) and Boundary Condition Subset (BCS) Indices will be specified in the future document, BCI Esprit III project no. 22797; 1997-1998) and PROFIT

14、 (Prediction of Temperature Gradients Influencing the Quality of Electronic Products; European Community IST Program, project no. 12529; 2000 2002). The CTM work was released into the public domain by means of reports and publications. Members of the DELPHI, SEED, and PROFIT projects have continued

15、to be active in the JC15 committee to promote an awareness of developments in CTM methodology and to participate in standardization efforts. The JEDEC activities have emphasized enhancing the practical application of the DELPHI methods and, as much as possible, leveraging the existing JEDEC thermal

16、standards to facilitate the adoption of these methods by the electronics industry, world-wide. 7 Criteria for comparison of CTM methods A number of criteria have been established in order to provide a context for the comparison of CTM methods. They will be applied in this document to CTM methods def

17、ined by subsidiary documents. Is the CTM test based or simulation based? o A model may be extracted directly from test results or from simulations that, themselves, have been validated with test results. Does the CTM contain an artifact of the test environment? o A model extracted directly from test

18、 results may have embedded in it the contribution of different heat flow paths and the resultant temperature differences caused by the test fixturing and test environment. In general, CTMs that contain an artifact of the test environment will have lower accuracy than those that do not. JEDEC Standar

19、d No. 15-1 Page 5 7 Criteria for comparison of CTM methods (contd) Does the CTM generation methodology inherently include an error analysis? o Simulation-based methods typically include this as a by-product of the optimization procedure to determine the best-fit values of the resistors in the CTM ne

20、twork. Methods that assign values to the resistors in a CTM directly from experimental measurements do not include an error analysis of the CTM as an integral part of the process of generating the resistor values. Calculation of BCI and BCS Indices. o A method of calculating a BCI Index will be spec

21、ified in a future document. (This document is indicated in the roadmap as, “BCI b. The side surfaces of the package. It then is transmitted into the ambient fluid. c. The package bottom surface and leads. It then flows into the PCB. 4) Thermal resistor networks are used to represent the heat flow pa

22、ths. 5) Each external surface of the part may be considered to be at a single temperature represented by one node. Alternatively, the external surfaces can be subdivided into regions each with a single temperature corresponding to one node. The CTM methods defined by JEDEC are the Two-Resistor Model

23、 and the DELPHI Model. They are described below. 9.1 Two-Resistor CTM The Two-Resistor CTM represents the heat flow paths described in 3a and 3c (above) in the simplest possible way, namely using a single thermal resistor for each. This is illustrated in Figure 2. Note that for the two resistor mode

24、l, the heat path described in 3b is ignored. JCtopJBBoard NodeCase NodeJunction NodeFigure 2 Two-Resistor Model Network Topology JEDEC Standard No. 15-1 Page 7 9 CTM methods (contd) 9.1 Two-Resistor CTM (contd) The Two-Resistor Model consists of three nodes as depicted in the Figure 2. These are con

25、nected together by two thermal resistors, being the measured values of the Junction-to-Board5and Junction-to-Case6resistances described above. NOTE JESD51-12 defines the use of the Junction-to-Case resistance. It does not define the test method to measure this quantity. The appropriate test method w

26、ill be specified in a future document. The heating power is applied at the Junction node. The Board node is considered to be in direct thermal contact with the local environment immediately below the footprint of the package (normally the PCB). The Case node is considered to be in direct thermal con

27、tact with the local environment immediately above the top of the package (normally air or a thermal interface material used in conjunction with a heat sink). Thus there are only two paths for the heat to leave the Junction node and flow into the environment - through the Case node and through the Bo

28、ard node. No heat flow through the sides of the package is accounted for. 9.2 Application of standard CTM criteria to Two-Resistor Model The Two-Resistor model has the following characteristics when rated according to the CTM criteria of Section 7: Is the CTM test-based or simulation-based? o The tw

29、o resistors are extracted from JEDEC-standard thermal tests or a validated detailed thermal model that simulates the test environment. Does the CTM contain an artifact of the test environment? o The junction-to-board resistor contains a contribution due to heat flow through the test board. Does the

30、CTM generation methodology inherently include an error analysis? o The two-resistor CTM methodology does not contain an error analysis. Calculation of BCI and BCS Indices. o Will be specified in a future document. JEDEC Standard No. 15-1 Page 8 9 CTM methods (contd) 9.3 DELPHI CTM A DELPHI compact m

31、odel is a thermal resistance network. The DELPHI network is comprised of a limited number of nodes connected to each other by thermal resistors or links. A possible configuration is shown in Figure 3. In effect, the complex 3D heat flow within a real package is represented by a series of links. Netw

32、ork nodes are, by definition, each associated with a single temperature only. They can be either surface or internal. Surface nodes are associated with a physical region of the package surface defining the area of the node. In such a case, the nodal temperature represents the average temperature of

33、the area allocated to the node in the actual package. Internal nodes lie within the package body and may or may not correspond to a physical region within the package. Surface nodes must always have a direct one-to-one association with the corresponding physical areas on the actual package. Therefor

34、e, it is critical that they communicate with the environment in the same manner as the package surfaces they represent. Surface nodes communicate with internal nodes as well as the surrounding environment. Internal nodes do not communicate with the environment directly; however they may have a heat

35、source associated with them (for example, to represent the heat flow from a die within the package). Figure 3 Example of a Compact Model Network Topology Junction (heat source) Top Inner Top OuterBottom Inner Bottom OuterLeadsThermal Resistors JEDEC Standard No. 15-1 Page 9 9 CTM methods (contd) 9.4

36、 Application of standard CTM criteria to DELPHI model The DELPHI model has the following characteristics when rated according to the CTM criteria in 7: Is the CTM test-based or simulation-based? o It is simulation-based. The values of the resistors in the network topology representing the package ar

37、e chosen by minimization of the Objective Function. Does the CTM contain an artifact of the test environment? o The network representing the package does not contain any resistors representing heat flow in the test board. Thus, the DELPHI model contains no artifact of the test environment. Does the

38、CTM generation methodology inherently include an error analysis? o The statistical procedure used to extract optimum values for the individual resistors inherently includes an error analysis. Calculation of BCI and BCS Indices. o Will be specified in a future document. 10 Bibliography Selected publi

39、shed documents related to CTM history and methodology. 1. W. Krueger and A. Bar-Cohen, “Thermal characterization of a PLCC-expanded Rjcmethodology” IEEE Transactions on Components and Packaging Technologies, Vol. 15, 1992, pp. 691-698. 2. H. Rosten, C. Lasance, and J. Parry, “The World of Thermal Ch

40、aracterization According to DELPHI Part I: Background to DELPHI,” IEEE Transactions on Components and Packaging Technologies, Vol. 20, 1997, pp. 384-391. 3. C. Lasance, D. den Hertog, and P. Stehouwer, “Creation and Evaluation of Compact Models for Thermal Characterization Using Dedicated Optimisati

41、on Software,” Proceedings of the Fifteenth IEEE SEMI-THERM Symposium, 1999, pp. 189-200. 4. Aranyosi, A. Ortega, J. Evans, T. Tarter, J. Pursel, and J. Radhakrishnan, “Development of Compact Thermal Models for Advanced Electronic Packaging: Methodology and Experimental Validation for a Single-Chip C

42、PGA Package,” Proceedings of the ITHERM Conference, 2000, pp. 225-232. 5. E.G.T. Bosch, “Thermal Compact Models: An Alternative Approach,” IEEE Transactions on Components and Packaging Technologies, Vol. 26, 2003, pp.173-178. 6. H. Pape and G. Noebauer, “Thermal Characterization of Active Components

43、,” Electronics Cooling, Vol. 4, No. 2, 1999, pp. 38-43. JEDEC Standard No. 15-1 Page 10 10 Bibliography (contd) 7. H. Pape, and G. Noebauer, “Generation and Verification of Boundary Independent Compact Thermal Models for Active Components According to the DELPHI/SEED Methods,” Proceedings of the Fif

44、teenth IEEE SEMI-THERM Symposium, 1999, pp.201-211. 8. M. Rencz, V. Szekely, and E. Kollar, “Measuring Dynamic Thermal Multiport Parameters of IC Packages”, Proceedings of the 6th THERMINIC Workshop, Budapest, 2000, pp.244-249. 9. C. Lasance, “Recent Progress in Compact Thermal Models,” Proceedings

45、of the Twenty-first IEEE SEMI-THERM Symposium, San Jose, CA, 2003, pp. 290-299. 10. C. Lasance, “The Influence of Various Common Assumptions on the Boundary-Condition-Independence of Compact Thermal Models,” IEEE Transactions on Components and Packaging Technologies, Vol. 27, 2004, pp.523-529. 11. H

46、. Pape, D. Schweitzer, J. Janssen, A. Morelli, C. Villa, “Thermal Transient Modeling and Experimental Validation in the European Project PROFIT,” IEEE Transactions on Components and Packaging Technologies, Vol. 27, 2004, pp.530-539. 12. M.-N. Sabry, “Higher-Order Compact Thermal Models,” Proceedings

47、 of the 10th THERMINIC Workshop, Sophia-Antipolis, 2004, pp.273-281. 13. M.-N. Sabry, “Compact Thermal Models for Electronic Systems, “IEEE Transactions on Components and Packaging Technologies, Vol. 26, No. 2, 2003, pp.179-185. 14. M.-N. Sabry, “Flexible- Profile Compact Thermal Models,”Proceedings

48、 of 11th THERMINIC Workshop, Belgirate, Italy, 2005, pp. 32-37. 15. M.-N. Sabry, “Dynamic Compact Thermal Models Used for Electronic Design: A Review of Recent Progress,” Interpack 03, Paper No. 35185, Maui, July 6-11, 2003. 16. M-N. Sabry, S. Hossam, “Compact Thermal Models: A Global Approach,” Pro

49、ceedings of 1st Theta Workshop, Cairo, 2007, pp. 51-57. 17. C. Lasance, “Ten Years of Boundary-Condition-Independent Compact Thermal Modeling of Electronic Parts: A Review,” Heat Transfer Engineering, Vol. 29, Issue 2, 2008, pp.149-168. Standard Improvement Form JEDEC The purpose of this form is to provide the Technical Committees of JEDEC with input from the industry regarding usage of the subject standard. Individuals or companies are invited to submit comments to JEDEC. All comments will be collected and dispersed to the appropriat