ITU-T V 27-1988 4800 BITS PER SECOND MODEM WITH MANUAL EQUALIZER STANDARDIZED FOR USE ON LEASED TELEPHONE-TYPE CIRCUITS《租用电话型电路上使用的标准化4800bit s带人工均衡器的调制解调器 -电话网络上的数据交流》.pdf

《ITU-T V 27-1988 4800 BITS PER SECOND MODEM WITH MANUAL EQUALIZER STANDARDIZED FOR USE ON LEASED TELEPHONE-TYPE CIRCUITS《租用电话型电路上使用的标准化4800bit s带人工均衡器的调制解调器 -电话网络上的数据交流》.pdf》由会员分享，可在线阅读，更多相关《ITU-T V 27-1988 4800 BITS PER SECOND MODEM WITH MANUAL EQUALIZER STANDARDIZED FOR USE ON LEASED TELEPHONE-TYPE CIRCUITS《租用电话型电路上使用的标准化4800bit s带人工均衡器的调制解调器 -电话网络上的数据交流》.pdf（9页珍藏版）》请在麦多课文档分享上搜索。

1、INTERNATIONAL TELECOMMUNICATION UNION)45G134 6 TELECOMMUNICATIONSTANDARDIZATION SECTOROF ITU$!4!G0G0#/-5.)#!4)/./6%2G0G04(%G0G04%,%0(/.%G0G0.%47/2+G0“)43G0G00%2G0G03%#/.$G0G0-/$%-7)4(G0G0-!.5!,G0G0%15!,):%2G0G034!.$!2$):%$amended at Geneva, 1976 and 1980,Malaga-Torremolinos, 1984)1 IntroductionThis

2、modem is intended to be used primarily on Recommendation M.1020 1 circuits but this does not precludethe use of this modem over circuits of lower quality at the discretion of the Administration concerned.On leased circuits, considering that there exist and will come into being many modems with featu

3、res designedto meet the requirements of the Administrations and users, this Recommendation in no way restricts the use of any othermodems.The principal characteristics for this recommended modem for transmitting data at 4800 bits per second onleased circuits are as follows:a) it is capable of operat

4、ing in a full-duplex mode or half-duplex mode;b) differential eight-phase modulation with synchronous mode of operation;c) possibility of a backward (supervisory) channel at modulation rates up to 75 bauds in each direction oftransmission, the use of these channels being optional;d) inclusion of a m

5、anually adjustable equalizer.2 Line signals2.1 The carrier frequency is to be 1800 1 Hz. No separate pilot frequencies are provided. The power levels usedwill conform to Recommendation V.2.2.2 Division of power between the forward and backward channelsIf simultaneous transmission of the forward and

6、backward channels occurs in the same direction, a backwardchannel should be 6 dB lower in power level than the forward (data) channel.2.3 The data stream to be transmitted is divided into groups of three consecutive bits (tribits). Each tribit isencoded as a phase change relative to the phase of the

7、 immediately preceding signal element (see Table 1/V.27). At thereceiver the tribits are decoded and the bits are reassembled in correct order. The left-hand digit of the tribit is the oneoccurring first in the data stream as it enters the modulator portion of the modem after the scrambler.3 Data si

8、gnalling and modulation ratesThe data signalling rate shall be 4800 bits per second 0.01%, i.e. the modulation rate is 1600 bauds 0.01%.4 Received signal frequency toleranceThe carrier frequency tolerance allowance at the transmitter is 1 Hz and assuming a maximum frequency driftof 6 Hz in the conne

9、ction between the modems, then the receiver must be able to accept errors of at least 7 Hz in thereceived frequencies.2 Fascicle VIII.1 - Rec. V.275 Backward channelThe modulation rate, characteristic frequencies, tolerances, etc. to be as recommended for backward channel inRecommendation V.23. This

10、 does not preclude the use of a higher speed backward channel with operational capabilityof 75 bauds or higher, bearing the same characteristic frequencies as the V.23 backward channel.6 Interchange circuits6.1 List of essential interchange circuits (see Table 2/V.27)TABLE 1/V.27Tribit valuesPhase c

11、hange(see Note)00001111001111001001100104590135180225270315Note - The phase change is the actual on-line phase shift in thetransition region from the centre of one signalling element to thecentre of the following signalling element.Fascicle VIII.1 - Rec. V.27 3TABLE 2/V.27Interchange circuitForward

12、(data) channelhalf-duplex of full-duplex(see Note 1)No DesignationWithoutbackwardchannelWith backwardchannel102103104105(see Note 2)106107108/1109113114115118119120121122Signal ground or common return .Transmitted data.Received data .Request to send.Ready for sending.Data set ready.Connect data set

13、to line Data channel received line signal detector Transmitter signal element timing(DTE source)Transmitter signal element timing(DCE source)Receiver signal element timing(DCE source)Transmitter backward channel data .Received backward channel data .Transmit backward channel line signal .Backward ch

14、annel readyBackward channel received line signal detector .XXXXXXXXXXXXXXXXXXXXXXXXXXXNote 1 - All essential interchange circuits and any others which are provided shall comply with the functional and operationalrequirements of Recommendation V.24. All interchange circuits indicated by X shall be pr

15、operly terminated in the data terminalequipment and in the data circuit-terminating equipment in accordance with the appropriate Recommendation for electricalcharacteristics 6.6).Note 2 - No essential for 4-wire full-duplex continuous carrier operation.6.2 Threshold and response times of circuit 109

16、A fall in level of the incoming line signal to -31 dBm or lower for more than 10 5 ms will cause circuit 109 tobe turned OFF. An increase in level to -26 1 dBm or higher will turn this circuit ON after a delay of:a) 13 3 ms for fast operations,b) 100 ms to 1200 ms for slow operation,where the choice

17、 of the delay for slow operation depends upon the application. Delays within the range of b)may be provided for 4-wire full-duplex continuous carrier operation.4 Fascicle VIII.1 - Rec. V.276.3 Response time for circuit 106The time between the OFF to ON transition of circuit 105 and the OFF to ON tra

18、nsition of circuit 106 shall beoptionally 20 3 ms or 50 20 ms.6.4 Clamping in half-duplex modeThe DCE, when operating in half-duplex mode on a 2-wire line shall hold, where implemented:a) circuit 104 in the binary 1 condition and circuit 109 in the OFF condition when circuit 105 is in the ONconditio

19、n and, where required to protect circuit 104 from false signals, for a period of 150 25 msfollowing the ON to OFF transition on circuit 105; the use of this additional delay is optional, based onsystem considerations;b) circuit 119 in the binary 1 condition and circuit 122 in the OFF condition when

20、circuit 120 is in the ONcondition and, where required to protect circuit 119 from false signals, for a time interval following theON to OFF transition on circuit 120. The specific duration of this time interval is left for further study.The additional delay is optional, based on system consideration

21、s.6.5 Fault condition of interchange circuits(See Recommendation V.28, 7 for association of the receiver failure detection types.)6.5.1 The DTE should interpret a fault condition on circuit 107 as an OFF condition using failure detection type 1.6.5.2 The DCE should interpret a fault condition on cir

22、cuits 105 and 108 as an OFF condition using failure detectiontype 1.6.5.3 All other circuits not referred to above may use failure detection type 0 or 1.6.6 Electrical characteristics of interchange circuitsUse of electrical characteristics conforming to Recommendation V.28 is recommended together w

23、ith theconnector and pin assignment plan specified by ISO 2110.Note - Manufacturers may wish to note that the long-term objective is to replace electrical characteristicsspecified in Recommendation V.28, and that Study Group XVII has agreed that the work shall proceed to develop amore efficient, all

24、 balanced, interface for the V-Series application which minimizes the number of interchange circuits.7 Timing arrangementsClocks should be included in the modem to provide the data terminal equipment with transmitter signal elementtiming, circuit 114 and receiver signal clement timing, circuit 115.

25、Alternatively, the transmitter signal element timingmay be originated in the data terminal equipment and be transferred to the modem via circuit 113.8 Synchronizing signalDuring the interval between the OFF to ON transition of circuit 105 and the OFF to ON transition of circuit106, synchronizing sig

26、nals for properly conditioning the receiving modem must be generated by the transmittingmodem. These signals are defined as:a) signals to establish basic demodulator requirements;b) signals to establish scrambler synchronization.The actual composition of the synchronization signals is continuous 180

27、 degrees phase reversals on line for9 1 ms followed by continuous 1s at the input to the transmit scrambler for b). Condition b) shall be sustained until theOFF to ON transition of circuit 106.9 Line signal characteristicsA 50% raised cosine energy spectrum shaping is equally divided between the rec

28、eiver and transmitter.Fascicle VIII.1 - Rec. V.27 510 ScramblerA self-synchronizing scrambler/descrambler having the generating polynomial:1 + x-6+ x-7with additional guards against repeating patterns of 1, 2, 3, 4, 6, 9 and 12 bits, shall be included in the modem. AppendixI shows a suitable logical

29、 arrangement.At the transmitter the scrambler shall effectively divide the message polynomial, of which the input datasequence represents the coefficients in descending order, by the scrambler generating polynomial, to generate thetransmitted sequence, and at the receiver the received polynomial, of

30、 which the received data sequence represents thecoefficients in descending order, shall be multiplied by the scrambler generating polynomial to recover the messagesequence.The detailed scrambling and descrambling processes are described in Appendix I.11 EqualizerA manually adjustable equalizer with

31、the capability of compensating for the amplitude and group delaydistortion within the limits of Recommendation M.1020 1 shall be provided in the receiver. The transmitter shall beable to send an equalization pattern while the receiver shall incorporate a means of indicating correct adjustment of the

32、equalizer controls. The equalizer pattern is generated by applying continuous 1s to the input of the transmitter scramblerdefined above.12 Alternative equalization and scrambler techniquesThis Recommendation does not preclude the use of alternative equalization techniques, for example manuallyadjust

33、able transmit equalizers for use in multipoint polled networks and for point-to-point networks with an unattendedlocation.These techniques, and their incorporation in the modem, and a new scrambler, should be the subject of furtherstudy.Note - For modems with automatic adaptive equalizers, see Recom

34、mendation V.27 bis.13 The following information is provided to assist equipment manufacturers:- the data modem should have no adjustment for send level or receive sensitivity under the control of theoperator;- no fall-back rate has been included because the convenient rate would be 3200 bit/s, not a

35、 permitted rate;- circuit 108/2 has not been included in the list of interchange circuits because it was considered that themodem would not be suitable for switched network use until an automatic equalizer had beenrecommended.6 Fascicle VIII.1 - Rec. V.27APPENDIX I(to Recommendation V.27)Detailed sc

36、rambling and descrambling processesI.1 ScramblingThe message polynomial is divided by the generating polynomial 1 + x-6+ x-7. (See Figure I-1/V.27.) Thecoefficients of the quotient of this division are taken in descending order from the data sequence to be transmitted.The transmitted bit sequence is

37、 continuously searched over a span of 45 bits for sequences of the formwhereai= 1 or 0 and ai= ai+ 9or ai+ 12If such a sequence occurs, the bit immediately following the sequence is inverted before transmission.I.2 DescramblingAt the receiver the incoming bit sequence is continuously searched over a

38、 span of 45 bits for sequences of theform p(x). If such a sequence occurs, the bit immediately following the sequence is inverted. The polynomial representedby the resultant sequence is then multiplied by the generating polynomial 1 + x-6+ x-7to form the recovered messagepolynomial. The coefficients

39、 of the recovered polynomial, taken in descending order, form the output data sequence.I.3 Elements of scrambling processThe factor 1 + x-6+ x-1randomizes the transmitted data over a sequence length of 127 bits.The equality ai= ai+9in the guard polynomial p(x) prevents repeated patterns of 1, 3 and

40、9 bits from occurringfor more than 42 successive bits.The equality ai= ai+12in p(x) prevents repeated patterns of 2, 4, 6 and 12 bits from occurring for more than45 successive bits.Fascicle VIII.1 - Rec. V.27 7I.4 Figure I-2/V.27 is given as an indication only, since with another technique this logical arrangement mighttake another form.Reference1 CCITT Recommendation Characteristics of special quality international leased circuits, with specialbandwidth conditioning, Vol. IV, Rec. M.1020.