EN 61691-2-2001 en Behavioural Languages Part 2 VHDL Multilogic System for Model Interoperability《行为语言 第2部分 模型互通性用VHDL多种逻辑系统 IEC 61691-2 2001》.pdf

《EN 61691-2-2001 en Behavioural Languages Part 2 VHDL Multilogic System for Model Interoperability《行为语言 第2部分 模型互通性用VHDL多种逻辑系统 IEC 61691-2 2001》.pdf》由会员分享，可在线阅读，更多相关《EN 61691-2-2001 en Behavioural Languages Part 2 VHDL Multilogic System for Model Interoperability《行为语言 第2部分 模型互通性用VHDL多种逻辑系统 IEC 61691-2 2001》.pdf（28页珍藏版）》请在麦多课文档分享上搜索。

1、BRITISH STANDARD Behavioural languages Part 2: VHDL multilogic system for model interoperability The European Standard EN 61691-2:2001 has the status ofa British Standard ICs 35.240.50 BS EN IEC 6 169 1-21200 1 6 169 1-21200 1 Wk present to the responsible international/European committee any enquir

2、ies on the interpretation, or proposals for change, and keep the UK interests informed; monitor related international and European developments and promulgate them in the UK. - A list of organizations represented on this committee can be obtained on request to its secretary. From 1 January 1997, all

3、 IEC publications have the number 60000 added to the old number. For instance, IEC 27-1 has been renumbered as IEC 60027-1. For a period oftime during the change over from one numbering system to the other, publications may contain identifiers from both systems. Cr oss-r e fer enc e s The British St

4、andards which implement international or European publications referred to in this document may be found in the BSI Standards Catalogue under the section entitled “International Standards Correspondence Index”, or by using the “Find” facility of the BSI Standards Electronic Catalogue. A British Stan

5、dard does not purport to include all the necessary provisions of a contract. Users of British Standards are responsible for their correct application. Compliance with a British Standard does not of itself confer immunity from legal obligations. Summary of pages This document comprises a front cover,

6、 an inside front cover, the EN title page, the EN foreword page, the IEC title page, pages 2 to 23 and a back cover. The BSI copyright date displayed in this document indicates when the document was last issued. O BSI 2 April 2002 ISBN O 580 39266 X EUROPEAN STANDARD EN 61691-2 NORME EUROPENNE EUROP

7、ISCHE NORM Decem ber 2001 ICs 35.240.50 English version Behavi ou ral languages Part 2: VHDL multilogic system for model interoperability (IEC 61691-212001) Langages relatifs au comportement Verhaltensebenensprache Partie 2: Systme multilogique en VHDL permettant Iinteroprabilit des modles Teil 2: S

8、ystem fr mehrwertige Logik fr das VHDL-Interoperabilittsmodell (CE1 61691-212001) (IEC 61691-212001) This European Standard was approved by CENELEC on 2001-09-01. CENELEC members are bound to comply with the CENKENELEC Internal Regulations which stipulate the conditions for giving this European Stan

9、dard the status of a national standard without any alteration. Up-to-date lists and bibliographical references concerning such national standards may be obtained on application to the Central Secretariat or to any CENELEC member. This European Standard exists in three official versions (English, Fre

10、nch, German). A version in any other language made by translation under the responsibility of a CENELEC member into its own language and notified to the Central Secretariat has the same status as the official versions. CENELEC members are the national electrotechnical committees of Austria, Belgium,

11、 Czech Republic, Denmark, Finland, France, Germany, Greece, Iceland, Ireland, Italy, Luxembourg, Malta, Netherlands, Norway, Portugal, Spain, Sweden, Switzerland and United Kingdom. CENELEC European Committee for Electrotechnical Standardization Comit Europen de Normalisation Electrotechnique Europi

12、sches Komitee fr Elektrotechnische Normung Central Secretariat: rue de Stassart 35, B - 1050 Brussels O 2001 CENELEC - All rights of exploitation in any form and by any means reserved worldwide for CENELEC members. Ref. No. EN 61691-2:2001 E EN 61691-22001 Foreword The text of document 93/130/FDIS,

13、future edition 1 of IEC 61691-2, prepared by IEC TC 93, Design automation, was submitted to the IEC-CENELEC parallel vote and was approved by CENELEC as EN 61691-2 on 2001-09-01. The following dates were fixed: - latest date by which the EN has to be implemented at national level by publication of a

14、n identical national standard or by endorsement - latest date by which the national standards conflicting with the EN have to be withdrawn (dop) 2002-06-01 (dow) 2004-09-01 This standard is based on IEEE Std 1164:1993, Multivalue logic system for VHDL model interopera bility. Endorsement not i ce Th

15、e text of the International Standard IEC 61691-2:2001 was approved by CENELEC as a European Standard without any modification. INTERNATIONAL STANDARD EN 61691-2:2001 I EC 61691-2 First edition 2001 -06 Behavioural languages Part 2: VHDL multilogic system for model interoperability Reference number I

16、EC 61 691 -2:2001 (E) Page 2 EN 61691-22001 BEHAVIOURAL LANGUAGES - Part 2: VHDL multilogic system for model interoperatibility 1. Overview 1.1 Scope This standard is embodied in the Std-logic-1164 package package body along with this clause 1 documentation. The information annex AA is a guide to us

17、ers and is not part of this standard, but suggests ways in which one might use 1.2 Conformance with this standard The following conformance rules shall apply as they a) b) No modifications shall be made to the package declaration The Std-logic-1164 package body represents the formal Std-logic-1164 p

18、ackage declaration. Implementers of this package body as it is; or they may choose to implement to the user. Users shall not implement a semantic that 2. Std-logic-1164 package declaration _ - Title : Std-logic-1164 multivalue logic system - Library : This package shall be compiled into a library _

19、: symbolically named IEEE. - Developers: IEEE model standards group (par 1164) - Purpose : This packages defines a standard for designers _ _ _ : to use in describing the : used in VHDL modeling. _ O BSI 2 April 2002 Page 3 EN 61691-22001 - Limitation: The logic system defined in this package may _

20、: be insufficient for modeling switched _ : since such a requirement is out of the _ : effort. Furthermore, mathematics, primitives, _ : timing standards, etc. are considered _ : issues in relation to this package and _ : beyond the scope of this effort. - Note : No declarations or definitions shall

21、 be _ : or excluded from, this package. The _ : defines the types, subtypes, and _ : Std-logic-1164. The Std-logic-1164 _ : considered the formal definition of the _ : this package. Tool developers may _ : the package body in the most efficient _ : to them. _ _ - modification history - version I mod

22、. date:l - 4.200 101/02/92 I _ PACKAGE Std-logic-1164 IS - logic state system (unresolved) TYPE std-ulogic IS ( U, - Uninitialized X, - Forcing Unknown O, - Forcing O l, - Forcing 1 Z, - High Impedance W, - Weak Unknown L, - Weak O H, -Weak 1 - - Dont care 2 1; - unconstrained array of std-ulogic fo

23、r use with the TYPE std-ulogic-vector IS ARRAY ( NATURAL RANGE WHEN 1 I H = WHEN OTHERS = RETURN xmap; END CASE; END; FUNCTION Tobitvector ( s : std-logic-vector ; xmap : BIT-VECTOR-IS ALIAS sv : std-logic-vector ( sLENGTH-1 DOWNTO VARIABLE result : BIT-VECTOR (sLENGH-1 DOWNTO O ); FOR i IN resultRA

24、NGE LOOP BEGIN CASE sv(i) IS WHEN 07 I cc = WHEN 1 I H = WHEN OTHERS = result(i) := xmap; END CASE; END LOOP; RETURN result; END; FUNCTION Tobitvector ( s : std-ulogic-vector; xmap : BIT-VECTOR-IS ALIAS sv : std-logic-vector ( sLENGTH-1 DOWNTO O BSI 2 April 2002 Page 15 EN 61691-22001 VARIABLE resul

25、t : BIT-VECTOR (SLENCTH-1 DOWNTO O ); FOR i IN resultRANGE LOOP BEGIN CASE sv(i) IS WHEN 07 I L = WHEN 1 I H = WHEN OTHERS = result(i) := xmap; END CASE; END LOOP; RETURN result; END; FUNCTION To-StdUlogic ( b : BIT ) RETURN BEGIN CASE b IS WHEN 07 = RETURN 07 WHEN 1 = RETURN 1 END CASE; END; FUNCTI

26、ON To-StdlogicVector (b : BIT-VECTOR ) RETURN ALIAS bv BIT-VECTOR (bLENCTH-1 DOWNTO O ) IS b; VARIABLE result : std-logic-vector (bLENGTH-1 FOR i IN resultRANGE LOOP BEGIN CASE bv (i) IS WHEN O = result(i) := O; WHEN 1 = result(i) := 1; END CASE; END LOOP; RETURN result; END; FUNCTION To-StdLogicVec

27、tor ( s : std-ulogic-vector ) RETURN std-logic-vector IS ALIAS sv : std-ulogic-vector ( sLENCTH-1 DOWNTO VARIABLE result : std-logic-vector ( sLENGTH- 1 FOR i IN RESULTRANGE LOOP END LOOP; RETURN result; BEGIN result(i) := sv(i) END: FUNCTION To-StdULogicVector (b : BIT-VECTOR ) IS ALIAS bv BIT-VECT

28、OR ( bLENCTH-1 DOWNTO O ) IS b; VARIABLE result : stdulogic-vector ( bLENGTH- 1 FOR i IN resultRANGE LOOP BEGIN CASE bv (i) IS WHEN O = result(i) := O; WHEN 1 = result(i) := 1; END CASE; END LOOP; RETURN result; O BSI 2 April 2002 Page 16 EN 61691-22001 END; FUNCTION To-StdULogicVector ( s : std-log

29、ic-vector ) RETURN stdulogic-vector IS ALIAS sv : std-logic-vector ( sLENGTH-1 DOWNTO VARIABLE result : std-ulogic-vector ( sLENC3“- 1 FOR i IN resultRANGE LOOP END LOOP; RETURN result; BEGIN result(i) := sv(i); END; - strength strippers and type convertors - tox0l FUNCTION ToXO 1 ( s : std-logic-ve

30、ctor ) RETURN ALIAS sv : std-logic-vector ( 1 TO sLENC2“ ) IS s; VARIABLE result : std-logic-vector ( 1 TO sLENGTH ); FOR i IN resultRANGE LOOP END LOOP; RETURN result; BEGIN result(i) := cvtto-x0 1 (sv(i); END; FUNCTION ToX01 ( s : std-ulogic-vector ) RETURN ALIAS sv : std-ulogic-vector ( 1 TO sLEN

31、C2“ ) IS s; VARIABLE result : stdulogic-vector ( 1 TO sLENGI“ ); FOR i IN resultRANGE LOOP END LOOP; RETURN result; BEGIN result(i) := cvtto-x0 1 (sv(i); END; FUNCTION ToX01 ( s : std-ulogic ) RETURN XO1 IS BEGIN END; RETURN (cvt-to-x0 1 (s); FUNCTION ToX01 ( b : BIT-VECTOR ) RETURN ALIAS bv : BIT-V

32、ECTOR ( 1 TO bLENC2“ ) IS b; VARIABLE result : std-logic-vector ( 1 TO bLENGTH ); FOR i IN resultRANGE LOOP BEGIN CASE bv(i) IS WHEN O = result(i) := O; WHEN 1 = result(i) := 1; END CASE; END LOOP; RETURN result; END; O BSI 2 April 2002 Page 17 EN 61691-22001 FUNCTION ToX01 ( b : BIT-VECTOR ) RETURN

33、 ALIAS bv : BIT-VECTOR ( 1 TO bLENC2“ ) IS b; VARIABLE result : stdulogic-vector ( 1 TO bLENC2“ ); FOR i IN resultRANGE LOOP BEGIN CASE bv(i) IS WHEN O = result(i) := O; WHEN 1 = result(i) := 1; END CASE; END LOOP; RETURN result; END; FUNCTION ToX01 ( b : BIT ) RETURN XO1 IS BEGIN CASE b IS WHEN O =

34、 RETURN(0); WHEN 1 = RETURN(1); END CASE; END; - to-x0lz FUNCTION TOXOlZ ( s: std-logic-vector ) RETURN ALIAS sv : std-logic-vector ( 1 TO sLENC2“ ) IS s; VARIABLE result : std-logic-vector ( 1 TO sLENGTH ); FOR i IN resultRANGE LOOP END LOOP; RETURN result; BEGIN result(i) := cvtto-x0lz (sv(i); END

35、; FUNCTION TO-XO1Z ( s : std-ulogic-vector ) RETURN ALIAS sv : std-ulogic-vector ( 1 TO sLENC2“ ) IS s; VARIABLE result : stdulogic-vector ( 1 TO sLENGI“ ); FOR i IN resultRANGE LOOP END LOOP; RETURN result; BEGIN result(i) := cvtto-x0lz (sv(i); END: FUNCTION ToXOlZ ( s : std-ulogic ) RETURN XO1Z IS

36、 BEGIN END; RETURN (cvt-to-x0 lz(s); FUNCTION ToXOlZ ( b : BIT-VECTOR ) RETURN ALIAS bv : BIT-VECTOR ( 1 TO bLENC2“ ) IS b; VARIABLE result : std-logic-vector ( 1 TO bLENGTH ); FOR i IN resultRANGE LOOP BEGIN CASE bv(i) IS O BSI 2 April 2002 Page 18 EN 61691-22001 WHEN O = result(i) := O; WHEN 1 = r

37、esult(i) := 1; END CASE; END LOOP; RETURN result; END; FUNCTION ToXOlZ ( b : BIT-VECTOR ) RETURN ALIAS bv : BIT-VECTOR ( 1 TO bLENC2“ ) IS b; VARIABLE result : stdulogic-vector ( 1 TO bLENC2“ ); FOR i IN resultRANGE LOOP BEGIN CASE bv(i) IS WHEN O = result(i) := O; WHEN 1 = result(i) := 1; END CASE;

38、 END LOOP; RETURN result; END; FUNCTION ToXOlZ ( b : BIT ) RETURN XO1Z IS BEGIN CASE b IS WHEN O = RETURN(0); WHEN 1 = RETURN(1); END CASE; END; - to-ux0 1 FUNCTION To-UXO1 ( s : std-logic-vector ) RETURN ALIAS sv : std-logic-vector ( 1 TO sLENC2“ ) IS s; VARIABLE result : std-logic-vector ( 1 TO sL

39、ENGTH ); FOR i IN resultRANGE LOOP END LOOP; RETURN result; BEGIN result(i) := cvttoi01 (sv(i); END; FUNCTION To-UXO1 ( s : std-ulogic-vector ) RETURN ALIAS sv : std-ulogic-vector ( 1 TO sLENC2“ ) IS s; VARIABLE result : stdulogic-vector ( 1 TO sLENGI“ ); FOR i IN resultRANGE LOOP END LOOP; RETURN r

40、esult; BEGIN result (i) := cvttoux01 (sv(i); END; FUNCTION To-UXO1 ( s : std-ulogic ) RETURN UXO1 IS BEGIN END; RETURN (cvt-toux0 1 (s); O BSI 2 April 2002 Page 19 EN 61691-22001 FUNCTION To-UXO1 ( b : BIT-VECTOR ) RETURN ALIAS bv : BIT-VECTOR ( 1 TO bLENC2“ ) IS b; VARIABLE result : std-logic-vecto

41、r ( 1 TO bLENGTH ); FOR i IN resultRANGE LOOP BEGIN CASE bv(i) IS WHEN O = result(i) := O; WHEN 1 = result(i) := 1; END CASE; END LOOP; RETURN result; END; FUNCTION To-UXO1 ( b : BIT-VECTOR ) RETURN ALIAS bv : BIT-VECTOR ( 1 TO bLENGTH ) IS b; VARIABLE result : std-ulogic-vector ( 1 TO bLENC2“ ) FOR

42、 i IN resultRANGE LOOP BEGIN CASE bv(i) IS WHEN O = result(i) := O; WHEN 1 = result(i) := 1; END CASE; END LOOP; RETURN result; END; FUNCTION To-UXO1 ( b : BIT ) RETURN UXO1 IS BEGIN CASE b IS WHEN O = RETURN(0); WHEN 1 = RETURN(1); END CASE; END; - edge detection FUNCTION rising-edge (SIGNAL s : st

43、d-ulogic) RETURN BEGIN RETURN (sEVENT AND (To-XOl(s) = 1) AND (ToXO l(sLAST-VALUE) = END; FUNCTION falling-edge (SIGNAL s : std-ulogic) RETURN BEGIN RETURN (sEVENT AND (To-XOl(s) = O) AND (ToXO l(sLAST-VALUE) = - object contains an unknown FUNCTION Is-X ( s : std-ulogic-vector ) RETURN BOOLEAN IS BE

44、GIN FOR i IN sRANGE LOOP WHEN U I X I CASE s(i) IS O BSI 2 April 2002 Page 20 EN 61691-22001 WHEN OTHERS = NULL; END CASE; END LOOP; RETURN FALSE; END: FUNCTION Is-X ( s : std-logic-vector ) RETURN BOOLEAN IS BEGIN FOR i IN SRANGE LOOP CASE s(i) IS WHEN U I X I WHEN OTHERS = NULL; END CASE END LOOP;

45、 RETURN FALSE; END: FUNCTION Is-X ( s : std-ulogic BEGIN ) RETURN BOOLEAN IS CASE s IS WHEN U I X I Z WHEN OTHERS = NULL; END CASE; RETURN FALSE; END; END std-logic-1164; O BSI 2 April 2002 Page 21 EN 61691-22001 Annex A Using the Std-logic-1164 Package (Informa tive) This annex is intended to be a

46、brief guide to using the a means of building models that interoperate, provided typing imposed by the VHDL language. A.l Value system The value system in Std-logic-1164 was developed to model the logic system is named “std-ulogic” where the comprising the type have a specified semantic and a interop

47、erate, one must interpret the meaning of each of Type std-ulogic is ( U, Uninitialized state X, Forcing Unlcnown etc. 07, Forcing Zero 17, Forcing One Z, High Impedance W, Weak Unlcnown L, Weak Zero H, Weak One 2 Dont Care modeling ); A.2 Handling strengths Behavioral modeling techniques rarely requ

48、ire lcnowledge “strength stripper” functions have been designed “forcing” strength counterparts. Once in forcing strength, the model can simply respond to stripping is done by using one of the following functions: ToX01 (.) To-UXO 1 (.) converts L and H to O and converts L and H to O and to X A.3 Use of the uninitialized value The U value is located in the first position of automatically initialized to U unless expressly Uninitialized values were designed to provide a means of uninitialized state since the time of system XNOR, and NOT have been designe