ECA EIA-364-109-2003 TP-109 Loop Inductance Measurement Test Procedure for Electrical Connectors (1 nH-10 nH)《TP-109 电连接器的电感(回路)测量试验程序(1 nH - 10 nH)》.pdf

《ECA EIA-364-109-2003 TP-109 Loop Inductance Measurement Test Procedure for Electrical Connectors (1 nH-10 nH)《TP-109 电连接器的电感(回路)测量试验程序(1 nH - 10 nH)》.pdf》由会员分享，可在线阅读，更多相关《ECA EIA-364-109-2003 TP-109 Loop Inductance Measurement Test Procedure for Electrical Connectors (1 nH-10 nH)《TP-109 电连接器的电感(回路)测量试验程序(1 nH - 10 nH)》.pdf（40页珍藏版）》请在麦多课文档分享上搜索。

1、 ANSI/EIA-364-109-2003 (2009) Approved: May 20, 2003 Reaffirmed: December 2, 2009 EIA STANDARD TP-109 LOOP INDUCTANCE MEASUREMENT TEST PROCEDURE FOR ELECTRICAL CONNECTORS (1 nH 10 nH) EIA-364-109 EIA-364-109May 2003 ELECTRONIC COMPONENTS, ASSEMBLIES see 2.2.4.1 for more detailed information. Unless

2、otherwise specified in the referencing document it is recommended that the following equipment settings be used: Smith chart format, set network analyzer to display inductance values, minimum of 401 measurement points, frequency span conduct both wideband and narrowband sweeps, no smoothing, averagi

3、ng set to 16 or higher. NOTE “Wideband” sweep is typically the full range of the network analyzer and “narrowband” sweep is over a limited range (for example 100 MHz wide). EIA-364-109 Page 7 4.3 Fixture measurement Position the probes to touch the interface pads of the test board characterization s

4、tructure. Measure and record the loop inductance of the fixture from the Smith chart at the frequency(s) of interest. NOTE A loop inductance vs. frequency graph may be generated through the use of data acquisition software and spreadsheet software, if specified in the referencing document. EIA-364-1

5、09 Page 8 4.4 Specimen measurement 4.4.1 Connect the probe to the fixture interface pad of the driven line with the specimen installed as shown in figure A.1. Terminate the far end of the driven line in an electrical short circuit to the return conductor(s). 4.4.2 Place the specimen a minimum of 5 c

6、m from any object that may introduce error into the measurement. 4.4.3 Measure and record the loop inductance over the specified test frequency range or discrete frequencies. 4.4.4 Calculate the specimen loop inductance by subtracting the fixture loop inductance, (see 4.3) from the specimen plus fix

7、ture loop inductance, see 4.4.3. NOTE If specified in the referencing document, a loop inductance vs. frequency graph may be generated through the use of data acquisition software and spreadsheet software. 4.4.5 If requested, repeat 4.4.1 through 4.4.4 on multiple conductors throughout the specimen.

8、 4.4.6 When additional measurements with different test frequencies or ranges are required perform the calibration step defined in 4.2, then repeat 4.4.1 through 4.4.5 as necessary. 5 Details to be specified The following details shall be specified in the referencing document: 5.1 Measurement freque

9、ncy range and/or discrete frequency(s) 5.2 Special requirements with respect to the fixture, and the short circuit, (see 2.2.1.4) construction and electrical properties of each. 5.3 Signal/ground pattern, including the number and location of signal and grounds. It is recommended that enough location

10、s within the specimen be measured to take into account the varying loop inductances within the specimen 5.4 Location of the drive signal connection point, location of the return signal connection point and connections to be made to adjacent pins, if any 5.5 Specimen environment impedance if other th

11、an 50 ohms 5.6 Plots, if desired, and Smith charts or loop inductance vs. frequency graphs EIA-364-109 Page 9 6 Test documentation Documentation shall contain the details specified in clause 5, with any exceptions, and the following: 6.1 Title of test 6.2 Test equipment used, and date of last and ne

12、xt calibration 6.3 Description of test fixture and associated calibration structures 6.4 Values and observations 6.5 Representative graphs, if available 6.6 Name of operator and date of test EIA-364-109 Page A-1 Annex A Loop inductance measurement setup (normative) A.1 Figure A.1 shows an example of

13、 a typical test equipment setup for loop inductance measurements including the equipment, cables, probes, and fixture. connectorfixturereferencestructureVector Network AnalyzerprobePort 1 Test cable driven linereturn pathshortcircuitFigure A.1 - Example of test equipment setup for loop inductance me

14、asurements EIA-364-109 Page A-2 A.2 Figure A.2 shows an example of the measurement set up for measuring the loop inductance of a fixture with a ground plane return path. The signal and ground vias are shorted together with a copper surface. The test fixture should be designed such that the signal tr

15、ace, pad interface, and copper surface provide the lowest inductance path from the probe tip to the signal and ground vias. This reference trace and pad interface should represent the same structures and geometries that will be used for the specimen measurement. Figure A.2 - Example of fixture loop

16、inductance measurement setup EIA-364-109 Page A-3 A.3 Figure A.3 shows an example of the measurement set up for measuring the loop inductance of the fixture plus specimen. The figure shows an example of the probe, pads, shorting block, and a specimen consisting of an edgecard connector. The ground p

17、ad is connected to the test board ground plane (not shown) that is in turn connected to the specimen ground contacts. It is important that the shorting block connect the specified return path conductors, but not adjacent signal pins. Figure A.3 - Example of loop inductance measurement setup EIA-364-

18、109 Page A-4 A.4 Figure A.4 shows a drawing of a microprobe contacting the bottom side of the PCB test fixture and the specimen mounted on the opposite side of the PCB. The test professional should be aware that this type of fixture may be used, but that all vias and traces should be taken into cons

19、ideration when conducting the calibration procedures. Figure A.4 - Diagram of microprobes contacting the bottom side of the printed circuit board test fixture Specimen Microprobe Fixture EIA-364-109 Page B-1 B Calibration standards and test board reference traces (informative) B.1 Calibration standa

20、rds B.1.1 For the equipment calibration, a traceable calibration impedance standard should be used for a reference baseline. Specific equipment calibration should be performed according to the manufacturers instructions. However, care should be taken as to what standards or other fixtures are used f

21、or the calibration procedure. NOTE The term “calibration” used in this document is not to be confused with the periodic factory equipment calibration. Calibration is used in the sense of characterizing the fixture so that when the “fixture plus specimen” measurement is taken, the characteristics of

22、the specimen alone can be accurately determined. B.1.2 When possible the fixture should be designed to allow the attachment of the calibration standard as close to the specimen as possible. Reflections from fixture imperfections increase measurement error. B.1.3 Printed circuit test boards should no

23、t be used as calibration standards. Because of different printed circuit board technologies, fabrication control, and material variations, it becomes difficult to insure that different board designs or fabrication techniques will have the same calibration reference for the impedance measurements. Th

24、e impedance value of “controlled impedance traces” on a printed circuit board is typically 10% or 5% of the target value. In measurements and applications, this may be an acceptable tolerance to hold, however, for calibration purposes, this should not be used as a baseline. B.1.4 The use of the trac

25、eable standard termination at the end of the test cable will allow the test fixture printed circuit board effects to be measured more accurately. The test professional will be able to accurately measure the impedance or transmission characteristic of the printed circuit board fixture, and not allow

26、the test equipment to try to compensate for any fixture discontinuities. B.1.5 Figures B.1 through B.4 show single ended test boards using SOLT (Short-Open-Load-Through) calibration trace structures. Calibration using other methods, for example TRL (Through-Reflect-Line), will require different stru

27、ctures. EIA-364-109 Page B-2 Figure B.1 Short reference trace Figure B.2 Open reference trace EIA-364-109 Page B-3 Figure B.3 Fifty ohm load reference trace Figure B.4 Transmission reference trace EIA-364-109 Page B-4 B.2 Test board reference traces Test boards shall include reference traces for mea

28、suring the frequency domain characteristics of the fixture in order to correct for fixture effects (e.g., discontinuities in impedance). Recommended test fixture configurations include: B.2.1 A reference trace ending in a via which is shorted to the return path conductor(s). The length of this refer

29、ence trace should be the same as that of the trace connected to the near end of the specimen. B.2.2 A reference trace ending in a via which is open with respect to the return path conductor(s). The length of this reference trace should be the same as that of the trace connected to the near end of th

30、e specimen. B.2.3 A reference trace terminated in the specimen environment impedance. The length of this reference trace should be the same as that of the trace connected to the near end of the specimen. B.2.4 A reference structure consisting of a through transmission trace whose length is equal to

31、the total fixture trace length for a single path, (length of the near end and far end traces). The test fixture shall provide an identical coaxial cable or probe connection at both ends. NOTE 1 This reference structure should be designed with the same configuration in which the specimen would be use

32、d in a typical application (such as footprint pads, grounds, traces, vias, etc). NOTE 2 The calibration structures above are described as terminating in a via. This is appropriate for pin-in-hole terminations, but is not appropriate for all terminations, e.g. surface mount connectors. Ideally the re

33、ference trace should terminate in the same type of pad or connection as the actual connector would experience. EIA-364-109 Page C-1 C Printed circuit board design considerations for electronics measurements (informative) This annex provides a general overview of circuit board design considerations f

34、or numerous electronics measurements, not just inductance. Although several clauses do not pertain to inductance measurements, the information is provided for the user who may design a single test board to perform multiple electronics measurements. C.1 The designer should take precautions in designi

35、ng printed-circuit boards for high-speed testing for several reasons. These include reflections due to impedance mismatches, signal attenuation due to skin effect of the narrow conductors, resonance effects due to long traces, crosstalk between traces, and others. Printed circuit board features that

36、 may be of concern include vias, SMT pads, probe interface, etc. Electrical discontinuities caused by these features are unavoidable in the test fixture(s), and shall not be overlooked as they may affect the impedance results of the specimen. This annex can not in the space allotted cover these topi

37、cs in detail, but will attempt to lay the groundwork for further analysis and design, and refer the reader to more detailed treatments of the subject. There are a number of excellent references on the subject, which are listed at the end of this annex. C.2 When the printed circuit board traces appro

38、ach critical lengths (defined later in the document), it becomes essential to design the traces to match the impedance of the test equipment to avoid inaccurate results due to reflections. Controlling the line impedance of printed circuit board traces is difficult without the use of embedded referen

39、ce planes in the board. The preferred reference plane is one connected to signal ground, but any low impedance reference will work (including a voltage plane) if it is sufficiently decoupled. The signal line impedance is determined by conductor geometry, including the trace width and thickness, dist

40、ance from the ground or other reference plane or conductor, and the dielectric constant of the board material. In the case of differential trace pairs, the spacing between the two traces is also critical. Several formulas exist for calculation of printed circuit board trace impedance, and a number o

41、f impedance calculation software tools are also available. The choice of board impedance formula is based on the conductors relative placement as well as their position in the board cross-section, some common examples of which are shown in the figures below. wthDielectricGroundbtwhGroundGroundDielec

42、tric(a)(b)Figure C.1 - Microstrip (a) and stripline (b) geometries EIA-364-109 Page C-2 C.2.1 In figure C.1 (a), a cross section of a microstrip transmission line is shown. The signal line of width w and thickness t lies on top of the surface of the dielectric layer with relative dielectric constant

43、 r(typically between 4 and 5 for glass-epoxy boards) at a height of h above a ground or other reference plane. The characteristic impedance of a signal line with such a structure is given by the following equation. 1)+=twhr8.098.5ln41.187Z0C.2.2 This value is approximate, in that it assumes that the

44、 conductor is surrounded on three sides by air; if the conductor is covered by solder mask or other material (as is typical), the higher dielectric constant of that material will lower the impedance from the value calculated using the equation. C.2.3 The stripline structure shown in figure C.1 (b) i

45、s one in which the signal line is surrounded by the dielectric material, with ground or reference planes on two sides. The characteristic impedance for the stripline structure is given by the following equation. 2) +=wtbZr8.067.04ln600C.2.4 A similar structure also exists where the conductor in ques

46、tion is inside the surface of the printed circuit board but is only adjacent to a ground or reference plane in one direction. This is referred to variously as “buried” microstrip or “covered” microstrip, and is shown in figure C.2. Figure C.2 - Buried microstrip geometry 1) Blood, William R., Jr.: M

47、ECL System Design Handbook (Phoenix, AZ: Motorola Semiconductor Products, Inc., 1988), p. 45. 2) Op. cit., p. 48. b t w h Ground Dielectric EIA-364-109 Page C-3 C.2.4.1 The characteristic impedance for this configuration is given by the following equation. 3)+=twhZr8.098.5ln600C.2.5 The equations ab

48、ove have all dealt with single-ended (unbalanced) signal lines. In the case of differential (balanced) signals, the impedance is more difficult to compute than the conventional single-ended impedance; the use of field solver software is often necessary to solve this type of problem. The use of vias

49、is to be discouraged where possible, as the capacitance of vias causes impedance mismatches and consequent reflections in the signal path. In the event that surface ground planes are used to construct stripline structures, the surface and buried ground planes should be connected together by vias spaced no more than /8 apart, to prevent resonances and other undesired effects on the printed circuit board. Typically, the value for is the highest frequency at which measurements are to be taken. C.2.6 Attenuation of