ECA EIA-364-109-2003 TP-109 Loop Inductance Measurement Test Procedure for Electrical Connectors (1 nH-10 nH).pdf

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1、 EIA STANDARD TP-109 Loop Inductance Measurement Test Procedure for Electrical Connectors (1 nH-10 nH) EIA-364-109 May 2003 Electronic Components Industry Association ANSI/EIA-364-109-2003 (R2016) Approved: May 20, 2003 Reaffirmed: April 13, 2016 EIA-364-109 NOTICE EIA Engineering Standards and Publ

2、ications are designed to serve the public interest through eliminating misunderstandings between manufacturers and purchasers, facilitating interchangeability and improvement of products, and assisting the purchaser in selecting and obtaining with minimum delay the proper product for his particular

3、need. Existence of such Standards and Publications shall not in any respect preclude any member or nonmember of ECIA from manufacturing or selling products not conforming to such Standards and Publications, nor shall the existence of such Standards and Publications preclude their voluntary use by th

4、ose other than ECIA members, whether the standard is to be used either domestically or internationally. Standards and Publications are adopted by ECIA in accordance with the American National Standards Institute (ANSI) patent policy. By such action, ECIA does not assume any liability to any patent o

5、wner, nor does it assume any obligation whatever to parties adopting the Standard or Publication. This EIA standard is considered to have International Standardization implications, but the International Electrotechnical Commission activity has not progressed to the point where a valid comparison be

6、tween the EIA standard and the IEC document can be made. This Standard does not purport to address all safety problems associated with its use or all applicable regulatory requirements. It is the responsibility of the user of this Standard to establish appropriate safety and health practices and to

7、determine the applicability of regulatory limitations before its use. (From Standards Proposal No. 4831 and reaffirmed by Standards Proposal No. 5361.06, formulated under the cognizance of the EIA CE-2.0 Committee on National Connector and Socket Standards). Published by ELECTRONIC COMPONENTS INDUST

8、RY ASSOCIATION 2016 Standards see 2.2.4.1 for more detailed information. Unless otherwise specified in the referencing document it is recommended that the following equipment settings be used: null Smith chart format,null set network analyzer to display inductance values,null minimum of 401 measurem

9、ent points,null frequency span conduct both wideband and narrowband sweeps,null no smoothing,null averaging set to 16 or higher.NOTE null “Wideband” sweep is typically the full range of the network analyzer and“narrowband” sweep is over a limited range (for example 100 MHz wide). EIA-364-109 Page 7

10、4.3 Fixture measurement Position the probes to touch the interface pads of the test board characterization structure. Measure and record the loop inductance of the fixture from the Smith chart at the frequency(s) of interest. NOTE null A loop inductance vs. frequency graph may be generated through t

11、he use of data acquisition software and spreadsheet software, if specified in the referencing document. EIA-364-109 Page 8 4.4 Specimen measurement 4.4.1 Connect the probe to the fixture interface pad of the driven line with the specimen installed as shown in figure A.1. Terminate the far end of the

12、 driven line in an electrical short circuit to the return conductor(s). 4.4.2 Place the specimen a minimum of 5 cm from any object that may introduce error into the measurement. 4.4.3 Measure and record the loop inductance over the specified test frequency range or discrete frequencies. 4.4.4 Calcul

13、ate the specimen loop inductance by subtracting the fixture loop inductance, (see 4.3) from the specimen plus fixture loop inductance, see 4.4.3. NOTE If specified in the referencing document, a loop induct ance vs. frequency graph may be generated through the use of data acquisition software and sp

14、readsheet software. 4.4.5 If requested, repeat 4.4.1 through 4.4.4 on multiple conductors throughout the specimen. 4.4.6 When additional measurements with different test frequencies or ranges are required perform the calibration step defined in 4.2, then repeat 4.4.1 through 4.4.5 as necessary. 5 De

15、tails to be specified The following details shall be specified in the referencing document: 5.1 Measurement frequency range and/or discrete frequency(s) 5.2 Special requirements with respect to the fixture, and the short circuit, (see 2.2.1.4) construction and electrical properties of each. 5.3 Sign

16、al/ground pattern, including the number and location of signal and grounds. It is recommended that enough locations within the specimen be measured to take into account the varying loop inductances within the specimen 5.4 Location of the drive signal connection point, location of the return signal c

17、onnection point and connections to be made to adjacent pins, if any 5.5 Specimen environment impedance if other than 50 ohms 5.6 Plots, if desired, and Smith charts or loop inductance vs. frequency graphs EIA-364-109 Page 9 6 Test documentation Documentation shall contain the details specified in cl

18、ause 5, with any exceptions, and the following: 6.1 Title of test 6.2 Test equipment used, and date of last and next calibration 6.3 Description of test fixture and associated calibration structures 6.4 Values and observations 6.5 Representative graphs, if available 6.6 Name of operator and date of

19、test EIA-364-109 Page A-1 Annex A Loop inductance measurement setup (normative) A.1 Figure A.1 shows an example of a typical test equipment setup for loop inductance measurements including the equipment, cables, probes, and fixture. EIA-364-109 Page A-2 A.2 Figure A.2 shows an example of the measure

20、ment set up for measuring the loop inductance of a fixture with a ground plane return path. The signal and ground vias are shorted together with a copper surface. The test fixture should be designed such that the signal trace, pad interface, and copper surface provide the lowest inductance path from

21、 the probe tip to the signal and ground vias. This reference trace and pad interface should represent the same structures and geometries that will be used for the specimen measurement. Figure A.2 - Example of fixture loop inductance measurement setup EIA-364-109 Page A-3 A.3 Figure A.3 shows an exam

22、ple of the measurement set up for measuring the loop inductance of the fixture plus specimen. The figure shows an example of the probe, pads, shorting block, and a specimen consisting of an edgecard connector. The ground pad is connected to the test board ground plane (not shown) that is in turn con

23、nected to the specimen ground contacts. It is important that the shorting block connect the specified return path conductors, but not adjacent signal pins. EIA-364-109 Page A-4 A.4 Figure A.4 shows a drawing of a microprobe contacting the bottom side of the PCB test fixture and the specimen mounted

24、on the opposite side of the PCB. The test professional should be aware that this type of fixture may be used, but that all vias and traces should be taken into consideration when conducting the calibration procedures. Microprobe Fixture Specimen Figure A.4 - Diagram of microprobes contacting the bot

25、tom side of the printed circuit board test fixture EIA-364-109 Page B-1 B Calibration standards and test board reference traces (informative) B.1 Calibration standards B.1.1 For the equipment calibration, a traceable calibration impedance standard should be used for a reference baseline. Specific eq

26、uipment calibration should be performed according to the manufacturers instructions. However, care should be taken as to what standards or other fixtures are used for the calibration procedure. NOTE null The term “calibration” used in this document is not to be confused with the periodic factory equ

27、ipment calibration. Calibration is used in the sense of characterizing the fixture so that when the “fixture plus specimen” measurement is taken, the characteristics of the specimen alone can be accurately determined. B.1.2 When possible the fixture should be designed to allow the attachment of the

28、calibration standard as close to the specimen as possible. Reflections from fixture imperfections increase measurement error. B.1.3 Printed circuit test boards should not be used as calibration standards. Because of different printed circuit board technologies, fabrication control, and material vari

29、ations, it becomes difficult to insure that different board designs or fabrication techniques will have the same calibration reference for the impedance measurements. The impedance value of “controlled impedance traces” on a printed circuit board is typically 10% or 5% of the target value. In measur

30、ements and applications, this may be an acceptable tolerance to hold, however, for calibration purposes, this should not be used as a baseline. B.1.4 The use of the traceable standard termination at the end of the test cable will allow the test fixture printed circuit board effects to be measured mo

31、re accurately. The test professional will be able to accurately measure the impedance or transmission characteristic of the printed circuit board fixture, and not allow the test equipment to try to compensate for any fixture discontinuities. B.1.5 Figures B.1 through B.4 show single ended test board

32、s using SOLT (Short-Open-Load- Through) calibration trace structures. Calibration using other methods, for example TRL (Through-Reflect-Line), will require different structures. EIA-364-109 Page B-2 Figure B.1 Short reference trace Figure B.2 Open reference trace EIA-364-109 Page B-3 Figure B.3 Fift

33、y ohm load reference trace Figure B.4 Transmission reference trace EIA-364-109 Page B-4 B.2 Test board reference traces Test boards shall include reference traces for measuring the frequency domain characteristics of the fixture in order to correct for fixture effects (e.g., discontinuities in imped

34、ance). Recommended test fixture configurations include: B.2.1 A reference trace ending in a via which is shorted to the return path conductor(s). The length of this reference trace should be the same as that of the trace connected to the near end of the specimen. B.2.2 A reference trace ending in a

35、via which is open with respect to the return path conductor(s). The length of this reference trace should be the same as that of the trace connected to the near end of the specimen. B.2.3 A reference trace terminated in the specimen environment impedance. The length of this reference trace should be

36、 the same as that of the trace connected to the near end of the specimen. B.2.4 A reference structure consisting of a through transmission trace whose length is equal to the total fixture trace length for a single path, (length of the near end and far end traces). The test fixture shall provide an i

37、dentical coaxial cable or probe connection at both ends. NOTE 1 null This reference structure should be designed with the same configuration in which the specimen would be used in a typical application (such as footprint pads, grounds, traces, vias, etc). NOTE 2 null The calibration structures above

38、 are described as terminating in a via.This is appropriate for pin-in-hole terminations, but is not appropriate for allterminations, e.g. surface mount connectors. Ideally the reference trace should terminate in the same type of pad or connection as the actual connector would experience. EIA-364-109

39、 Page C-1 C Printed circuit board design considerations for electronics measurements (informative) This annex provides a general overview of circuit board design considerations for numerous electronics measurements, not just inductance. Although several clauses do not pertain to inductance measureme

40、nts, the information is provided for the user who may design a single test board to perform multiple electronics measurements. C.1 The designer should take precautions in designing printed-circuit boards for high-speed testing for several reasons. These include reflections due to impedance mismatche

41、s, signal attenuation due to skin effect of the narrow conductors, resonance effects due to long traces, crosstalk between traces, and others. Printed circuit board features that may be of concern include vias, SMT pads, probe interface, etc. Electrical discontinuities caused by these features are u

42、navoidable in the test fixture(s), and shall not be overlooked as they may affect the impedance results of the specimen. This annex can not in the space allotted cover these topics in detail, but will attempt to lay the groundwork for further analysis and design, and refer the reader to more detaile

43、d treatments of the subject. There are a number of excellent references on the subject, which are listed at the end of this annex. C.2 When the printed circuit board traces approach critical lengths (defined later in the document), it becomes essential to design the traces to match the impedance of

44、the test equipment to avoid inaccurate results due to reflections. Controlling the line impedance of printed circuit board traces is difficult without the use of embedded reference planes in the board. The preferred reference plane is one connected to signal ground, but any low impedance reference w

45、ill work (including a voltage plane) if it is sufficiently decoupled. The signal line impedance is determined by conductor geometry, including the trace width and thickness, distance from the ground or other reference plane or conductor, and the dielectric constant of the board material. In the case

46、 of differential trace pairs, the spacing between the two traces is also critical. Several formulas exist for calculation of printed circuit board trace impedance, and a number of impedance calculation software tools are also available. The choice of board impedance formula is based on the conductor

47、s relative placement as well as their position in the board cross-section, some common examples of which are shown in the figures below. EIA-364-109 Page C-2 C.2.1 In figure C.1 (a), a cross section of a microstrip transmission line is shown. The signal line of width w and thickness t lies on top of

48、 the surface of the dielectric layer with relative dielectric constant r(typically between 4 and 5 for glass-epoxy boards) at a height of h above a ground or other reference plane. The characteristic impedance of a signal line with such a structure is given by the following equation. 1)C.2.2 This va

49、lue is approximate, in that it assumes that the conductor is surrounded on three sides by air; if the conductor is covered by solder mask or other material (as is typical), the higher dielectric constant of that material will lower the impedance from the value calculated using the equation. C.2.3 The stripline structure shown in figure C.1 (b) is one in which the signal line is surrounded by the dielectric material, with ground or reference planes on two sides. The characteristic impedance for the stripline structure is given by the following equation. 2)C.2.4 A simila