ECA 567-A-1995 VHDL Hardware Component Modeling and Interface Standard《VHDL硬件部件建模和接口标准》.pdf

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1、EIA 567-A 95 3234600 O562220 922 kW EIA STANDARD VHDL Hardware Component Modeling and Interface Standard EIA-567-A (Revision of EM-5670000) JULY 1995 ELECTRONIC INDUSTRIES ASSOCIATION ENGINEERING DEPARTMENT EIA 567-A 95 3234600 0562223 8b9 = NOTICE EIA Engineering Standards and Publications are desi

2、gned to serve the public interest through eliminating misunderstandings between manufacturers and purchasers, facilitating interchangeability and improvement of products, and assisting the purchaser in selecting and obtaining with minimum delay the proper product for his particular need. Existence o

3、f such Standards and Publications shall not in any respect preclude any member or nonmember of EIA from manufacturing or selling products not conforming to such Standards and Publications, nor shall the existence of such Standards and Publications preclude their voluntary use by those other than EIA

4、 members, whether the standard is to be used either domestically or internationally. Recommended Standards and Publications are adopted by EIA in accordance with the American National Standards Institute (ANSI) patent policy. By such action, EIA does not assume any liability to any patent owner, nor

5、 does it assume any obligation whatever to parties adopting the Recommended Standard or Publication. This EIA Standard is considered to have International Standardization implication, but the International Electrotechnical Commission activity has not progressed to the point where a valid comparison

6、between the EIA Standard and the IEC document can be made. This Standard does not purport to address all safety problems associated with its use or all applicable regulatory requirements. It is the responsibility of the user of this Standard to establish appropriate safety and health practices and t

7、o determine the applicability of regulatory limitations before its use. (From Standards Proposal No. 3051, formulated under the cognizance of the VHDL Model Standards Committee). Published by ELECTRONIC INDUSTRIES ASSOCIATION 1995 Engineering Department 2500 Wilson Boulevard Arlington, VA 22201 PRIC

8、E: Please refer to the current Catalog of EIA, JEDEC, and TIA STANDARDS and ENGINEERING PUBLICATIONS or call Global Engineering Documents, USA and Canada (1 -800-854-7179) Intemational (303-397-7956) All rights reserved Printed in U.S.A. EIA 567-A 95 lsill 3234600 O562222 7T5 EIA 567-A 95 m 3234600

9、0562223 631 M EIA567-A 1 . 2 . 3 . Introduction . 1 1.1. Scope . 1 1.2. Purpose 1 1.3. Definitions 1 1.4. Recommendations 4 Documents . 5 2.1. Applicable Documents . 5 29 . Reference Documents 5 5 29.1. 29.2. 22.3. Government . 5 Institute of Electrical and Electronic Engineers. Inc . (IEEE) Electro

10、nic Industries Association . 5 Component Model Structure 6 3.1. 3.2. Design Library . 7 3.1.1. Component Entity . 7 3.1.1.1. Signal Interface Definitions . 7 3.1.1.2. Header Definition 7 3.1.2. Architecture . 8 3.1.2.1. Architecture Types . 8 3.1.2.1.1. Behavioral Body . 8 3.1.2.1.2. Structural Body

11、 . 8 3.1.2.2. Model Fidelity 8 3.1.2.2.1. Bus Functional Model 8 3.1.2.2.1.1. Timing 8 3.1.2.2.1 .2 . Functionality . 9 3.1.2.2.2. Fully Functional Model . 9 3.1.2.3. Header Definition 9 3.1.2.4. Error Checking 9 3.1.3. Packages . 9 3.1.3.1. Header Definition 9 3.1.4. Design Configurations . 9 3.1.4

12、.1. Header Definition 10 Testbench Design Files 10 3.2.1. Design File Organization 10 3.2.2. Waveform i_clk).When the setup constraint represents a single STD-LOGIC type the element subtype declaration shall be of type TIME. When the setup constraint applies to a STD-LOGIC-VECTOR, the element subtyp

13、e declaration shall be of type SETUP-VECTOR. 14 EIA 567-A 95 3234600 0562243 657 EIA567-A 4.5.5. Hold liming Violations When a signal changes its value within a time span less than the hold time referenced to another signal and MGENERATION is TRUE, a timing violation message shall be issued. A hold

14、constraint of a component model shall have at least one element declaration of type TIME that defaults to O ns, and shall define the worst case hold time of the signal in relationship to another signai. The element dedaration shall be used as piace holders for hold time: The element declaration shal

15、l be included in the timing record called MODEL-TIMES that shall be defined in the component riming view package. Each hold constraint shall have an element declaration. The element declarations identifier shall follow the convention of starting with the characters “H-“ followed by the signal name o

16、f the data signal followed by another “-“ and then the reference signal (e.g., H-data-clk).When the hold constraint represents a single STD-LOGIC type the element subtype declaration shall be of type TIME. When the hold constraint applies to a STD-LOGIC-VECTOR, the element subtype declaration shall

17、be of type HOLD-VECTOR. 4.5.6. Pulse Width Timing Violations When a signals pulse width is greater than maximum specified limits or less than minimum specified limits and MGENERATION is TRUE, a timing violation message shall be issued. A pulse constraint of a component model shall have at least one

18、element declaration of type TIME that defaults to O ns, and shall define the worst case pulse constraint (minimum or maximum) time of the signal. The element declaration shall be used as place holders for pulse width times. The element dedaration shall be included in the timing record called MODEL-T

19、IMES which shall be defined in the componerzr timing viert. package. Each pulse width constraint shall have an element declaration. The element declarations identifier shall follow the convention of starting with the characters pertinent to the constraint. as shown in Table 4-3. followed by the sign

20、al name (e-g PWL-min-data-clk).When the pulse consrraint represents a single STD-LOGIC type, the element subtype declaration shrill be of type TIME. When the pulse width constraint applies to i1 STD-LOGIC-VECTOR, the element subtype declaration shall be of type PULSE-VECTOR. 15 - - EIA 567-A 95 3234

21、600 0562242 593 W Prefm String “PWH-min-“ “ PWL-min-“ “PWH-max-“ “PWL-maX-“ . Meaning minimim pulse width high minimim pulse width low maximum pulse width high . maximum pulse width low Table 4-3. Puise Width Prefixes Prefix String “CY C-min-“ 4.5.7. Signal Cycle Time Violations When a specified sig

22、nals cycle time is less than its limits and MGENEUTION is TRUE, a timing violation message shall be issued. A cycle constraint of a component model shall have at least one element declaration of type TLME that defaults to O ns, and shall define the worst case cycle time of the signal. The element de

23、claration shall be used as place holders for cycle time. The element declaration shall be included in the timing record called MODEL-TIMES which shall be defined in the component timing view package. Each cycle consuaint shall have an element declaration. The element declarations identifier shall fo

24、llow the convention of starting with the characters pertinent to the constraint, as shownin Table 4- 4, followed by the signai name of the signai (e.g., CYC-minclk).When the cycle constraint represents a single STDLOGIC type the element subtype declaration shall be of type TIME. When the cycle time

25、consuaint applies to a STD-LOGIC-VECTOR, the element subtype declaration shall be of type CYCLE-VECTOR. Meaning minimim cycle high Table 4-4. Cycle Time Prefixes 4.6. Electronic Data Sheet An Electronic Data Sheet for a component model consists of an electricul view*, a timing view, and a physical v

26、iew. The timing view shall be provided as part of the component model. It is recommended that an electrical view and a physicui iiew also be provided. 16 EIA 567-A 75 I 3234600 0562243 42T I EIA567-A EIA567EV Component Electrical View EIA567TV Component Timing View EIA567PV Component Physical View E

27、lectronic Data Sheet -1 Figure 4- 1. Electronic Data Sheet Each view is implemented using a standard package and a package specific to the component being modeled. The next three sections describe the standard packages EIA567EV, EIA567TV, and EIA567PV. The following three sections define requirement

28、s for the component-specific views and packages. 4.6.1. EIA567EV - Electrical View Package - Recommendation The EIA567EV package, which supports the electrical view, shall be used and not modified. It contains the type declarations for the following physical units: RESISTANCE 0 CAPACITANCE TEMPERATU

29、RE VOLTAGE 0 CURRENT POWER It contains the type definition EV-SIGNAL-LIMIT. EV-SIGNAL-LUIIT is a record with element declarations as shown in Table 4-5. Table 4-5. EIA567EV EV-SIGNAL-LIMIT Record 17 EIA 567-A 95 3234600 0562244 36b Element Declaration Vmin VmaX Imax Pma The package also includes the

30、 type definition IO-DRIVER-TYPES-TYPE. IO-DRIVER-TYPES-TYPE is an unconstrained array of EV-SIGNALLIMIT indexed by natural. The package contains the type definition POWERLIMIT. POWER-LIMTT is a record with element declarations as shown in Tabie 4-6. Type VOLTAGE VOLTAGE CURRENT POWER The package als

31、o includes the type defintition POWERLIST-TYPE. POWERLISTTYPE is an unconstrained array of POWERLIMIT indexed by natural. This package is included in Appendix B of this specification. 4.6.2. EIA56TTV - Timing View Package The EIA567TV package, which suppons the timing view, shall be used and not mod

32、ified. The type DELAY is defined within the E1.4567TV package as an enumeration type with the following ordering from left: (tlh. thl, tlz. tzh, thz, ttl) Table 4-7 describes the enumerated values of DELAY. 18 EIA 5b7-A 95 I 3234b00 0562245 2T2 I Enumeration tlh thl tlz tzh thz tZl EIA567-A Descript

33、ion O to 1 transition time 1 to O transition time O to Z,W,H,L transition time Z,W,H,L to O transition urne 1 to Z,W,H,L transition time Z,W,H,L to 1 transition time The attribute ARTIFICIAL is defined as string( 1 to lo). The type TIME-VECTOR is defined within the EIA567TV package as an array index

34、ed by DELAY of TIME. TIME-VECTOR may be used to specify the delays to be applied to each pin of a vector (e.g, a bus) if all of the pins have identical delay specifications. The type TIME-VECTORS is defined within the EIA567TV package as an array indexed by natural of TIME-VECTOR. TIME-VECTORS may b

35、e used to specify the delays to be applied to each pin of a vector when required, even if all of the pins have identicai delay specifications. This type may also be used to specify different path delays to individual outputs from differing inputs. If used in this way for vectors, each pin element of

36、 the vector must have its own entry identifier. The type OPERATING-POINT-TYPE is defined in the EIA567TV package as an enumerated type with the foilowing elements in order: (MINIMUM. NOMINAL. MAXIMUM) All time entries that relate to the minimum operuring poilu shall represent the fastest operationai

37、 characterisitics published by the compniieizr manufacturer. All time entries that relate to the nominal opercring poinr shall represent the nominal operational characterisitics published by the componenr manufacturer. All time entries that relate to the maximum operuring point shall represent the s

38、lowest operational characterisitics published by the component manufacturer. The type SETUP-VECTOR is defined within the EIA567TV package as un unconstrained array indexed by natural of TIME. The type HOLD-VECTOR is defined within the EIA567TV package as an unconstrained array indexed by natural of

39、TIME. 19 EIA 563-A 95 D 3234600 05b22Yb 139 W EI-A The type CYCLE-VECTOR is defined within the EIA567TV package as an unconstrained array indexed by natural of TIME. The type PULSE-VEcTOR is defined within the EIA567TV package as an unconstrained array indexed by natural of TIME. The type WD-VECTOR

40、is defined within the EIA567TV package as an unconstrained array indexed by natural of TIME. The type LD-VECTOR is defined within the EIA567TV package as an unconstrained array indexed by natural of TIME. An element of type TIME may be used to speciQ the required parameters to be applied to each pin

41、 of a vector if all of the pins have identicai parameters. SETUP-VECTOR, HOLD-VECTOR, CYCLE-VECTOR, and PULSE-VEff OR may be used to specify parameters to be applied to each pin of a vector when required, even if ail of the pins have identical parameters. These types may also be used to specify mult

42、iple test parameters for individual pins. If used in this way for vectors, each pin element of the vector must have its own entry identifier. This package is included in Appendix B of this specification. 4.6.3. The EIA567PV package, which supports the physical view, shall be used and not modified. E

43、IA567PV - Physical View Package - Recommendation The subtype EIA-STRING is defined within the EIA567PV package as a string ranging from 1 to 28. The type PIN-RECORD is defined within the EIA567PV package as a record with two element deciarations. The first element declaration is PIN-ID of EIA-STRING

44、. The second is SIGNAL-NAME of IA-STRING. This package is included in Appendix B of this specification. 4.6.4. Component Electrical View Package - Recommendation A coniponenr model shall have an elecrricai iieai- package with information describing its electrical characteristics. 20 EIA 5b7-A 95 I 3

45、234600 0562247 075 Elm-A Signai Characterisitics Power Characterisitics c c Drive (Voh 43 loh, Vol Q 101) Test Load Input Thresholds Leakage Currents Pin Loads Operating Voltage Range Maximum Supply Current Number of Supplies Figure 4-2. Electrical View 4.6.4.1. Input Output Driver Characterisitics

46、- Recommendation Each unique type of INPUT or OUTPUT driver used at the interface of the component model shaii have its electrical characteristics defined in a model-specific package. A constant called IO-DRIVERTYPES , defined of type IO-DRIVER-TY PESTY PE shall be used. It shall be defined in the c

47、omponent electrical view package as an unconstrained array indexed by natural of EV-SIGNAL-LIMIT. The index O slice shall have all entries set to the left value of the record element type. For all other indexed slices, any enuies that ,are not relevant to the driver described shall assign the record

48、 elements the appropriate base type left value (Example: An input buffer shall have all output related values set to left). The constant shall be assigned actuais in the component electrical view package or package body. 4.6.4.2. Pin List - Recommendation A component models signal pins, power pins.

49、and iio connccr pins shall be listed in an enurneration type called PIN-LIST. The type shall be declared in the coponenf electrical view package. The enumeration literal shall be formed by concatenating the signal name with the letters “ndx“. if the signai represents an array of signals then the enumeration literal shall be formed by contcatenating the signal name with iin “_“ followed by the unique signal index number followed by the letters “ndx“. 4.6.4.3. Pin List to Driver Type Mapping - Recommendation A compone