DLA SMD-5962-99524 REV C-2013 MICROCIRCUIT MEMORY DIGITAL CMOS ELECTRICALLY ALTERABLE (IN-SYS REPROGRAMMABLE) 3 3 V - 256 MACROCELL PROGRAMMABLE LOGIC DEVICE MONOLITHIC SILICON.pdf

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1、 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Table I parameter changes; CIN, tHPT, tSPT, tIHPT, tISPT and tSLEW for device 01, editorial changes Table I and Terminal connections. ksr 01 - 06 - 05 Raymond Monnin B Boilerplate update and part of five year review. tcr 05-12-15 Raymond Monnin C

2、 Correct 1.3 and 3.10 to include Tuse = +55 degrees C for Data Retention. Update 3.9 and 3.10 to include sampling 20(0) for Endurance and Data Retention. Update boilerplate to current MIL-PRF-38535 requirements. Remove all Class M references. lhl 13-11-12 Charles F. Saffle REV C C C C C C C C SHEET

3、15 16 17 18 19 20 21 22 REV STATUS REV C C C C C C C C C C C C C C OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PMIC N/A PREPARED BY Kenneth Rice DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 http:/www.landandmaritime.dla.mil STANDARD MICROCIRCUIT DRAWING CHECKED BY Jeff Bowling THIS DRAWING I

4、S AVAILABLE FOR USE BY All DEPARTMENTS AND AGENCIES OF THE DEPARTMENT OF DEFENSE APPROVED BY Raymond Monnin MICROCIRCUIT, MEMORY, DIGITAL, CMOS, ELECTRICALLY ALTERABLE (IN-SYS REPROGRAMMABLE), 3.3 V - 256 MACROCELL, PROGRAMMABLE LOGIC DEVICE, MONOLITHIC SILICON DRAWING APPROVAL DATE 00-05-11 AMSC N/

5、A REVISION LEVEL C SIZE A CAGE CODE 67268 5962-99524 SHEET 1 OF 22 DSCC FORM 2233 APR 97 5962-E034-14 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-99524 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVI

6、SION LEVEL C SHEET 2 DSCC FORM 2234 APR 97 1. SCOPE 1.1 Scope. This drawing documents two product assurance class levels consisting of high reliability (device class Q) and space application (device class V). A choice of case outlines and lead finishes are available and are reflected in the Part or

7、Identifying Number (PIN). When available, a choice of Radiation Hardness Assurance (RHA) levels are reflected in the PIN. 1.2 PIN. The PIN is as shown in the following example: 5962 - 99524 01 Q X X Federal stock class designator RHA designator (see 1.2.1) Device type (see 1.2.2) Device class design

8、ator Case outline (see 1.2.4) Lead finish (see 1.2.5) / (see 1.2.3) / Drawing number 1.2.1 RHA designator. Device classes Q and V RHA marked devices meet the MIL-PRF-38535 specified RHA levels and are marked with the appropriate RHA designator. A dash (-) indicates a non-RHA device. 1.2.2 Device typ

9、e(s). The device type(s) identify the circuit function as follows: Device type Generic number Circuit function Toggle Speed (Mhz) 01 CY37256VP 256 Macrocell CPLD 66 1.2.3 Device class designator. The device class designator is a single letter identifying the product assurance level as follows: Devic

10、e class Device requirements documentation Q or V Certification and qualification to MIL-PRF-38535 1.2.4 Case outline(s). The case outline(s) are as designated in MIL-STD-1835 and as follows: Outline letter Descriptive designator Terminals Package style Z See figure 1 160 Quad flat package 1.2.5 Lead

11、 finish. The lead finish is as specified in MIL-PRF-38535 for device classes Q and V. 1.3 Absolute maximum ratings. 1/ Supply voltage range (VCC) - -0.5 V dc to +4.6 V dc Programming supply voltage range (VPP) - 3.0 V dc to 3.6 V dc DC input voltage range - -0.5 V dc to +7.0 V dc Maximum power dissi

12、pation - 2.0 W 2/ Lead temperature (soldering, 10 seconds) - +260C Thermal resistance, junction-to-case (JC): Case outline Z - 7.2 C/W Junction temperature (TJ) - +150C 3/ Storage temperature range - -65C to +150C Endurance - 25 erase/write cycles (minimum) Data retention (at Tuse = +55C) - 10 years

13、 (minimum) _ 1/ Stresses above the absolute maximum rating may cause permanent damage to the device. Extended operation at the maximum levels may degrade performance and affect reliability. 2/ Must withstand the added PD due to short circuit test (e.g., IOS). 3/ Maximum junction temperature shall no

14、t be exceeded except for allowable short duration burn-in screening conditions in accordance with method 5004 of MIL-STD-883. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-99524 DLA LAND AND MARITIME COLUMB

15、US, OHIO 43218-3990 REVISION LEVEL C SHEET 3 DSCC FORM 2234 APR 97 1.4 Recommended operating conditions. 4/ Case operating temperature Range (TC) - -55C to +125C Supply voltage relative to ground(VCC) - +3.0 V dc minimum to +3.6 V dc maximum Ground voltage (GND) - 0 V dc Input high voltage (VIH) - 2

16、.0 V dc minimum Input low voltage (VIL) - 0.8 V dc maximum 2. APPLICABLE DOCUMENTS 2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a part of this drawing to the extent specified herein. Unless otherwise specified, the issues of these

17、 documents are those cited in the solicitation or contract. DEPARTMENT OF DEFENSE SPECIFICATION MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for. DEPARTMENT OF DEFENSE STANDARDS MIL-STD-883 - Test Method Standard Microcircuits. MIL-STD-1835 - Interface Standard Electroni

18、c Component Case Outlines. DEPARTMENT OF DEFENSE HANDBOOKS MIL-HDBK-103 - List of Standard Microcircuit Drawings. MIL-HDBK-780 - Standard Microcircuit Drawings. (Copies of these documents are available online at http:/quicksearch.dla.mil or from the Standardization Document Order Desk, 700 Robbins A

19、venue, Building 4D, Philadelphia, PA 19111-5094.) 2.2 Non-Government publications. The following document(s) form a part of this document to the extent specified herein. Unless otherwise specified, the issues of the documents are the issues of the documents cited in the solicitation. ASTM INTERNATIO

20、NAL (ASTM) ASTM Standard F1192 - Standard Guide for the Measurement of Single Event Phenomena from Heavy Ion Irradiation of Semiconductor Devices. (Applications for copies of ASTM publications should be addressed to: ASTM International, 100 Barr Harbor Drive, PO Box C700, West Conshohocken, PA 19428

21、-2959; http:/www.astm.org.) JEDEC SOLID STATE TECHNOLOGY ASSOCIATION JEDEC JESD78 - IC Latch-Up Test. (Applications for copies should be addressed to the JEDEC Solid State Technology Association 2011, 3103 North 10th Street, Suite 240 South, Arlington, VA 22201-2107; http:/www.jedec.org.) (Non-Gover

22、nment standards and other publications are normally available from the organizations that prepare or distribute the documents. These documents also may be available in or through libraries or other informational services.) 2.3 Order of precedence. In the event of a conflict between the text of this

23、drawing and the references cited herein, the text of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a specific exemption has been obtained. _ 4/ All voltage values in this drawing are with respect to VSS. Provided by IHSNot for Res

24、aleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-99524 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL C SHEET 4 DSCC FORM 2234 APR 97 3. REQUIREMENTS 3.1 Item requirements. The individual item requirements for device cl

25、asses Q and V shall be in accordance with MIL-PRF-38535 as specified herein, or as modified in the device manufacturers Quality Management (QM) plan. The modification in the QM plan shall not affect the form, fit, or function as described herein. 3.2 Design, construction, and physical dimensions. Th

26、e design, construction, and physical dimensions shall be as specified in MIL-PRF-38535 and herein for device classes Q and V 3.2.1 Case outline(s). The case outline(s) shall be in accordance with 1.2.4 herein and figure 1. 3.2.2 Terminal connections. The terminal connections shall be as specified on

27、 figure 2. 3.3 Electrical performance characteristics and postirradiation parameter limits. Unless otherwise specified herein, the electrical performance characteristics and postirradiation parameter limits are as specified in table I and shall apply over the full case operating temperature range. 3

28、.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table IIA. The electrical tests for each subgroup are defined in table I. 3.5 Marking. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturers PIN may also be mark

29、ed. For packages where marking of the entire SMD PIN number is not feasible due to space limitations, the manufacturer has the option of not marking the “5962-“ on the device. For RHA product using this option, the RHA designator shall still be marked. Marking for device classes Q and V shall be in

30、accordance with MIL-PRF-38535. 3.5.1 Certification/compliance mark. The certification mark for device classes Q and V shall be a “QML“ or “Q“ as required in MIL-PRF-38535. 3.6 Certificate of compliance. For device classes Q and V, a certificate of compliance shall be required from a QML-38535 listed

31、 manufacturer in order to supply to the requirements of this drawing (see 6.6.1 herein). The certificate of compliance submitted to DLA Land and Maritime-VA prior to listing as an approved source of supply for this drawing shall affirm that the manufacturers product meets, for device classes Q and V

32、, the requirements of MIL-PRF-38535 and herein. 3.7 Certificate of conformance. A certificate of conformance as required for device classes Q and V in MIL-PRF-38535 shall be provided with each lot of microcircuits delivered to this drawing. 3.8 Processing CPLDs. All testing requirements and quality

33、assurance provisions herein shall be satisfied by the manufacturer prior to delivery. 3.8.1 Erasure of CPLDs. When specified, devices shall be erased in accordance with the procedures and characteristics specified in 4.6 herein. 3.8.2 Programmability of CPLDs. When specified, devices shall be progra

34、mmed to the specified pattern using the procedures and characteristics specified in 4.7 herein. 3.8.3 Verification of erasure or programmed CPLDs. When specified, devices shall be verified as either programmed (see 4.7 herein) to the specified pattern or erased (see 4.6 herein). As a minimum, verifi

35、cation shall consist of performing a functional test (subgroup 7) to verify that all bits are in the proper state. Any bit that does not verify to be in the proper state shall constitute a device failure, and shall be removed from the lot. 3.9 Endurance. A reprogrammability test shall be completed a

36、s part of the vendors reliability monitor. This reprogrammability test shall be done only for initial characterization and after any design or process changes which may affect the reprogrammability of the device using 20(0) sampling. The methods and procedures may be vendor specific, but shall be un

37、der document control and shall be made available upon request. 3.10 Data retention. A data retention stress test shall be completed as part of the vendors reliability monitors. This test shall be done for initial characterization and after any design or process change which may affect data retention

38、 using 20(0) sampling. The methods and procedures may be vendor specific, but shall guarantee 10 years minimum at Tuse = +55C. The vendors procedure shall be kept under document control and shall be made available upon request by the preparing or acquiring activity, along with the test data. Provide

39、d by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-99524 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL C SHEET 5 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics. Test Symbol Condi

40、tions 3.0 V VCC 3.6 V -55oC TC +125oC unless otherwise specified Group A Subgroups Device type Limits Unit Min Max High Level output voltage VOH VCC = 3.0 V, VIL = 0.8V IOH = -3.0 mA, VIH = 2.0 V 1/ 1, 2, 3 All 2.4 V Low level output voltage VOL VCC = 3.0 V, IOL = 6.0 mA VIL = 0.8 V, VIH = 2.0 V 1/

41、0.5 V High level input voltage 2/ VIH 2 5.5 V Low level input voltage 2/ VIL -0.5 0.8 V Input load current IIX VIN = 0 V or VCC, with Busshold off -10 +10 A Output leakage current IOZ VCC = 3.6 V VO = GND or VCC, Output disabled, Busshold off -50 +50 A Output short circuit current 3/ 4/ IOS VCC = 3.

42、6 V, VOUT = 0.5 V -30 -160 mA Power supply current 5/ ICC VCC = 3.6 V, IOUT = 0 mA, VIN = 0 V and 3.6 V f = 1.0 MHz 300 mA Input bus hold low sustained current 3/ IBHL VCC = 3.0 V,VIL = 0.8 V +75 A Input bus hold high sustained current 3/ IBHH VCC = 3.0 V,VIH = 2.0 V -75 A Input bus hold low sustain

43、ed overdrive current 3/ IBHLO VCC = 3.6 V +500 A Input bus hold high sustained overdrive current 3/ IBHHO VCC = 3.6 V -500 A See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-9952

44、4 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL C SHEET 6 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics - Continued. Test Symbol Conditions 3.0 V VCC 3.6 V -55oC TC +125oC unless otherwise specified Group A Subgroups Device type Limits Unit Min Max Input capa

45、citance 3/ CIN See 4.4.1e, VIN = 3.3 V, f = 1 MHz, TA = 25C 4 01 8 pF Output capacitance 3/ COUT 12 Dual functional pin capacitance 3/ CDP 16 Functional test See 4.4.1c 7,8A,8B 01 Input to combinatorial output 6/ 7/ 8/ tPD See figures 3 and 4 (circuit A) 9, 10, 11 01 20 ns Input to output through tr

46、ansparent input or output latch 3/ 6/ 7/ 8/ tPDL See figures 3 and 4 (circuit A) 9, 10, 11 01 22 Input to output through transparent input and output latch 3/ 6/ 7/ 8/ tPDLL 01 24 01 24 Input to output enable see figure 3 test waveforms 3/ 6/ 7/ 8/ tEA See figures 3 and 4 (circuit B) 01 24 01 24 Input to output disable see figure 3 test waveforms 3/ 6/ 7/ tER 01 24 Clock or latch enable input high time 3/ 6/ tWH See figures 3 and 4 (circuit A) 01 5 Clock or latch enable input low time 3/ 6/ tWL 01 5 Input register or latch set-up time 3/ 6/ tIS 01 4 In