DLA SMD-5962-98510 REV B-2007 MICROCIRCUIT MEMORY DIGITAL CMOS 36000 GATE PROGRAMMABLE LOGIC ARRAY MONOLITHIC SILICON《微型电路 带记忆力 数字型CMOS 36000门可编程逻辑器件 单块硅》.pdf

《DLA SMD-5962-98510 REV B-2007 MICROCIRCUIT MEMORY DIGITAL CMOS 36000 GATE PROGRAMMABLE LOGIC ARRAY MONOLITHIC SILICON《微型电路 带记忆力 数字型CMOS 36000门可编程逻辑器件 单块硅》.pdf》由会员分享，可在线阅读，更多相关《DLA SMD-5962-98510 REV B-2007 MICROCIRCUIT MEMORY DIGITAL CMOS 36000 GATE PROGRAMMABLE LOGIC ARRAY MONOLITHIC SILICON《微型电路 带记忆力 数字型CMOS 36000门可编程逻辑器件 单块硅》.pdf（40页珍藏版）》请在麦多课文档分享上搜索。

1、 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Table IA, Capacitance test - moved packages to show correct capacitance. Added conversion table for Y and Z package. Redrew case U figure 1 to correct row names. Made changes to Table IIA. ksr 99-04-09 Raymond Monnin B Boilerplate update, part of

2、 5 year review. ksr 07-06-12 Robert M. Heber REV B B B B B SHEET 35 36 37 38 39 REV B B B B B B B B B B B B B B B B B B B B SHEET 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 REV STATUS REV B B B B B B B B B B B B B B OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PMIC N/A PREPARED

3、BY Kenneth Rice DEFENSE SUPPLY CENTER COLUMBUS STANDARD MICROCIRCUIT DRAWING CHECKED BY Jeff Bowling COLUMBUS, OHIO 43218-3990 http:/www.dscc.dla.mil THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS APPROVED BY Raymond Monnin AND AGENCIES OF THE DEPARTMENT OF DEFENSE DRAWING APPROVAL DATE 96 - 0

4、6 - 24 MICROCIRCUIT, MEMORY, DIGITAL, CMOS, 36000 GATE PROGRAMMABLE LOGIC ARRAY, MONOLITHIC SILICON AMSC N/A REVISION LEVEL B SIZE A CAGE CODE 67268 5962-98510 SHEET 1 OF 39 DSCC FORM 2233 APR 97 5962-E319-07 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from I

5、HS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-98510 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 2 DSCC FORM 2234 APR 97 1. SCOPE 1.1 Scope. This drawing documents three product assurance class levels consisting of space application (device class V), high reliab

6、ility (device classes M and Q), and nontraditional performance environment (device class N). A choice of case outlines and lead finishes are available and are reflected in the Part or Identifying Number (PIN). When available, a choice of Radiation Hardness Assurance (RHA) levels is reflected in the

7、PIN. For device class N, the user is cautioned to assure that the device is appropriate for the application environment. 1.2 PIN. The PIN is as shown in the following example: 5962 - 98510 01 Q X C Federal stock class designator RHA designator (see 1.2.1) Device type (see 1.2.2)Device class designat

8、orCase outline (see 1.2.4) Lead finish (see 1.2.5) / (see 1.2.3) / Drawing number 1.2.1 RHA designator. Device classes N, Q, and V RHA marked devices meet the MIL-PRF-38535 specified RHA levels and are marked with the appropriate RHA designator. A dash (-) indicates a non-RHA device. 1.2.2 Device ty

9、pe(s). The device type(s) identify the circuit function as follows: Device type Generic number Circuit function Access time 01 XQ4036XL-3 36,000 gate programmable array 3.0 ns 1.2.3 Device class designator. The device class designator is a single letter identifying the product assurance level as fol

10、lows: Device class Device requirements documentation M Vendor self-certification to the requirements for MIL-STD-883 compliant, non-JAN class level B microcircuits in accordance with MIL-PRF-38535, appendix A N Certification and qualification to MIL-PRF-38535 with a nontraditional performance enviro

11、nment (encapsulated in plastic) Q or V Certification and qualification to MIL-PRF-38535 1.2.4 Case outline(s). The case outline(s) are as designated in MIL-STD-1835, JEDEC Publication 95, and as follows: Outline letter Descriptive designator Terminals Package style X CMGA36-P411 411 Pin grid array p

12、ackage Y See figure 1 228 Quad flat package Z See figure 1 228 Quad flat package U LBGA-B-352 352 Ball grid array with four rows on each side (plastic) (JEDEC MO-192-BAR-2 ) T PQFP-G-240 240 Quad flat package (JEDEC MS-029-GA ) with heat sink molded in the package (plastic) 1.2.5 Lead finish. The le

13、ad finish is as specified in MIL-PRF-38535 for device classes N, Q, and V. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-98510 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET

14、 3 DSCC FORM 2234 APR 97 1.3 Absolute maximum ratings. 1/ 2/ Supply voltage range to ground potential (VCC) - -0.5 V dc to +4.0 V dc DC input voltage range ( VIN) - -0.5 V to 5.5V Voltage applied to three-state output(VTS) - -0.5 V to 5.5V Lead temperature (soldering, 10 seconds) - +260C Power dissi

15、pation (PD ) - 2.0 W Thermal resistance, junction-to-case (JC): Case outline X - See MIL-STD-1835 Case outlines Y, Z - 20C/W 3/ Case outlines U - 0.8C/W 3/ Case outlines T - 1.5C/W 3/ Junction temperature (TJ) for ceramic packages - +150C 4/ Junction temperature (TJ) for plastic packages - +125C 4/

16、Storage temperature range - -65C to +150C 1.4 Recommended operating conditions. Supply voltage relative to ground(VCC) - +3.0 V dc minimum to +3.6 V dc maximum Input high voltage ( VIH) - 50% of VCCto 5.5 V Input low voltage (VIL)- 0V to 30% of VCCMaximum input signal transition time (tIN) - 250 ns

17、Case operating temperature range (TC)- -55C to +125C Junction operating temperature range (TJ) - -55C to +125C for Plastic packages 1.5 Digital logic testing for device classes N, Q and V. Fault coverage measurement of manufacturing logic tests (MIL-STD-883, test method 5012) - 99.9 percent 2. APPLI

18、CABLE DOCUMENTS 2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a part of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the solicitation or contract. DEPARTM

19、ENT OF DEFENSE SPECIFICATION MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for. DEPARTMENT OF DEFENSE STANDARDS MIL-STD-883 - Test Method Standard Microcircuits. MIL-STD-1835 - Interface Standard Electronic Component Case Outlines. DEPARTMENT OF DEFENSE HANDBOOKS MIL-HDBK

20、-103 - List of Standard Microcircuit Drawings. MIL-HDBK-780 - Standard Microcircuit Drawings. (Copies of these documents are available online at http:/assist.daps.dla.mil/quicksearch/ or http:/assist.daps.dla.mil or from the Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Phila

21、delphia, PA 19111-5094.) 1/ All voltage values in this drawing are with respect to VSS2/ Stresses above the absolute maximum rating may cause permanent damage to the device. Extended operation at the maximum levels may degrade performance and affect reliability. 3/ When a thermal resistance for this

22、 case is specified in MIL-STD-1835 that value shall supersede the value indicated herein. 4/ Maximum junction temperature shall not be exceeded except for allowable short duration burn-in screening conditions in accordance with method 5004 of MIL-STD-883. Provided by IHSNot for ResaleNo reproduction

23、 or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-98510 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 4 DSCC FORM 2234 APR 97 2.2 Non-Government publications. The following documents form a part of this document to the e

24、xtent specified herein. Unless otherwise specified, the issues of these documents are those cited in the solicitation. AMERICAN SOCIETY FOR TESTING AND MATERIALS (ASTM) ASTM Standard F1192-00 - Standard Guide for the Measurement of Single Event Phenomena from Heavy Ion Irradiation of Semiconductor D

25、evices. (Applications for copies of ASTM publications should be addressed to: ASTM International, PO Box C700, 100 Barr Harbor Drive, West Conshohocken, PA 19428-2959; http:/www.astm.org.) ELECTRONICS INDUSTRIES ALLIANCE (EIA) JEDEC Standard EIA/JESD78 - IC Latch-Up Test. JEDEC Publication 95 - Regi

26、stered and Standard Outlines for Semiconductor Devices (Copies of these documents are available online at www.jedec.org/ or from the Electronics Industries Alliance, 2500 Wilson Boulevard, Arlington, VA 22201-3834). (Non-Government standards and other publications are normally available from the org

27、anizations that prepare or distribute the documents. These documents also may be available in or through libraries or other informational services.) 2.3 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text of this drawing takes pr

28、ecedence. Nothing in this document, however, supersedes applicable laws and regulations unless a specific exemption has been obtained. 3. REQUIREMENTS 3.1 Item requirements. The individual item requirements for device classes N, Q, and V shall be in accordance with MIL-PRF-38535 and as specified her

29、ein or as modified in the device manufacturers Quality Management (QM) plan. The modification in the QM plan shall not affect the form, fit, or function as described herein. The individual item requirements for device class M shall be in accordance with MIL-PRF-38535, appendix A for non-JAN class le

30、vel B devices and as specified herein. 3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified in MIL-PRF-38535 and herein for device classes N, Q, and V or MIL-PRF-38535, appendix A and herein for device class M. 3.2.1 Case outline(

31、s). The case outline(s) shall be in accordance with 1.2.4 herein and figure 1. 3.2.2 Terminal connections. The terminal connections shall be as specified on figure 2. 3.2.3 Logic block diagram. The logic block diagram shall be as specified on figure 3. 3.3 Electrical performance characteristics and

32、postirradiation parameter limits. Unless otherwise specified herein, the electrical performance characteristics and postirradiation parameter limits are as specified in table I and shall apply over the full case operating temperature range. 3.4 Electrical test requirements. The electrical test requi

33、rements shall be the subgroups specified in table IIA. The electrical tests for each subgroup are defined in table I. 3.5 Marking. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturers PIN may also be marked. For packages where marking of the entire SMD PIN numbe

34、r is not feasible due to space limitations, the manufacturer has the option of not marking the “5962-“ on the device. For RHA product using this option, the RHA designator shall still be marked. Marking for device classes N, Q, and V shall be in accordance with MIL-PRF-38535. Marking for device clas

35、s M shall be in accordance with MIL-PRF-38535, appendix A. 3.5.1 Certification/compliance mark. The certification mark for device classes N, Q, and V shall be a “QML“ or “Q“ as required in MIL-PRF-38535. The compliance mark for device class M shall be a “C“ as required in MIL-PRF-38535, appendix A.

36、Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-98510 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 5 DSCC FORM 2234 APR 97 3.6 Certificate of compliance. For device classes

37、N, Q, and V, a certificate of compliance shall be required from a QML-38535 listed manufacturer in order to supply to the requirements of this drawing (see 6.6.1 herein). For device class M, a certificate of compliance shall be required from a manufacturer in order to be listed as an approved source

38、 of supply in MIL-HDBK-103 (see 6.6.2 herein). The certificate of compliance submitted to DSCC-VA prior to listing as an approved source of supply for this drawing shall affirm that the manufacturers product meets, for device classes N, Q, and V, the requirements of MIL-PRF-38535 and herein or for d

39、evice class M, the requirements of MIL-PRF-38535, appendix A and herein. 3.7 Certificate of conformance. A certificate of conformance as required for device classes N, Q, and V in MIL-PRF-38535 or for device class M in MIL-PRF-38535, appendix A shall be provided with each lot of microcircuits delive

40、red to this drawing. 3.8 Notification of change for device class M. For device class M, notification to DSCC-VA of change of product (see 6.2 herein) involving devices acquired to this drawing is required for any change that affects this drawing. 3.9 Verification and review for device class M. For d

41、evice class M, DSCC, DSCCs agent, and the acquiring activity retain the option to review the manufacturers facility and applicable required documentation. Offshore documentation shall be made available onshore at the option of the reviewer. 3.10 Microcircuit group assignment for device class M. Devi

42、ce class M devices covered by this drawing shall be in microcircuit group number 42 (see MIL-PRF-38535, appendix A). 4. VERIFICATION 4.1 Sampling and inspection. For device classes N, Q, and V, sampling and inspection procedures shall be in accordance with MIL-PRF-38535 or as modified in the device

43、manufacturers Quality Management (QM) plan. The modification in the QM plan shall not affect the form, fit, or function as described herein. For device class M, sampling and inspection procedures shall be in accordance with MIL-PRF-38535, appendix A. 4.2 Screening. For device classes N, Q, and V, sc

44、reening shall be in accordance with MIL-PRF-38535, and shall be conducted on all devices prior to qualification and technology conformance inspection. For device class M, screening shall be in accordance with method 5004 of MIL-STD-883, and shall be conducted on all devices prior to quality conforma

45、nce inspection. 4.2.1 Additional criteria for device class M. a. Delete the sequence specified as initial (preburn-in) electrical parameters through interim (postburn-in) electrical parameters of method 5004 and substitute lines 1 through 6 of table IIA herein. b. For device class M, the test circui

46、t shall be maintained by the manufacturer under document revision level control and shall be made available to the preparing or acquiring activity upon request. For device class M, the test circuit shall specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with th

47、e intent specified in method 1015. c. Interim and final electrical parameters shall be as specified in table IIA herein. 4.2.2 Additional criteria for device classes N, Q, and V. a. The burn-in test duration, test condition and test temperature, or approved alternatives shall be as specified in the device manufacturers QM plan in accordance with MI