DLA SMD-5962-96846 REV B-2004 MICROCIRCUIT DIGITAL-LINEAR CMOS SINGLE SUPPLY 600 KSPS 12-BIT A D CONVERTER MONOLITHIC SILICON《互补金属氧化物半导体 单供应600KSPS12-BIT交流电或直流电转换器 硅单片电路数字线型微电路》.pdf

《DLA SMD-5962-96846 REV B-2004 MICROCIRCUIT DIGITAL-LINEAR CMOS SINGLE SUPPLY 600 KSPS 12-BIT A D CONVERTER MONOLITHIC SILICON《互补金属氧化物半导体 单供应600KSPS12-BIT交流电或直流电转换器 硅单片电路数字线型微电路》.pdf》由会员分享，可在线阅读，更多相关《DLA SMD-5962-96846 REV B-2004 MICROCIRCUIT DIGITAL-LINEAR CMOS SINGLE SUPPLY 600 KSPS 12-BIT A D CONVERTER MONOLITHIC SILICON《互补金属氧化物半导体 单供应600KSPS12-BIT交流电或直流电转换器 硅单片电路数字线型微电路》.pdf（13页珍藏版）》请在麦多课文档分享上搜索。

1、 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Add case outline L. drw 99-09-01 Raymond Monnin B Drawing updated to reflect current requirements. -rrp 04-12-15 Raymond Monnin REV SHET REV SHET REV STATUS REV B B B B B B B B B B B B OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 12 PMIC N/A PREPARED

2、BY Dan Wonnell DEFENSE SUPPLY CENTER COLUMBUS STANDARD MICROCIRCUIT DRAWING CHECKED BY Ray Monnin COLUMBUS, OHIO 43218-3990 http:/www.dscc.dla.mil THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS APPROVED BY Ray Monnin MICROCIRCUIT, DIGITAL-LINEAR, CMOS, SINGLE SUPPLY, 600 KSPS, 12-BIT, A/D CONV

3、ERTER, MONOLITHIC SILICON AND AGENCIES OF THE DEPARTMENT OF DEFENSE DRAWING APPROVAL DATE 96-07-25 AMSC N/A REVISION LEVEL B SIZE A CAGE CODE 67268 5962-96846 SHEET 1 OF 12 DSCC FORM 2233 APR 97 5962-E048-05 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IH

4、S-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-96846 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 2 DSCC FORM 2234 APR 97 1. SCOPE 1.1 Scope. This drawing documents two product assurance class levels consisting of high reliability (device classes Q and M) and spac

5、e application (device class V). A choice of case outlines and lead finishes are available and are reflected in the Part or Identifying Number (PIN). When available, a choice of Radiation Hardness Assurance (RHA) levels are reflected in the PIN. 1.2 PIN. The PIN is as shown in the following example:

6、5962 - 96846 01 Q L A Federal stock class designator RHA designator (see 1.2.1) Device type (see 1.2.2)Device class designatorCase outline (see 1.2.4) Lead finish (see 1.2.5) / (see 1.2.3) / Drawing number 1.2.1 RHA designator. Device classes Q and V RHA marked devices meet the MIL-PRF-38535 specifi

7、ed RHA levels and are marked with the appropriate RHA designator. Device class M RHA marked devices meet the MIL-PRF-38535, appendix A specified RHA levels and are marked with the appropriate RHA designator. A dash (-) indicates a non-RHA device. 1.2.2 Device type(s). The device type(s) identify the

8、 circuit function as follows: Device type Generic number Circuit function 01 7892S Single supply 12-bit 600 KSPS ADC 1.2.3 Device class designator. The device class designator is a single letter identifying the product assurance level as follows: Device class Device requirements documentation M Vend

9、or self-certification to the requirements for MIL-STD-883 compliant, non-JAN class level B microcircuits in accordance with MIL-PRF-38535, appendix A Q or V Certification and qualification to MIL-PRF-38535 1.2.4 Case outline(s). The case outline(s) are as designated in MIL-STD-1835 and as follows: O

10、utline letter Descriptive designator Terminals Package style J GDIP1-T24 or CDIP2-T24 24 Dual-in-line L GDIP3-T24 or CDIP4-T24 24 Dual-in-line 1.2.5 Lead finish. The lead finish is as specified in MIL-PRF-38535 for device classes Q and V or MIL-PRF-38535, appendix A for device class M. Provided by I

11、HSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-96846 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 3 DSCC FORM 2234 APR 97 1.3 Absolute maximum ratings. 1/ VDDto AGND -0.3 V dc to +7 V d

12、c VDDto DGND -0.3 V dc to +7 V dc Analog input voltage to AGND 17 V dc Reference input voltage to AGND -0.3 V dc to VDD+ 0.3 V dc Digital input voltage to DGND. -0.3 V dc to VDD+ 0.3 V dc Digital output voltage to DGND. -0.3 V dc to VDD+ 0.3 V dc Power dissipation (PD) 450 mW Storage temperature ran

13、ge. -65C to +150C Junction temperature (TJ) . +150C Lead temperature (soldering, 10 sec). +300C Thermal resistance, junction-to-ambient (JA). 70C/W 1.4 Recommended operating conditions. Ambient operating temperature range (TA). -55C to +125C 2. APPLICABLE DOCUMENTS 2.1 Government specification, stan

14、dards, and handbooks. The following specification, standards, and handbooks form a part of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the solicitation or contract. DEPARTMENT OF DEFENSE SPECIFICATION MIL-PRF-38535 - Integ

15、rated Circuits, Manufacturing, General Specification for. DEPARTMENT OF DEFENSE STANDARDS MIL-STD-883 - Test Method Standard Microcircuits. MIL-STD-1835 - Interface Standard Electronic Component Case Outlines. DEPARTMENT OF DEFENSE HANDBOOKS MIL-HDBK-103 - List of Standard Microcircuit Drawings. MIL

16、-HDBK-780 - Standard Microcircuit Drawings. (Copies of these documents are available online at http:/assist.daps.dla.mil/quicksearch/ or http:/assist.daps.dla.mil or from the Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.) 2.2 Order of precedence.

17、In the event of a conflict between the text of this drawing and the references cited herein, the text of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a specific exemption has been obtained. 1/ Stresses above the absolute maximum

18、rating may cause permanent damage to the device. Extended operation at the maximum levels may degrade performance and affect reliability. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-96846 DEFENSE SUPPLY C

19、ENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 4 DSCC FORM 2234 APR 97 3. REQUIREMENTS 3.1 Item requirements. The individual item requirements for device classes Q and V shall be in accordance with MIL-PRF-38535 and as specified herein or as modified in the device manufacturers Qual

20、ity Management (QM) plan. The modification in the QM plan shall not affect the form, fit, or function as described herein. The individual item requirements for device class M shall be in accordance with MIL-PRF-38535, appendix A for non-JAN class level B devices and as specified herein. 3.2 Design,

21、construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified in MIL-PRF-38535 and herein for device classes Q and V or MIL-PRF-38535, appendix A and herein for device class M. 3.2.1 Case outline. The case outline shall be in accordance with 1.2.4 her

22、ein. 3.2.2 Terminal connections. The terminal connections shall be as specified on figure 1. 3.3 Electrical performance characteristics and postirradiation parameter limits. Unless otherwise specified herein, the electrical performance characteristics and postirradiation parameter limits are as spec

23、ified in table I and shall apply over the full ambient operating temperature range. 3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table II. The electrical tests for each subgroup are defined in table I. 3.5 Marking. The part shall be marked wi

24、th the PIN listed in 1.2 herein. In addition, the manufacturers PIN may also be marked. For packages where marking of the entire SMD PIN number is not feasible due to space limitations, the manufacturer has the option of not marking the “5962-“ on the device. For RHA product using this option, the R

25、HA designator shall still be marked. Marking for device classes Q and V shall be in accordance with MIL-PRF-38535. Marking for device class M shall be in accordance with MIL-PRF-38535, appendix A. 3.5.1 Certification/compliance mark. The certification mark for device classes Q and V shall be a “QML“

26、 or “Q“ as required in MIL-PRF-38535. The compliance mark for device class M shall be a “C“ as required in MIL-PRF-38535, appendix A. 3.6 Certificate of compliance. For device classes Q and V, a certificate of compliance shall be required from a QML-38535 listed manufacturer in order to supply to th

27、e requirements of this drawing (see 6.6.1 herein). For device class M, a certificate of compliance shall be required from a manufacturer in order to be listed as an approved source of supply in MIL-HDBK-103 (see 6.6.2 herein). The certificate of compliance submitted to DSCC-VA prior to listing as an

28、 approved source of supply for this drawing shall affirm that the manufacturers product meets, for device classes Q and V, the requirements of MIL-PRF-38535 and herein or for device class M, the requirements of MIL-PRF-38535, appendix A and herein. 3.7 Certificate of conformance. A certificate of co

29、nformance as required for device classes Q and V in MIL-PRF-38535 or for device class M in MIL-PRF-38535, appendix A shall be provided with each lot of microcircuits delivered to this drawing. 3.8 Notification of change for device class M. For device class M, notification to DSCC-VA of change of pro

30、duct (see 6.2 herein) involving devices acquired to this drawing is required for any change that affects this drawing. 3.9 Verification and review for device class M. For device class M, DSCC, DSCCs agent, and the acquiring activity retain the option to review the manufacturers facility and applicab

31、le required documentation. Offshore documentation shall be made available onshore at the option of the reviewer. 3.10 Microcircuit group assignment for device class M. Device class M devices covered by this drawing shall be in microcircuit group number 81 (see MIL-PRF-38535, appendix A). Provided by

32、 IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-96846 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 5 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics. Limits Test

33、Symbol Conditions 1/ -55C TA +125C unless otherwise specified Group A subgroups Device type Min Max Unit Signal to noise ratio + distortion ratio SNR fIN= 100 kHz, fSAMPLE= 500 ksps 1, 2, 3 01 70 dB Total harmonic distortion THD 1, 2, 3 01 -78 dB Peak harmonic or spurious distortion PHD 1, 2, 3 01 -

34、79 dB Intermodulation distortion IMD fs= 49 kHz, fb= 50 kHz 1, 2, 3 01 -78 dB Resolution RES 1, 2, 3 01 12 Bits Minimum resolution for which no codes are guaranteed RESMIN1, 2, 3 01 12 Bits Relative accuracy RA 1, 2, 3 01 1 LSB Differential nonlinearity DNL 1, 2, 3 01 1 LSB Positive and negative ful

35、l-scale error FSE 1, 2, 3 01 5 LSB Bipolar zero error BZE 1, 2, 3 01 3 LSB Input voltage range VINInput applied to VIN1with VIN2grounded 1, 2, 3 01 10 V Input resistance RINInput applied to VIN1with VIN2grounded 1, 2, 3 01 8 k REF IN input voltage range VREFINSee 4.4.1c 4 01 2.38 2.625 V Input imped

36、ance RREFResistor connected to internal reference node 1, 2, 3 01 1.6 k Reference input capacitance CRINSee 4.4.1c 4 01 10 pF 1 10 REF OUT error VRE2, 3 01 25 mV Input high voltage VINHVDD = 5 V 5% 1, 2, 3 01 2.4 V Input low voltage VINL VDD= 5 V 5% 1, 2, 3 01 0.8 V Input current IINVIN= 0 V to VDD1

37、, 2, 3 01 10 A Input capacitance CINSee 4.4.1c 4 01 10 pF Output high voltage VOHISOURCE= 200 A 1, 2, 3 01 4 V Output low voltage VOLISINK= 1.6 mA 1, 2, 3 01 0.4 V See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDAR

38、D MICROCIRCUIT DRAWING SIZE A 5962-96846 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 6 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics - Continued. Limits Test Symbol Conditions 1/ -55C TA +125C unless otherwise specified Group A subgroups De

39、vice type Min Max Unit Floating state capacitance CFSDB11 - DB0, see 4.4.1c 4 01 15 pF Floating state leakage current ILKGDB11 - DB0 1, 2, 3 01 10 A Power supply current IDDnormal operation 1, 2, 3 01 19 mA Power dissipation PDnormal operation 1, 2, 3 01 95 mW Conversion time tCONV2/, see figure 2 1

40、, 2, 3 01 1.68 s Acquisition time tACQ2/, see figure 2, see 4.4.1c 9, 10, 11 01 320 ns CONVST pulse width t12/, see figure 2, see 4.4.1c 9, 10, 11 01 45 ns EOC pulse width t22/, see figure 2, see 4.4.1c 9, 10, 11 01 60 ns EOC falling edge to CS falling edge setup time t32/, see figure 2, see 4.4.1c

41、9, 10, 11 01 0 ns CS to RD setup time t42/, see figure 2, see 4.4.1c 9, 10, 11 01 0 ns Read pulse width t52/, see figure 2, see 4.4.1c 9, 10, 11 01 45 ns Data access time after falling edge of RD t62/, 3/, see figure 2, see 4.4.1c 9, 10, 11 01 40 ns Bus relinquish time after rising edge of RD t72/,

42、4/, see figure 2, see 4.4.1c 9, 10, 11 01 5 40 ns CS to RD hold time t82/, see figure 2, see 4.4.1c 9, 10, 11 01 0 ns RD to CONVST setup time t92/, see figure 2, see 4.4.1c 9, 10, 11 01 200 ns RFS low to SCLK falling edge setup time t102/, see figure 2, see 4.4.1c 9, 10, 11 01 35 ns RFS low to data

43、valid delay t112/, 3/, see figure 2, see 4.4.1c 9, 10 11 01 30 ns SCLK high pulse width t122/, see figure 2, see 4.4.1c 9, 10, 11 01 25 ns SCLK low pulse width t132/, see figure 2, see 4.4.1c 9, 10, 11 01 25 ns SCLK rising edge to data valid hold time t142/, 3/, see figure 2, see 4.4.1c 9, 10, 11 01

44、 5 ns SCLK rising edge to data valid delay time t152/, 3/, see figure 2, see 4.4.1c 9, 10, 11 01 30 ns See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-96846 DEFENSE SUPPLY CENTE

45、R COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 7 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics - Continued. Limits Test Symbol Conditions 1/ -55C TA +125C unless otherwise specified Group A subgroups Device type Min Max Unit RFS to SCLK falling edge hold time t16

46、2/, see figure 2, see 4.4.1c 9, 10, 11 01 30 ns Bus relinquish time after rising edge of RFS t172/, 4/, see figure 2, see 4.4.1c 9, 10, 11 01 0 30 ns Bus relinquish time after rising edge of SCLK t17A2/, 4/, see figure 2, see 4.4.1c 9, 10, 11 01 0 30 ns 1/ VDD= +5 V 5%, AGND = DGND = 0 V, REF IN = +

47、2.5 V. 2/ All input signals are measured with tr = tf = 1 ns (10% to 90% of +5 V) and timed from a voltage level of +1.6 V. 3/ Defined as the time required for an output to cross 0.8 V or 2.4 V. 4/ These times are derived from the measured time taken by the data outputs to change 0.5 V. The measured

48、 number is then extrapulated back to remove the effects of charging or discharching the 50 pF capacitor. Therefore these timing characteristics are the true bus relinquish times and as such are independent of external bus loading capacitances. 4. VERIFICATION 4.1 Sampling and inspection. For device classes Q and V, sampling and inspection procedures shall be in accordance with MIL-PRF-38535 or as modified in the device manufacturers Quality Management (QM) plan. The modification in the QM plan shall not affect the form, fit, o