DLA SMD-5962-96621 REV E-2005 MICROCIRCUIT DIGITAL RADIATION HARDENED CMOS NAND GATES MONOLITHIC SILICON《抗辐射互补金属氧化物半导体与非硅单片电路数字微电路》.pdf
《DLA SMD-5962-96621 REV E-2005 MICROCIRCUIT DIGITAL RADIATION HARDENED CMOS NAND GATES MONOLITHIC SILICON《抗辐射互补金属氧化物半导体与非硅单片电路数字微电路》.pdf》由会员分享,可在线阅读,更多相关《DLA SMD-5962-96621 REV E-2005 MICROCIRCUIT DIGITAL RADIATION HARDENED CMOS NAND GATES MONOLITHIC SILICON《抗辐射互补金属氧化物半导体与非硅单片电路数字微电路》.pdf(27页珍藏版)》请在麦多课文档分享上搜索。
1、 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Changes in accordance with NOR 5962-R184-97. CFS 97-02-24 Monica L. Poelking B Changes in accordance with NOR 5962-R396-97. - RLC 97-07-29 Raymond L. Monnin C Add device class T criteria. Editorial changes throughout. JAK 98-12-07 Monica L. Poelk
2、ing D Correct the total dose rate and update RHA levels. - LTG 99-04-28 Monica L. Poelking E Update boilerplate to MIL-PRF-38535 requirements. Editorial changes throughout. LTG 05-09-07 Thomas M. Hess REV SHET REV E E E E E E E E E E E SHEET 15 16 17 18 19 20 21 22 23 24 25 REV STATUS REV E C D E E
3、E E D C C E E E E OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PMIC N/A PREPARED BY Dan Wonnell DEFENSE SUPPLY CENTER COLUMBUS STANDARD MICROCIRCUIT DRAWING CHECKED BY Monica L. Poelking COLUMBUS, OHIO 43218-3990 http:/www.dscc.dla.mil THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS APPROVE
4、D BY Monica L. Poelking AND AGENCIES OF THE DEPARTMENT OF DEFENSE DRAWING APPROVAL DATE 95-11-27 MICROCIRCUIT, DIGITAL, RADIATION HARDENED, CMOS, NAND GATES, MONOLITHIC SILICON AMSC N/A REVISION LEVEL E SIZE A CAGE CODE 67268 5962-96621 SHEET 1 OF 25 DSCC FORM 2233 APR 97 5962-E487-05 Provided by IH
5、SNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-96621 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL C SHEET 2 DSCC FORM 2234 APR 97 1. SCOPE 1.1 Scope. This drawing documents three product assuran
6、ce class levels consisting of high reliability (device classes Q and M), space application (device class V) and for appropriate satellite and similar applications (device class T). A choice of case outlines and lead finishes are available and are reflected in the Part or Identifying Number (PIN). Wh
7、en available, a choice of Radiation Hardness Assurance (RHA) levels is reflected in the PIN. For device class T, the user is encouraged to review the manufacturers Quality Management (QM) plan as part of their evaluation of these parts and their acceptability in the intended application. 1.2 PIN. Th
8、e PIN is as shown in the following example: 5962 R 96621 01 V X C Federal stock class designator RHA designator (see 1.2.1) Device type (see 1.2.2)Device class designatorCase outline (see 1.2.4) Lead finish (see 1.2.5) / (see 1.2.3) / Drawing number 1.2.1 RHA designator. Device classes Q, T, and V R
9、HA marked devices meet the MIL-PRF-38535 specified RHA levels and are marked with the appropriate RHA designator. Device class M RHA marked devices meet the MIL-PRF-38535, appendix A specified RHA levels and are marked with the appropriate RHA designator. A dash (-) indicates a non-RHA device. 1.2.2
10、 Device type(s). The device type(s) identify the circuit function as follows: Device type Generic number Circuit function 01 4011B Radiation hardened, CMOS, quad 2-input NAND gate 02 4012B Radiation hardened, CMOS, dual 4-input NAND gate 03 4023B Radiation hardened, CMOS, triple 3-input NAND gate 04
11、 4011BN Radiation hardened, CMOS, quad 2-input NAND gate with neutron irradiated die 05 4012BN Radiation hardened, CMOS, dual 4-input NAND gate with neutron irradiated die 06 4023BN Radiation hardened, CMOS, triple 3-input NAND gate with neutron irradiated die 1.2.3 Device class designator. The devi
12、ce class designator is a single letter identifying the product assurance level as follows: Device class Device requirements documentation M Vendor self-certification to the requirements for MIL-STD-883 compliant, non-JAN class level B microcircuits in accordance with MIL-PRF-38535, appendix A Q, V C
13、ertification and qualification to MIL-PRF-38535 T Certification and qualification to MIL-PRF-38535 with performance as specified in the device manufacturers approved quality management plan. 1.2.4 Case outline(s). The case outline(s) are as designated in MIL-STD-1835 and as follows: Outline letter D
14、escriptive designator Terminals Package style C CDIP2-T14 14 Dual-in-line X CDFP3-F14 14 Flat pack Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-96621 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-399
15、0 REVISION LEVEL D SHEET 3 DSCC FORM 2234 APR 97 1.2.5 Lead finish. The lead finish is as specified in MIL-PRF-38535 for device classes Q, T, and V or MIL-PRF-38535, appendix A for device class M. 1.3 Absolute maximum ratings. 1/ 2/ 3/ Supply voltage range (VDD) -0.5 V dc to +20 V dc DC input voltag
16、e range (VIN) -0.5 V dc to VDD+ 0.5 V dc DC input current, any one input (IIN). 10 mA Device dissipation per output transistor . 100 mW Storage temperature range (TSTG) . -65C to +150C Lead temperature (soldering, 10 seconds). +265C Thermal resistance, junction-to-case (JC): Case outline C . 24C/W C
17、ase outline X 30C/W Thermal resistance, junction-to-ambient (JA): Case outline C . 74C/W Case outline X 116C/W Junction temperature (TJ) +175C Maximum package power dissipation at TA= +125C (PD): 4/ Case outline C . 0.68 W Case outline X 0.43 W 1.4 Recommended operating conditions. 2/ 3/ Supply volt
18、age range (VDD) +3.0 V dc to +18 V dc Case operating temperature range (TC). -55C to +125C Input voltage range (VIN) +0.0 V to VDDOutput voltage range (VOUT). +0.0 V to VDD1.5 Radiation features: Maximum total dose available (dose rate = 50 300 rad (Si)/s) 1 x 105Rads (Si) Single event phenomenon (S
19、EP) effective linear energy threshold (LET), no upsets (see 4.4.4.5) 75 MeV/(cm2/mg) 5/ Dose rate upset (20 ns pulse) 5 x 108Rads (Si)/s 5/ Dose rate latch-up 2 x 108Rads(Si)/s 5/ Dose rate survivability 5 x 1011Rads (Si)/s 5/ Neutron irradiated (device types 04, 05, and 06) . 1 x 1014neutrons/cm25/
20、 1/ Stresses above the absolute maximum rating may cause permanent damage to the device. Extended operation at the maximum levels may degrade performance and affect reliability. 2/ Unless otherwise noted, all voltages are referenced to VSS. 3/ The limits for the parameters specified herein shall app
21、ly over the full specified VDDrange and case temperature range of -55C to +125C unless otherwise noted. 4/ If device power exceeds package dissipation capability, provide heat sinking or derate linearly (the derating is based on JA) at the following rate: Case outline C. 13.5 mW/C Case outline X . 8
22、.6 mW/C 5/ Guaranteed by design or process but not tested. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-96621 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL E SHEET 4 DSCC FORM 223
23、4 APR 97 2. APPLICABLE DOCUMENTS 2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a part of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the solicitation or
24、contract. DEPARTMENT OF DEFENSE SPECIFICATION MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for. DEPARTMENT OF DEFENSE STANDARDS MIL-STD-883 - Test Method Standard Microcircuits. MIL-STD-1835 - Interface Standard Electronic Component Case Outlines. DEPARTMENT OF DEFENSE H
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