DLA SMD-5962-95632 REV G-2013 MICROCIRCUIT LINEAR RADIATION HARDENED CMOS QUAD DIFFERENTIAL LINE DRIVER MONOLITHIC SILICON.pdf

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1、 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Add paragraph 1.3 and Appendix A in accordance with NOR 5962-R031-97. 96-11-06 R. MONNIN B Add device class T criteria. Editorial changes throughout. Redrawn. -lgt 98-12-23 R. MONNIN C Add vendor CAGE F8859. Updated footnote 2/ in table I to acco

2、mmodate RHA designator “D”. Update boilerplate to reflect current requirements. -rrp 02-11-27 R. MONNIN D Add junction temperature to 1.3. Made change to propagation delay time tests, tPZH/tPZLand tPLZ/tPHZin table I. - rrp 07-03-02 J. RODENBECK E Make a correction to Figure 2 by replacing the secon

3、d from the left ENABLE with ENABLE . - ro 08-03-20 R. HEBER F Add device type 02. Update radiation features under paragraph 1.5. Add paragraph 2.2 ASTM information and Table IB. Delete table III, Dose rate induced latchup testing and Dose rate upset testing paragraphs. - ro 12-04-17 C. SAFFLE G Add

4、case outline Y. Add note under figure 1. Delete device class M references. - ro 13-05-22 C. SAFFLE REV SHEET REV G G G G G G G G G G SHEET 15 16 17 18 19 20 21 22 23 24 REV STATUS REV G G G G G G G G G G G G G G OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PMIC N/A PREPARED BY KENNETH S. RICE DL

5、A LAND AND MARITIME COLUMBUS, OHIO 43218-3990 http:/www.landandmaritime.dla.mil STANDARD MICROCIRCUIT DRAWING THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS AND AGENCIES OF THE DEPARTMENT OF DEFENSE CHECKED BY SANDRA ROONEY APPROVED BY MICHAEL FRYE MICROCIRCUIT, LINEAR, RADIATION HARDENED, CMO

6、S, QUAD DIFFERENTIAL, LINE DRIVER, MONOLITHIC SILICON DRAWING APPROVAL DATE 95-07-13 AMSC N/A REVISION LEVEL G SIZE A CAGE CODE 67268 5962-95632 SHEET 1 OF 24 DSCC FORM 2233 APR 97 5962-E362-13 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD

7、 MICROCIRCUIT DRAWING SIZE A 5962-95632 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL G SHEET 2 DSCC FORM 2234 APR 97 1. SCOPE 1.1 Scope. This drawing documents three product assurance class levels consisting of high reliability (device class Q), space application (device class V) a

8、nd for appropriate satellite and similar applications (device class T). A choice of case outlines and lead finishes are available and are reflected in the Part or Identifying Number (PIN). When available, a choice of Radiation Hardness Assurance (RHA) levels is reflected in the PIN. For device class

9、 T, the user is encouraged to review the manufacturers Quality Management (QM) plan as part of their evaluation of these parts and their acceptability in the intended application. 1.2 PIN. The PIN is as shown in the following example: 5962 F 95632 01 V X C Federal stock class designator RHA designat

10、or (see 1.2.1) Device type (see 1.2.2) Device class designator Case outline (see 1.2.4) Lead finish (see 1.2.5) / (see 1.2.3) / Drawing number 1.2.1 RHA designator. Device classes Q, T and V RHA marked devices meet the MIL-PRF-38535 specified RHA levels and are marked with the appropriate RHA design

11、ator. A dash (-) indicates a non-RHA device. 1.2.2 Device type(s). The device type(s) identify the circuit function as follows: Device type Generic number Circuit function 01 26CT31RH Radiation hardened quad differential line driver 02 26CT31EH Radiation hardened quad differential line driver 1.2.3

12、Device class designator. The device class designator is a single letter identifying the product assurance level as follows: Device class Device requirements documentation Q, V Certification and qualification to MIL-PRF-38535 T Certification and qualification to MIL-PRF-38535 with performance as spec

13、ified in the device manufacturers approved quality management plan. 1.2.4 Case outline(s). The case outline(s) are as designated in MIL-STD-1835 and as follows: Outline letter Descriptive designator Terminals Package style E CDIP2-T16 16 Dual-in-line X CDFP4-F16 16 Flat pack Y CDFP4-F16 16 Flat pack

14、 with grounded lid 1.2.5 Lead finish. The lead finish is as specified in MIL-PRF-38535 for device classes Q, T and V. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-95632 DLA LAND AND MARITIME COLUMBUS, OHIO

15、 43218-3990 REVISION LEVEL G SHEET 3 DSCC FORM 2234 APR 97 1.3 Absolute maximum ratings. 1/ Supply voltage . -0.5 V to +7.0 V Inputs, E, E voltage -0.5 V to VDD+0.5 V Output voltage (power on or off (0.0 V) -0.5 V to +7.0 V DC diode input current (any input) . 20 mA DC drain current (any output) 350

16、 mA DC VDDor ground current 400 mA Power dissipation at TA= 125C (PD) . 0.44 W 2/ For TA= -55C to 125C: Case outline E . 0.667 W Case outlines X and Y 0.526 W Storage temperature range -65C to +150C Lead temperature (soldering, 10 seconds) 300C Junction temperature (TJ) +175C Thermal resistance, jun

17、ction-to-case (JC) See MIL-STD-1835 Thermal resistance, junction-to-ambient (JA): Case outline E 75C/W Case outlines X and Y 95C/W 1.4 Recommended operating conditions. Operating temperature range (TA) . -55C to +125C Supply voltage range (VDD) +4.5 V to +5.5 V Low input voltage (VIL) 0 V to 0.8 V,

18、maximum High input voltage (VIH) . VDDto VDD/2 V, minimum Input rise and fall time . 500 ns maximum Dynamic current (IDYN) at +25 C . 3 mA Power dissipation capacitance (CPD) at +25C . 170 pF _ 1/ Stresses above the absolute maximum rating may cause permanent damage to the device. Extended operation

19、 at the maximum levels may degrade performance and affect reliability. 2/ Maximum device power dissipation is defined as VDDx ICCand must withstand the added PDdue to output current test IOat TA= +125C. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,

20、-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-95632 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL G SHEET 4 DSCC FORM 2234 APR 97 1.5 Radiation features. Maximum total dose available (dose rate = 50 300 rads(Si)/s): Device type 01 classes Q or V . 300 krads(Si) 3/ Device type 01 class

21、T 100 krads(Si) 3/ Device type 02 . 300 krads(Si) 4/ Maximum total dose available (dose rate 0.01 rad(Si)/s): Device type 02 50 krad(Si) 4/ Single event phenomena (SEP): No single event latch up (SEL) occurs at effective (LET) (see 4.4.3.) . 100 MeV/mg/cm25/ The manufacturer supplying RHA device typ

22、es 01 and 02 on this drawing has performed characterization testing to demonstrate that the parts do not exhibit enhanced low dose rate sensitivity (ELDRS) in accordance with MIL-STD-883, method 1019, paragraph 3.13.1.1. Therefore these parts may be considered ELDRS free at a level of 100 krads(Si).

23、 The manufacturer will perform only high dose rate lot acceptance testing on a wafer by wafer basis in accordance with MIL-STD-883, method 1019, condition A for device type 01. The manufacturer will perform high dose rate and low dose rate lot acceptance testing on a wafer by wafer basis in accordan

24、ce with MIL-STD-883, method 1019, conditions A and D for device type 02. 2. APPLICABLE DOCUMENTS 2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a part of this drawing to the extent specified herein. Unless otherwise specified, the i

25、ssues of these documents are those cited in the solicitation or contract. DEPARTMENT OF DEFENSE SPECIFICATION MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for. DEPARTMENT OF DEFENSE STANDARDS MIL-STD-883 - Test Method Standard Microcircuits. MIL-STD-1835 - Interface Stan

26、dard Electronic Component Case Outlines. DEPARTMENT OF DEFENSE HANDBOOKS MIL-HDBK-103 - List of Standard Microcircuit Drawings. MIL-HDBK-780 - Standard Microcircuit Drawings. (Copies of these documents are available online at http:/quicksearch.dla.mil or from the Standardization Document Order Desk,

27、 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.) _ 3/ The manufacturer supplying device type 01 has performed characterization testing in accordance with MIL-STD-883 method 1019 paragraph 3.13.1.1 and the parts exhibited no enhanced low dose rate sensitivity (ELDRS) at a level of 100

28、krads(Si). The radiation end point limits for the noted parameters are guaranteed only for the conditions as specified in MIL-STD-883, method 1019, condition A to a maximum total dose of 300 krads(Si) for device classes V, Q, or M and 100 krads(Si) for device class T. 4/ The manufacturer supplying d

29、evice type 02 has performed characterization testing in accordance with MIL-STD-883 method 1019 paragraph 3.13.1.1 and the parts exhibited no enhanced low dose rate sensitivity (ELDRS) at a level of 100 krads(Si). The radiation end point limits for the noted parameters are guaranteed only for the co

30、nditions as specified in MIL-STD-883, method 1019, condition A to a maximum total dose of 300 krads(Si), and condition D to a maximum total dose of 50 krads(Si). 5/ Guaranteed by process or design, not tested. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from

31、IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-95632 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL G SHEET 5 DSCC FORM 2234 APR 97 2.2 Non-Government publications. The following document(s) form a part of this document to the extent specified herein. Unless otherwise specified, t

32、he issues of the documents are the issues of the documents cited in the solicitation or contract. ASTM INTERNATIONAL (ASTM) ASTM F1192 Standard Guide for the Measurement of Single Event Phenomena (SEP) Induced by Heavy Ion Irradiation of Semiconductor Devices. (Copies of this document is available o

33、nline at http:/www.astm.org/ or from ASTM International, P.O. Box C700, 100 Bar Harbor Drive, West Conshohocken, PA 19428-2959). 2.3 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text of this drawing takes precedence. Nothing in

34、 this document, however, supersedes applicable laws and regulations unless a specific exemption has been obtained. 3. REQUIREMENTS 3.1 Item requirements. The individual item requirements for device classes Q, T and V shall be in accordance with MIL-PRF-38535 as specified herein, or as modified in th

35、e device manufacturers Quality Management (QM) plan. The modification in the QM plan shall not affect the form, fit, or function as described herein. 3.1.1 Microcircuit die. For the requirements of microcircuit die, see appendix A to this document. 3.2 Design, construction, and physical dimensions.

36、The design, construction, and physical dimensions shall be as specified in MIL-PRF-38535 and herein for device classes Q, T and V. 3.2.1 Case outlines. The case outlines shall be in accordance with 1.2.4 herein. 3.2.2 Terminal connections. The terminal connections shall be as specified on figure 1.

37、3.2.3 Truth table. The truth table shall be as specified on figure 2. 3.2.4 Radiation exposure circuit. The radiation exposure circuit shall be maintained by the manufacturer under document revision level control and shall be made available to the preparing and acquiring activity upon request. 3.3 E

38、lectrical performance characteristics and postirradiation parameter limits. Unless otherwise specified herein, the electrical performance characteristics and postirradiation parameter limits are as specified in table IA and shall apply over the full ambient operating temperature range. 3.4 Electrica

39、l test requirements. The electrical test requirements shall be the subgroups specified in table IIA. The electrical tests for each subgroup are defined in table IA. 3.5 Marking. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturers PIN may also be marked. For pac

40、kages where marking of the entire SMD PIN number is not feasible due to space limitations, the manufacturer has the option of not marking the “5962-“ on the device. For RHA product using this option, the RHA designator shall still be marked. Marking for device classes Q, T and V shall be in accordan

41、ce with MIL-PRF-38535. 3.5.1 Certification/compliance mark. The certification mark for device classes Q, T and V shall be a “QML“ or “Q“ as required in MIL-PRF-38535. 3.6 Certificate of compliance. For device classes Q, T and V, a certificate of compliance shall be required from a QML-38535 listed m

42、anufacturer in order to supply to the requirements of this drawing (see 6.6.1 herein). The certificate of compliance submitted to DLA Land and Maritime -VA prior to listing as an approved source of supply for this drawing shall affirm that the manufacturers product meets, for device classes Q, T and

43、 V, the requirements of MIL-PRF-38535 and herein. 3.7 Certificate of conformance. A certificate of conformance as required for device classes Q, T and V in MIL-PRF-38535 shall be provided with each lot of microcircuits delivered to this drawing. Provided by IHSNot for ResaleNo reproduction or networ

44、king permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-95632 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL G SHEET 6 DSCC FORM 2234 APR 97 TABLE IA. Electrical performance characteristics. Test Symbol Conditions 1/ 2/ -55C TA +125C unless otherwise spe

45、cified Group A subgroups Device type Limits Unit Min Max High level output voltage VOHVDD= 4.5 V and 5.5 V, IO= -20 mA 3/ 4/ 1, 2, 3 01, 02 2.5 V Low level output voltage VOLVDD= 4.5 V and 5.5 V, IO= 20 mA 3/ 4/ 1, 2, 3 01, 02 0.5 V Differential output voltage VT, VTVDD= VIH= 4.5 V, VIL= 0 V, RL= R1

46、 + R2 5/ 1, 2, 3 01, 02 2.0 V Difference in differential output VT TV VDD= VIH= 4.5 V, VIL= 0 V, RL= R1 + R2 5/ 1, 2, 3 01, 02 0.4 V Common Mode Output voltage VOS OSV VDD= VIH= 4.5 V, VIL= 0 V, RL= R1 + R2 5/ 1, 2, 3 01, 02 3.0 V Difference in Common Mode Output VOS OSV VDD= VIH= 4.5 V, VIL= 0 V, R

47、L= R1 + R2 5/ 1, 2, 3 01, 02 0.4 V High level input voltage VIHVDD= 4.5 V, 5.5 V 6/ 1, 2, 3 01, 02 VDD/2.0 V Low level input voltage VILVDD= 4.5 V, 5.5 V 6/ 1, 2, 3 01, 02 0.8 V Standby supply current IDDSBVDD= 5.5 V, output = open, VIN= VDDor GND 1, 2, 3 01, 02 500 A Three-state output leakage curr

48、ent IOZVDD= 5.5 V, force voltages = 0 V or VDD7/ 1, 2, 3 01, 02 5.0 A Delta supply current ICCVDD= 5.5 V, VIN= 2.4 V, 0.5 V 1, 2, 3 01, 02 2.0 mA Input leakage current IINVDD= 5.5 V, VIN= VDDor GND 1, 2, 3 01, 02 1.0 A Output leakage current power off IOFFVDD= 0.0 V, VOUT= 6.0 V, 250 mV, Inputs = GND 1, 2, 3 01, 02 -100 100 A Input clamp voltage VICat -1.0 mA 1, 2, 3 01, 02 -1.5 V at +1.0 mA +1.5 Functional test See 4.4.1b 7, 8A, 8B 01, 02 See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted w