DLA SMD-5962-95628-1998 MICROCIRCUIT MEMORY DIGITAL CMOS 512 X 36 X 2 CLOCKED FIFO MONOLITHIC SILICON《数字的互补金属氧化物半导体512 X 36 X 2时钟先入先出硅单片电路线型微电路》.pdf

《DLA SMD-5962-95628-1998 MICROCIRCUIT MEMORY DIGITAL CMOS 512 X 36 X 2 CLOCKED FIFO MONOLITHIC SILICON《数字的互补金属氧化物半导体512 X 36 X 2时钟先入先出硅单片电路线型微电路》.pdf》由会员分享，可在线阅读，更多相关《DLA SMD-5962-95628-1998 MICROCIRCUIT MEMORY DIGITAL CMOS 512 X 36 X 2 CLOCKED FIFO MONOLITHIC SILICON《数字的互补金属氧化物半导体512 X 36 X 2时钟先入先出硅单片电路线型微电路》.pdf（34页珍藏版）》请在麦多课文档分享上搜索。

1、REVISIONSLTR DESCRIPTION DATE (YR-MO-DA) APPROVEDREV SHEET REVSHEET 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33REV STATUSOF SHEETSREVSHEET 123456789101121314PMIC N/APREPARED BY Gary L. Gross DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216 STANDARDMICROCIRCUITDRAWINGTHIS DRAWING IS A

2、VAILABLEFOR USE BY ALLDEPARTMENTSAND AGENCIES OF THEDEPARTMENT OF DEFENSEAMSC N/A CHECKED BYJeff BowlingMICROCIRCUIT, MEMORY, DIGITAL, CMOS512 X 36 X 2 CLOCKED FIFO, MONOLITHIC SILICONAPPROVED BYRaymond MonninDRAWING APPROVAL DATE98-01-06SIZEACAGE CODE672685962-95628REVISION LEVELSHEET 1 OF 33 DSCC

3、FORM 2233APR 97 5962-E137-98DISTRIBUTION STATEMENT A. Approved for public release; distribution is unlimited.Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARDMICROCIRCUIT DRAWINGDEFENSE SUPPLY CENTER COLUMBUSCOLUMBUS, OHIO 43216-5000SIZEA5962-

4、95628REVISION LEVEL SHEET2DSCC FORM 2234APR 971. SCOPE1.1 Scope. This drawing documents two product assurance class levels consisting of high reliability (device classes Q and M)and space application (device class V). A choice of case outlines and lead finishes are available and are reflected in the

5、 Part orIdentifying Number (PIN). When available, a choice of Radiation Hardness Assurance (RHA) levels are reflected in the PIN.1.2 PIN. The PIN shall be as shown in the following example:5962 - 95628 01 Q Y X | | | | | | | | | | Federal RHA Device Device Case Lead stock class designator type class

6、 outline finishdesignator (see 1.2.1) (see 1.2.2) designator (see 1.2.4) (see 1.2.5) / (see 1.2.3)/Drawing number1.2.1 RHA designator. Device classes Q and V RHA marked devices meet the MIL-PRF-38535 specified RHA levels and aremarked with the appropriate RHA designator. Device class M RHA marked de

7、vices meet the MIL-PRF-38535, appendix Aspecified RHA levels and are marked with the appropriate RHA designator. A dash (-) indicates a non-RHA device.1.2.2 Device type(s). The device type(s) shall identify the circuit function as follows:Device type Generic number Circuit function01 ACT3632 512 X 3

8、6 X 2 clocked FIFO1.2.3 Device class designator. The device class designator shall be a single letter identifying the product assurance level asfollows:Device class Device requirements documentationM Vendor self-certification to the requirements for MIL-STD-883 compliant,non-JAN class level B microc

9、ircuits in accordance with MIL-PRF-38535,appendix AQ or V Certification and qualification to MIL-PRF-385351.2.4 Case outline(s). The case outline(s) shall be as designated in MIL-STD-1835 and as follows:Outline letter Descriptive designator Terminals Package styleY See figure 1 132 Ceramic quad flat

10、 package1.2.5 Lead finish. The lead finish is as specified in MIL-PRF-38535 for device classes Q and V or MIL-PRF-38535, appendixA for device class M. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARDMICROCIRCUIT DRAWINGDEFENSE SUPPLY CENTER C

11、OLUMBUSCOLUMBUS, OHIO 43216-5000SIZEA5962-95628REVISION LEVEL SHEET3DSCC FORM 2234APR 971.3 Absolute maximum ratings. 1/ 2/ 3/Supply voltage range (V ) . -0.5 V dc to +7.0 V dcCCDC input voltage range (I/O ports) (V ) -0.5 V dc to V + 0.5 V dc 4/IN CCDC output voltage range (V ) -0.5 V dc to V + 0.5

12、 V dc 4/OUT CCDC output current (I ) (per output)(V = 0.0 V to V ). 50 mAOOCDC input clamp current (I ) (V V ) . 20 mAIK IN IN CCDC output clamp current (I ) (V V ) . 50 mAOK OUT OUT CCStorage temperature range (T ) -65 C to +150 CSTGLead temperature (soldering, 10 seconds) +300 CThermal resistance,

13、 junction-to-case ( ) . 2.0 C/WJCJunction temperature (T ) . +150 CJMaximum power dissipation (P ) at T = +55 C in still air 1.8 W 5/DAV current (I ). 400 mACC VCCGround current (I ) 400 mAGND1.4 Recommended operating conditions. 2/ 3/Supply voltage range (V ) . +4.5 V dc to +5.5 V dcCCMaximum low l

14、evel input voltage (V ) +0.8 VILMinimum high level input voltage (V ) . +2.0 VIHMaximum high level output current (I ) -4.0 mAOHMaximum low level output current (I ) . +8.0 mAOLCase operating temperature range (T ) -55 C to +125 CC1.5 Digital logic testing for device classes Q and V.Fault coverage m

15、easurement of manufacturinglogic tests (MIL-STD-883, test method 5012). XX percent 6/2. APPLICABLE DOCUMENTS2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a partof this drawing to the extent specified herein. Unless otherwise specif

16、ied, the issues of these documents are those listed in theissue of the Department of Defense Index of Specifications and Standards (DoDISS) and supplement thereto, cited in thesolicitation.SPECIFICATIONDEPARTMENT OF DEFENSEMIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for

17、.STANDARDSDEPARTMENT OF DEFENSEMIL-STD-883 - Test Methods and Procedures for Microelectronics.MIL-STD-973 - Configuration Management.MIL-STD-1835 - Interface Standard for Microcircuit Case Outlines.1/ Stresses above the absolute maximum rating may cause permanent damage to the device. Extended opera

18、tion at themaximum levels may degrade performance and affect reliability.2/ Unless otherwise noted, all voltages are referenced to GND.3/ The limits for the parameters specified herein shall apply over the full specified V range and case temperature range ofCC-55 C to +125 C.4/ The input negative vo

19、ltage rating may be exceeded provided that the input clamp current rating is observed.5/ The maximum package power dissipation is calculated using a junction temperature of 150 C and a board trace length of750 mils.6/ Values will be added when they become available.Provided by IHSNot for ResaleNo re

20、production or networking permitted without license from IHS-,-,-STANDARDMICROCIRCUIT DRAWINGDEFENSE SUPPLY CENTER COLUMBUSCOLUMBUS, OHIO 43216-5000SIZEA5962-95628REVISION LEVEL SHEET4DSCC FORM 2234APR 97HANDBOOKSDEPARTMENT OF DEFENSEMIL-HDBK-103 - List of Standard Microcircuit Drawings (SMDs).MIL-HD

21、BK-780 - Standard Microcircuit Drawings.(Unless otherwise indicated, copies of the specification, standards, and handbooks are available from the StandardizationDocument Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.)2.2 Order of precedence. In the event of a conflict betw

22、een the text of this drawing and the references cited herein, the text ofthis drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless aspecific exemption has been obtained.3. REQUIREMENTS3.1 Item requirements. The individual item requirements fo

23、r device classes Q and V shall be in accordance with MIL-PRF-38535 and as specified herein or as modified in the device manufacturers Quality Management (QM) plan. The modification inthe QM plan shall not affect the form, fit, or function as described herein. The individual item requirements for dev

24、ice class Mshall be in accordance with MIL-PRF-38535, appendix A for non-JAN class level B devices and as specified herein.3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified inMIL-PRF-38535 and herein for device classes Q and V

25、or MIL-PRF-38535, appendix A and herein for device class M.3.2.1 Case outline(s). The case outline(s) shall be in accordance with 1.2.4 herein and figure 1.3.2.2 Terminal connections. The terminal connections shall be as specified on figure 2.3.2.3 Truth table(s). The truth table(s) shall be as spec

26、ified on figure 3.3.2.4 Block or logic diagram(s). The block or logic diagram(s) shall be as specified on figure 4.3.2.5 Test circuit and switching waveforms. The test circuit and switching waveforms shall be as specified on figures 5 and 6.3.3 Electrical performance characteristics and postirradiat

27、ion parameter limits. Unless otherwise specified herein, theelectrical performance characteristics and postirradiation parameter limits are as specified in table I and shall apply over the fullcase operating temperature range.3.4 Electrical test requirements. The electrical test requirements shall b

28、e the subgroups specified in table IIA. The electricaltests for each subgroup are defined in table I.3.5 Marking. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturers PIN may also bemarked as listed in MIL-HDBK-103. For packages where marking of the entire SMD P

29、IN number is not feasible due to spacelimitations, the manufacturer has the option of not marking the “5962-“ on the device. For RHA product using this option, theRHA designator shall still be marked. Marking for device classes Q and V shall be in accordance with MIL-PRF-38535. Markingfor device cla

30、ss M shall be in accordance with MIL-PRF-38535, appendix A.3.5.1 Certification/compliance mark. The certification mark for device classes Q and V shall be a “QML“ or “Q“ as required inMIL-PRF-38535. The compliance mark for device class M shall be a “C“ as required in MIL-PRF-38535, appendix A.3.6 Ce

31、rtificate of compliance. For device classes Q and V, a certificate of compliance shall be required from a QML-38535listed manufacturer in order to supply to the requirements of this drawing (see 6.6.1 herein). For device class M, a certificate ofcompliance shall be required from a manufacturer in or

32、der to be listed as an approved source of supply in MIL-HDBK-103 (see6.6.2 herein). The certificate of compliance submitted to DSCC-VA prior to listing as an approved source of supply for thisdrawing shall affirm that the manufacturers product meets, for device classes Q and V, the requirements of M

33、IL-PRF-38535 andherein or for device class M, the requirements of MIL-PRF-38535, appendix A and herein.Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARDMICROCIRCUIT DRAWINGDEFENSE SUPPLY CENTER COLUMBUSCOLUMBUS, OHIO 43216-5000SIZEA5962-95628R

34、EVISION LEVEL SHEET5DSCC FORM 2234APR 97TABLE I. Electrical performance characteristics.Test Symbol Test conditions 1/-55 C T +125 CC+4.5 V V +5.5 VCCunless otherwise specifiedDevicetypesGroup AsubgroupsLimits 2/ UnitMin MaxHigh level outputvoltageVOHFor all inputs affecting output under test, V =IN

35、2.0 V or 0.8 V,I = -4.0 mA, V = 4.5 VOH CC01 1, 2, 3 2.4 VLow level outputvoltageVOLFor all inputs affecting output under test, V =IN2.0 V or 0.8 V,I = 8 mA, V = 4.5 VOL CC01 1, 2, 3 0.5 VInput current I 3/IFor input under test, V = V or GND,ICCV = 5.5 VCC01 1, 2, 3 +5AThree-state outputleakage curr

36、ent highI 4/OZHV = V , V = 5.5 VOUT CC CC01 1, 2, 3 5 AThree-state outputleakage current lowIOZL 4/ V = GND, V = 5.5 VOUT CC01 1, 2, 3 -5 AQuiescent supplycurrent, outputs highICCFor all inputs, Output = port B, I = 0A,OUTV = 5.5 V, V = V -0.2 V or GNDCC IN CC01 1, 2, 3 400 AQuiescent supplycurrent,

37、 deltaICCV = 5.5 V,CCOne input at 3.4 V,Other inputs at VCCor GND.CG0ASG0AAG0A = VIHA0-A35 011, 2, 30mAG0AG0ABG0A = VIHB0-B35 0CG0ASG0AAG0A = VILA0-A35 1CG0ASG0ABG0A = VILB0-B35 1All other inputs 1Input capacitance CINSee 4.4.1e, V = 0I01 4 7 pFI/O capacitance COUTSee 4.4.1e, V = 0O410Functional tes

38、ts 5/ V = 2.0 V, V = 0.8 V, verify output V , V =IH IL O CC4.5 V and 5.5 V, 4.4.1c01 7, 8A, 8B L HClock frequencyCLKA or CLKBfclockC = 20 pF minimum, V = 4.5 V and LCC5.5 V, see figures 5 and 6 as applicable01 9, 10, 11 50 MHzClock cycle timeCLKA or CLKBtc01 9, 10, 11 20 nsPulse duration, CLKAand CL

39、KB high or lowtw01 9, 10, 11 8Setup time, A0-A35before CLKA , andB0-B35 before CLKB tsu(D)01 9, 10, 11 5Setup time,CG0ASG0AAG0A, W/RG0AA, ENA andMBA before CLKA ;CG0ASG0ABG0A, WG09/RB, MBB andENB before CLKB tsu(EN)01 9, 10, 11 5Setup time, RG09SG09TG091G09 orRG09SG09TG092G09 low beforeCLKA or CLKB

40、tsu(RS)6/01 9, 10, 11 6See footnotes at end of table.Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARDMICROCIRCUIT DRAWINGDEFENSE SUPPLY CENTER COLUMBUSCOLUMBUS, OHIO 43216-5000SIZEA5962-95628REVISION LEVEL SHEET6DSCC FORM 2234APR 97TABLE I. E

41、lectrical performance characteristics - Continued.Test Symbol Test conditions 1/-55(C T +125(CC+4.5 V V +5.5 VCCunless otherwise specifiedDevicetypesGroup AsubgroupsLimits 2/ UnitMin MaxSetup time, FS0 and FS1before RG09SG09TG091G09 and RG09SG09TG092G09hightsu(FS)C = 20 pF minimum,LV = 4.5 V and 5.5

42、 V,CCSee figures 5 and 6 as applicable01 9, 10, 11 8.5 nsHold time, A0-A35 afterCLKA and B0-B35 afterCLKB th(D)01 9, 10, 11 1Hold time, CG09SG09AG09, W/RG09A,ENA and MBA after CLKA and CG09SG09BG09, WG09/RB, MBB andENB after CLKB th(EN)01 9, 10, 11 1Hold time, RG09SG09TG091G09 or RG09SG09TG092G09low

43、 after CLKA or CLKB th(RS)6/01 9, 10, 11 4Hold time, FS0 and FS1after RG09SG09TG091G09 and RG09SG09TG092G09highth(FS)01 9, 10, 11 3Skew time, betweenCLKA and CLKB forORA, ORB, IRA, and IRBt sk(1)7/01 9, 10, 11 9Skew time, betweenCLKA and CLKB forAG0AEG0AAG0A, AG0AEG0ABG0A, AG0AFG0AAG0A, andAG0AFG0AB

44、G0At sk(2)7/01 9, 10, 11 16Access time, CLKA to A0-A35 and CLKB to B0-B35t a01 9, 10, 11 3 15Propagation delay time, CLKA to IRA and CLKB to IRBtpd(C-IR)01 9, 10, 11 2 10Propagation delay time, CLKA to ORA and CLKB to ORB tpd(C-OR)01 9, 10, 11 1 10Propagation delay time, CLKA to AG0AEG0AAG0A and CLK

45、B to AG0AEG0ABG0Atpd(C-AE)01 9, 10, 11 1 10Propagation delay time, CLKA to AG0AFG0AAG0A and CLKB to AG0AFG0ABG0Atpd(C-AF)01 9, 10, 11 1 10Propagation delay time, CLKA to MG09BG09FG091G09 low or MG09BG09FG092G09 high and CLKB to MG09BG09FG092G09 low or MG09BG09FG091G09 hightpd(C-MF)01 9, 10, 11 0 10S

46、ee footnotes at end of table.Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARDMICROCIRCUIT DRAWINGDEFENSE SUPPLY CENTER COLUMBUSCOLUMBUS, OHIO 43216-5000SIZEA5962-95628REVISION LEVEL SHEET7DSCC FORM 2234APR 97TABLE I. Electrical performance ch

47、aracteristics - Continued.Test Symbol Test conditions 1/-55(C T +125(CC+4.5 V V +5.5 VCCunless otherwise specifiedDevicetypesGroup AsubgroupsLimits 2/ UnitMin MaxPropagation delay time, CLKA to B0-B35 8/andCLKB to A0-A35 9/tpd(C-MR)C = 20 pF minimum,LV = 4.5 V and 5.5 V,CCSee figures 5 and 6 as appl

48、icable01 9, 10, 11 3 18.7 nsPropagation delay time, MBA to A0-A35 valid andMBB to B0-B35 validtpd(M-DV)01 9, 10, 11 3 13Propagation delay time, RG09SG09TG091G09 low to AG09EG09BG09 low,AG09FG09AG09 high, and MG09BG09FG091G09 high, and RG09SG09TG092G09 low toAG09EG09AG09 low, AG09FG09BG09 high, and MG09BG09FG092G09 hightpd(R-F)01 9, 10, 11 1 20Enable time, CG09SG09AG09 andW/RG09A low to A0-A35active and CG0ASG0ABG0A low andWG09/RB high to B0-B35activet en01 9, 10, 11 2 18Disable time, CG09SG09AG09 orW/RG09A high to A0-A35 athigh impedance and CG0ASG0A