DLA SMD-5962-95624 REV C-2006 MICROCIRCUIT HYBRID MEMORY DIGITAL 512K X 32-BIT STATIC RANDOM ACCESS MEMORY CMOS《混合数字的512K X 32-BIT 静电噪声随机存取存储器互补金属氧化物半导体微电路》.pdf

《DLA SMD-5962-95624 REV C-2006 MICROCIRCUIT HYBRID MEMORY DIGITAL 512K X 32-BIT STATIC RANDOM ACCESS MEMORY CMOS《混合数字的512K X 32-BIT 静电噪声随机存取存储器互补金属氧化物半导体微电路》.pdf》由会员分享，可在线阅读，更多相关《DLA SMD-5962-95624 REV C-2006 MICROCIRCUIT HYBRID MEMORY DIGITAL 512K X 32-BIT STATIC RANDOM ACCESS MEMORY CMOS《混合数字的512K X 32-BIT 静电噪声随机存取存储器互补金属氧化物半导体微电路》.pdf（21页珍藏版）》请在麦多课文档分享上搜索。

1、 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Added note to paragraph 1.2.2 and table I regarding the 4 transistor design. Paragraph 1.3; changed the power dissipation for device types 05-09 from 2.9 W max to 3.3 W max. Table I; changed the ICC max limit for device types 05-09 from 520 mA to

2、 600 mA. Table I; changed the ICCDR1max limit from 12 mA to 28 mA. Figure 1; changed dimension A minimum from 0.175 inches to 0.115 inches. Redrew entire document . -sld 00-09-27 Michael Jones B Drawing updated to reflect current requirements. -sld 04-03-29 Raymond Monnin C Table I; Changed the maxi

3、mum limit for COE and CAD tests from 32 pF to 30 pF. -sld 06-02-06 Raymond Monnin REV SHEET REV C C C C C C SHEET 15 16 17 18 19 20 REV C C C C C C C C C C C C C C REV STATUS OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PMIC N/A PREPARED BY Gary Zahn DEFENSE SUPPLY CENTER COLUMBUS STANDARD MICRO

4、CIRCUIT DRAWING CHECKED BY Michael C. Jones COLUMBUS, OHIO 43218-3990 http:/www.dscc.dla.mil APPROVED BY Kendall A. Cottongim MICROCIRCUIT, HYBRID, MEMORY, DIGITAL, 512K x 32-BIT, STATIC RANDOM ACCESS MEMORY, CMOS THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS AND AGENCIES OF THE DEPARTMENT OF

5、 DEFENSE DRAWING APPROVAL DATE 96-08-09 AMSC N/A REVISION LEVEL C SIZE A CAGE CODE 67268 5962-95624 SHEET 1 OF 20 DSCC FORM 2233 APR 97 5962-E251-06 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-95624 DEFEN

6、SE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL C SHEET 2 DSCC FORM 2234 APR 97 1. SCOPE 1.1 Scope. This drawing documents five product assurance classes as defined in paragraph 1.2.3 and MIL-PRF-38534. A choice of case outlines and lead finishes which are available and are reflec

7、ted in the Part or Identifying Number (PIN). When available, a choice of radiation hardness assurance levels are reflected in the PIN. 1.2 PIN. The PIN shall be as shown in the following example: 5962 - 95624 01 H N X Federal RHA Device Device Case Lead stock class designator type class outline fini

8、sh designator (see 1.2.1) (see 1.2.2) designator (see 1.2.4) (see 1.2.5) / (see 1.2.3) / Drawing number 1.2.1 Radiation hardness assurance (RHA) designator. RHA marked devices shall meet the MIL-PRF-38534 specified RHA levels and shall be marked with the appropriate RHA designator. A dash (-) indica

9、tes a non-RHA device. 1.2.2 Device type(s). The device type(s) identify the circuit function as follows: Device type 1/ Generic number Circuit function Access time 01 WS512K32F-120G4Q SRAM, 512K x 32-bit 120 ns 02 WS512K32F-100G4Q SRAM, 512K x 32-bit 100 ns 03 WS512K32F-85G4Q SRAM, 512K x 32-bit 85

10、ns 04 WS512K32F-70G4Q SRAM, 512K x 32-bit 70 ns 05 WS512K32F-55G4Q SRAM, 512K x 32-bit 55 ns 06 WS512K32F-45G4Q SRAM, 512K x 32-bit 45 ns 07 WS512K32F-35G4Q SRAM, 512K x 32-bit 35 ns 08 WS512K32F-25G4Q SRAM, 512K x 32-bit 25 ns 09 WS512K32F-20G4Q SRAM, 512K x 32-bit 20 ns 10 WS512K32M-45G4Q SRAM, 51

11、2K x 32-bit 45 ns 11 WS512K32M-35G4Q SRAM, 512K x 32-bit 35 ns 12 WS512K32M-25G4Q SRAM, 512K x 32-bit 25 ns 1.2.3 Device class designator. This device class designator shall be a single letter identifying the product assurance level. All levels are defined by the requirements of MIL-PRF-38534 and re

12、quire QML Certification as well as qualification (Class H, K, and E) or QML Listing (Class G and D). The product assurance levels are as follows: Device class Device performance documentation K Highest reliability class available. This level is intended for use in space applications. H Standard mili

13、tary quality class level. This level is intended for use in applications where non-space high reliability devices are required. 1/ Due to the nature of the 4 transistor design of the die in these device types, topologically pure testing is important, particularly for high reliability applications. T

14、he device manufacturer should be consulted concerning their testing methods and algorithms. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-95624 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVIS

15、ION LEVEL C SHEET 3 DSCC FORM 2234 APR 97 G Reduced testing version of the standard military quality class. This level uses the Class H screening and In-Process Inspections with a possible limited temperature range, manufacturer specified incoming flow, and the manufacturer guarantees (but may not t

16、est) periodic and conformance inspections (Group A, B, C and D). E Designates devices which are based upon one of the other classes (K, H, or G) with exception(s) taken to the requirements of that class. These exception(s) must be specified in the device acquisition document; therefore the acquisiti

17、on document should be reviewed to ensure that the exception(s) taken will not adversely affect system performance. D Manufacturer specified quality class. Quality level is defined by the manufacturers internal, QML certified flow. This product may have a limited temperature range. 1.2.4 Case outline

18、(s). The case outline(s) are as designated in MIL-STD-1835 and as follows: Outline letter Descriptive designator Terminals Package style N See figure 1 68 Co-fired, single cavity, quad flat pack, low capacitance 1.2.5 Lead finish. The lead finish shall be as specified in MIL-PRF-38534. 1.3 Absolute

19、maximum ratings. 1/ Supply voltage range (VCC) . -0.5 V dc to +7.0 V dc Signal voltage range (VG) -0.5 V dc to +7.0 V dc Power dissipation (PD) : Device types 01 through 09 3.3 W Maximum at 5 MHz Device types 10 through 12 4.4 W Maximum at 5 MHz Storage temperature range -65C to +150C Lead temperatu

20、re (soldering, 10 seconds). +300C 1.4 Recommended operating conditions. Supply voltage range (VCC) . +4.5 V dc to +5.5 V dc Input low voltage range (VIL) -0.5 V dc to +0.8 V dc Input high voltage range (VIH) +2.2 V dc to VCC+ 0.3 V dc Case operating temperature range (TC). -55C to +125C 2. APPLICABL

21、E DOCUMENTS 2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a part of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the solicitation or contract. DEPARTMENT

22、OF DEFENSE SPECIFICATION MIL-PRF-38534 - Hybrid Microcircuits, General Specification for. 1/ Stresses above the absolute maximum ratings may cause permanent damage to the device. Extended operation at the maximum levels may degrade performance and affect reliability. Provided by IHSNot for ResaleNo

23、reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-95624 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL C SHEET 4 DSCC FORM 2234 APR 97 DEPARTMENT OF DEFENSE STANDARDS MIL-STD-883 - Test Method Standard Microcircuits.

24、MIL-STD-1835 - Interface Standard for Electronic Component Case Outlines. DEPARTMENT OF DEFENSE HANDBOOKS MIL-HDBK-103 - List of Standard Microcircuit Drawings. MIL-HDBK-780 - Standard Microcircuit Drawings. (Copies of these documents are available online at http:/assist.daps.dla.mil/quicksearch/ or

25、 http:/assist.daps.dla.mil or from the Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.) 2.2 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text of this drawing takes precedence.

26、Nothing in this document, however, supersedes applicable laws and regulations unless a specific exemption has been obtained. 3. REQUIREMENTS 3.1 Item requirements. The individual item performance requirements for device classes D, E, G, H, and K shall be in accordance with MIL-PRF-38534. Compliance

27、with MIL-PRF-38534 shall include the performance of all tests herein or as designated in the device manufacturers Quality Management (QM) plan or as designated for the applicable device class. The manufacturer may eliminate, modify or optimize the tests and inspections herein, however the performanc

28、e requirements as defined in MIL-PRF-38534 shall be met for the applicable device class. In addition, the modification in the QM plan shall not affect the form, fit, or function of the device for the applicable device class. 3.2 Design, construction, and physical dimensions. The design, construction

29、, and physical dimensions shall be as specified in MIL-PRF-38534 and herein. 3.2.1 Case outline(s). The case outline(s) shall be in accordance with 1.2.4 herein and figure 1. 3.2.2 Terminal connections. The terminal connections shall be as specified on figure 2. 3.2.3 Truth table(s). The truth table

30、(s) shall be as specified on figure 3. 3.2.4 Logic diagram(s). The logic diagram(s) shall be as specified on figures 4 and 5. 3.2.5 Block diagram. The block diagram shall be as specified on figure 6. 3.2.6 Output load circuit. The output load circuit shall be as specified on figure 7. 3.3 Electrical

31、 performance characteristics. Unless otherwise specified herein, the electrical performance characteristics are as specified in table I and shall apply over the full specified operating temperature range. 3.4 Electrical test requirements. The electrical test requirements shall be the subgroups speci

32、fied in table II. The electrical tests for each subgroup are defined in table I. 3.5 Marking of device(s). Marking of device(s) shall be in accordance with MIL-PRF-38534. The device shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturers vendor similar PIN may also be marke

33、d. 3.6 Data. In addition to the general performance requirements of MIL-PRF-38534, the manufacturer of the device described herein shall maintain the electrical test data (variables format) from the initial quality conformance inspection group A lot sample, for each device type listed herein. Also,

34、the data should include a summary of all parameters manually tested, and for those which, if any, are guaranteed. This data shall be maintained under document revision level control by the manufacturer and be made available to the preparing activity (DSCC-VA) upon request. Provided by IHSNot for Res

35、aleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-95624 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL C SHEET 5 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics. Limits Test Symbol Conditio

36、ns 1/ 2/ 3/ -55C TC +125C unless otherwise specified Group A subgroups Device types Min Max Unit DC parameters Input leakage current ILIVCC= 5.5 V dc, VIN= GND or VCC1,2,3 All 10 A Output leakage current ILOCS = VIH, OE = VIH, VOUT= GND or VCC1,2,3 All 10 A Operating supply current ICCCS = VIL, OE =

37、 VIH, f = 5 MHz, VCC= 5.5 V dc 1,2,3 01-04 05-09 10-12 200 600 800 mA Standby current ISBCS = VIH, OE = VIH, f = 5 MHz, VCC= 5.5 V dc 1,2,3 01-04 05-09 10-12 4.0 60 120 mA Input low level VIL1,2,3 All 0.8 V Input high level VIH1,2,3 All 2.2 V VCC= 4.5 V, IOL= 2.1 mA 1,2,3 01-06 0.4 Output low voltag

38、e VOLVCC= 4.5 V, IOL= 8.0 mA 1,2,3 07-12 0.4 V VCC= 4.5 V, IOL= -1.0 mA 1,2,3 01-06 2.4 Output high voltage VOHVCC= 4.5 V, IOL= -4.0 mA 1,2,3 07-12 2.4 V Dynamic characteristics OE capacitance 4/ COEVIN= 0 V, f = 1.0 MHz, TA= +25C 4 All 30 pF WE capacitance 4/ CWE VIN= 0 V, f = 1.0 MHz, TA= +25C 4 A

39、ll 32 pF CS 1-4 capacitance 4/ CCSVIN= 0 V, f = 1.0 MHz, TA= +25C 4 All 15 pF Data I/O capacitance 4/ CI/OVIN= 0 V, f = 1.0 MHz, TA= +25C 4 All 15 pF See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT

40、 DRAWING SIZE A 5962-95624 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL C SHEET 6 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics - Continued. Limits Test Symbol Conditions 1/ 2/ 3/ -55C TC +125C unless otherwise specified Group A subgroups Device typ

41、es Min Max Unit Dynamic characteristics - Continued Address input capacitance 4/ CADVIN= 0 V, f = 1.0 MHz, TA= +25C 4 All 30 pF Functional testing Functional tests See 4.3.1c 7,8A,8B All Data retention characteristics Data retention supply voltage VDRCS VDR- 0.2 V 9,10,11 All 2.0 5.5 V Data retentio

42、n current ICCDR1VCC= 3 V 9,10,11 01-04 05-09 10-12 1.6 28 40 mA Read cycle AC timing characteristics Read cycle time tRCSee figure 4 9,10,11 01 02 03 04 05 06,10 07,11 08,12 09 120 100 85 70 55 45 35 25 20 ns Address access time tAA See figure 4 9,10,11 01 02 03 04 05 06,10 07,11 08,12 09 120 100 85

43、 70 55 45 35 25 20 ns See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-95624 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL C SHEET 7 DSCC FORM 2234 APR

44、97 TABLE I. Electrical performance characteristics - Continued. Limits Test Symbol Conditions 1/ 2/ 3/ -55C TC+125C unless otherwise specified Group A subgroups Device types Min Max Unit Read cycle AC timing characterisitics - Continued Chip select access time tACSSee figure 4 9,10,11 01 02 03 04 05

45、 06,10 07,11 08,12 09 120 100 85 70 55 45 35 25 20 ns Output enable to output valid tOESee figure 4 9,10,11 01 02 03 04,10 05-07,11 08,12 09 60 50 40 35 25 12 10 ns Output hold from address change tOHSee figure 4 9,10,11 01-04 10-12 05-09 5 5 0 ns Write AC timing characteristics WE controlled Write

46、cycle time tWCSee figure 5 9,10,11 01 02 03 04 05 06,10 07,11 08,12 09 120 100 85 70 55 45 35 25 20 ns See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-95624 DEFENSE SUPPLY CENTE

47、R COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL C SHEET 8 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics - Continued. Limits Test Symbol Conditions 1/ 2/ 3/ -55C TC +125C unless otherwise specified Group A subgroups Device types Min Max Unit Write AC timing characteristics

48、 WE controlled - Continued Chip select to end of write tCWSee figure 5 9,10,11 01 02 03 04 05 06,10 07,11 08,12 09 100 80 75 60 50 35 25 17 15 ns Address valid to end of write tAWSee figure 5 9,10,11 01 02 03 04 05 06,10 07,11 08,12 09 100 80 75 60 50 35 25 17 15 ns Data valid to end of write tDWSee figure 5 9,10,11 01,02 03,04,10 05,06 07,11 08 09 12 40 30 25 20 13 12 10 ns Write pulse width tWPSee figure 5 9,10,11 01,02 03,04 05 06,10 07,11