DLA SMD-5962-95612 REV A-1996 MICROCIRCUIT MEMORY DIGITAL CMOS PROGRAMMABLE LOGIC CELL ARRAY MONOLITHIC SILICON《数字的互补金属氧化物半导体 可编程逻辑电池陈列硅单片电路线型微电路》.pdf

《DLA SMD-5962-95612 REV A-1996 MICROCIRCUIT MEMORY DIGITAL CMOS PROGRAMMABLE LOGIC CELL ARRAY MONOLITHIC SILICON《数字的互补金属氧化物半导体 可编程逻辑电池陈列硅单片电路线型微电路》.pdf》由会员分享，可在线阅读，更多相关《DLA SMD-5962-95612 REV A-1996 MICROCIRCUIT MEMORY DIGITAL CMOS PROGRAMMABLE LOGIC CELL ARRAY MONOLITHIC SILICON《数字的互补金属氧化物半导体 可编程逻辑电池陈列硅单片电路线型微电路》.pdf（28页珍藏版）》请在麦多课文档分享上搜索。

1、SMD-5962-95612 REV A m 999999b 009005L 2TO m DEFENSE LOGISTICS AGENCY DEFENSE SUPPLY CENTER COLUMBUS 3990 BROAD STREET COLUMBUS, OH 43216-5000 IN REPLY REFER TO DSCC-VAS (Mr. K Rice/(DSN)850-0534/614-692-0534/ksr) OCT 3 0 1936 SUBJECT: Notice of Revision (NOR) 5962-RO12-97 for Standard Microcircuit

2、Drawing (SMD) 5962-95612 Military/Industry Distribution The enclosed NOR is approved for use effective as of the date of the NOR. In accordance with MIL-STD-100 SMD holders should, as a minimum, handwrite those changes described in the NOR to sheet 1 of the subject SMD. After completion, the NOR sho

3、uld be attached to the subject SMD for future reference. Those companies who were listed as approved sources of supply prior to this action have agreed to actions taken on devices for which they had previously provided DSCC a certificate of compliance. This is evidenced by an existing active current

4、 certificate of compliance on file at DSCC with a DSCC record of verbal coordination. The certificate of compliance for these devices is considered concurrence with the new revision unless DSCC is otherwise notified. If you have comments or questions, please contact Ken Rice at (DSN)850-0534/(614)69

5、2-0534. 1 Encl RAMONNIN Chief, Microelectronics Team Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-SND-57b2-95bL2 REV A 7979996 0070052 137 W NOTICE OF REVISION (NOR) THIS REVISION DESCRIBED BELOW HAS BEEN AUTHORIZED FOR THE DOCUMENT LISTED. 1. DAT

6、E (WMMDD) Form Approved 96-1 0-04 OM8 NO. 0704-0188 ubicrepdng,burden forthis wiledon is estimated to average 2 hours per,response. induding the time for reviewin insuctions, searchin existing data ources, gathenn and maintaining the data needed, and completing and reviewing the coii+ion of informat

7、ion. Sen8comments regardin dis burden stimate or an oker as ect of this collection of information including su gestions for reduang this burden to Department of Defense Wa%n tion leadquarters iervices. giredorate for Information Operatidns and Repofis 1215 Jefferson Davis Hi hway: Suite 1204. Arling

8、ton. VA 222024802. and to the ?ce of Mana ement and Bud et Pa emork Reduction Prolecl 07044188 Washin ton DC 20583. LEASE DO AT RETURN Y8Uk CgMPLETED FORM TO EITLER OF TdkSE ADJREkSED. RETURN COMPLETED FORM TO THE GOVERNMENT SSUING CONTRACTING OFFICER FOR THE CONTRACT/ PROCURING ACTIVITY NUMBER LIST

9、ED IN ITEM 2 OF THIS FORM. b. ADDRESS (Street, City, State, Zip Code) 5. CAGE CODE *. ORIGINATOR Defense Supply Center Columbus 67268 3990 Broad Street Columbus,OH 43216-5000 Last) 67268 I. TYPED NAME (First, Middle Initial, 7. CAGE CODE 1 I I 12. CONFIGURATION ITEM (OR SYSTEM) TO WHICH ECP APPLIES

10、Aii 2. PROCURING ACTIVITY NO. 3 6. NOR NO. 5962-R012-97 8. DOCUMENT NO. 5962-95612 3. DESCRIPTION OF REVISION I I I. TITLE OF DOCUMENT 10. REVISION LETTER a, CURRENT MICROCIRCUIT, MEMORY, DIGITAL CMOS, PROGRAMMABLE LOGIC :ELL ARRAY, MONOLITHIC SILICON b. NEW A Sheet 1: Sheet 9: 11. ECP NO. Revisions

11、 ltr colum; add I1Ai1. Revisions description colum; add “Changes in accordance with NOR 5962-R012-97i. Revisions date coluni; add 1196-10-0411. Rev status above sheet nunbers 1 and 9, add InAal. Revision Level block; add l0Aaa. Table I, footnote 3 Delete the last sentence of this footnote and replac

12、e it with the following: Vharacterization data is taken initially and after any design or process change which may affect this parameter .II Revision level block; add alA1l. b. ACTIVITY AUTHORIZED TO APPROVE CHANGE FOR GOVERNMENT 14. THIS SECTION FOR GOVERNMENT USE ONLY C. TYPED NAME (First, Middle

13、Initial, Last) One) I X I (i) Existing document supplemented by the NOR may be used in manufacture. d. TITLE Microelectronics Team Chief 15a. ACTIVITY ACCOMPLISHING REVISION H e. SIGNATURE Ray Monnin b. REVISION COMPLETED (Signature) DSCC-VAS Kenneth S. Rice DD Form 1695, APR 92 Previous editions am

14、 obsolete. f. DATE SIGNED (WMMDD) 96-1 0-04 c. DATE SIGNED (WMMDD) 96-10-04 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-LTR DESCRIPTION REV III APPROVED DATE (YR-MO-DA) REV 111 SIZE A SHEET I 15 I 16 I 17 5962-9561 2 CAGE CODE 67268 REV STATUS OF

15、 SHEETS PMIC N/A STANDARD MICROCIRCUIT DRAWING THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS AND AGENCIES OF THE DEPARTMENT OF DEFENSE AMSC N/A 18 19 20 21 22 23 REV I I 1- SHEET iii2i3 PREPAREDBY Kenneth Rice CHECKED BY Jeff Bowling APPROVED BY Michael A. Frye DRAWING APPROVAL DATE 96-03-1 2

16、 REVISION LEVEL DEFENSE ELECTRONICS SUPPLY CENTER DAYTON, OHIO 45444 MICROCIRCUIT, MEMORY, DIGITAL, CMOS, 9500 GATE PROGRAMMABLE LOGIC ARRAY, MONOLITHIC SILICON SHEET 1 OF 25 )ESC FORM 193 JUL 94 DISTRIBUTION STATEMENT A Approved for public release: distribution is unlimited. 5962-E274-96 Provided b

17、y IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-SflD-5962-95632 999999b 00862b8 901 1. SCOPE 1.1 =. This drawing docunents tuo product assurance class levels consisting of high reliability (device classes A choice of case outlines and lead finishes are availab

18、le and are When available, a choice of Radiation Hardness Assurance (RHA) levels Q and M) and space application (device class Y). reflected in the Part or Identifying Nunber (PIN). are reflected in the PIN. 1.2 PIN. The PIN is be as shoun in the follouing example: 95612 T t I_ I Federal RHA Device D

19、evice Case Lead stock class designator type ci ass outline finish designator (1.2-1) (See 1.2.2) designator (See 1.2.4) (See 1.2.5) 11 L (See 1.2.3) / Drauing number 1.2.1 desianatoc . Device classes P and V RHA marked devices meet the MIL-PRF-38535 specified RHA levels and are marked uith the appro

20、priate RHA designator. Device class M RHA marked devices meet the MIL-PRF-38535, appendix A specified RHA levels and are marked uith the appropriate RHA designator. A dash (-) indicates a non-RHA device. 1.2.2 pevice tvmm . The device type(s) shall identify the circuit function as follows: Device tm

21、 Generic nuniber Circuit function Toaste SDe ed J./ 175 = actual number of pins used, not maximum listed in MIL-STD-1835 I Stresses above the absolute maximm rating may cause permanent damage to the device. maximm levels may degrade performance and affect reliability. indicated herein. Maximm juncti

22、on temperature shall not be exceeded except for allowable short duration burn-in screening conditions in accordance with method 5004 of MIL-STD-883. STANDARD MICROCIRCUIT DRAWING DEFENSEELECTRONICSSUPPLYCENTER DAYTON, OHIO 45444 Extended operation at the 2/ When a thermal resistance for this case is

23、 specified in MIL-STD-1835 that value shall supersede the value 4/ SIZE 5962-9561 2 A REVISION LEVEL SHEET 2 o1 I O2 3195A-05 31 95n - 04 9500 gate programble array 9500 gate programble array 4.1 ns 3.3 ns 1.2.3 Device class desimator. The device class designator is a single letter identifying the p

24、roduct assurance levei as follow: Device reau irements docume ntation I Device M Vendor self-certification to the requirements for MIL-STD-883 conpliant, non-JAN class level B microcircuits in accordance with MIL-PRF-38535, appendix A Q or V Certification and qualification to MIL-PRF-38535 1.2.4 use

25、 outl ine(Q. The case outline(s) are as designated in MIL-CTD-1835 and as follows: gutline Lette r pescrint ive desi- Termi na 1 s kkaae stvlp X Y 2 CMGAB- 175 See figure 1 See figure 1 175 1/ Pin grid array package 164 Quad flat package 164 Quad flat package 1.2.5 ni these tests shall have been fau

26、lt graded in accordance with MIL-STD-883, test method 5012 (see 1.5 herein). O/V (latch-up) tests shall be measured only for initial qualification and after any design or process changes which may affect the performance of the device. For device class M procedures and circuits shall be maintained un

27、der docunent revision level control by the manufacturer and shall be made available to the preparing activity or acquiring activity upon request. For device classes P and V, the procedures and circuits shall be under the control of the device manufacturers technical review board (TRB) in accordance

28、with MIL-PRF-38535 and shall be made available to the preparing activity or acquiring activity upon request. Testing shall be on all pins, on 5 devices uith zero failures. Latch-up test shall be considered destructive. Subgroup 4 (GIN and CwT measurements) shall be measured only for initial qualific

29、ation and after any process or design changes which may affect input or output capacitance. Capacitance shall be measured betueen the designated terminal and GND at a frequency of 1 MHz. Sample size is five devices uith no failures, and all input and output terminais tested. d. Information contained

30、 in JEDEC standard nunber 17 may be used for reference. e. I SIZE I I 5962-9561 2 REVISION LEVEL SHEET STANDARD MICROCIRCUIT DRAWING DEFENSE ELECTRONICS SUPPLY CENTER DAYTON, OHIO 45444 I I I DESC FORM 193A JUL 94 Provided by IHSNot for ResaleNo reproduction or networking permitted without license f

31、rom IHS-,-,-SMD-5962-95hL2 9999996 0086272 332 Group A Subgroups Device type TTL inputs TTL inputs CMOS inputs - 1,2,3 1,2,3 1,2,3 1,2,3 1,2,3 1,2,3 4 4 4 7,8A,8B Al l Al 1 Al 1 AL 1 Al 1 Al 1 AL L Al 1 AL 1 All 2233.8 1845.9 2193.4 1850.3 3742.2 3157.1 1233.6 1089.0 ns ns ns ns 9,10,11 9,10,11 9,10

32、,11 02 O1 02 O1 02 O1 02 TABLE I. Electrical tx rf ormance characteristia. Test Conditions 4.5 v 5 vcc 5 5.5 v -55OC 5 T, 5 +125OC unless otherulise specified OH = 4.5 V, VI = -8.0 Wi, b, = 2.0 V = 0.8V High Level output vol tage Lon level output vol tage VOL I A1 1,203 Vcc 5.5 V, IoL = 8.0V VIL - 0

33、.8 V, VI“ = 2.0 V Icco CMOS inputs, Vcc = VIN = 5.5 V 1,2,3 I ALL Quiescent poner supply Quiescent poner supply input leakage current Horizontal long Line, current current pul 1 -up current High Level input Lou level input voltage vo 1 taae TTL inputs, Vcc = VIN = 5.5 V 1,2,3 ALL cco IL = 5.5 v, VIN

34、 = o v vcLld 5.5 v 1,2,3 I All IRLL vcc = 5.5 v, VIN = o v and 5.5 V HT LT 1 HC High level input vo 1 tage LC Lou level input vo l tage CMOS inputs PR DUN = 0.0 V See 4.4.le PD Power down (PUR DUN)voltage z/ Input capacitance except XTL1 AND XTLZ 5N See 4.4.le Input capacitance XTL1 and XTLZ LIN Out

35、put capacitance See 4.4.le See 4.4.1 C, ,T Functional test %l 9,10,11 1 O1 t + 484(t) + OPF interconnect 82 %3 LO + OPF * Interconnect PID + 44t + OPF interconnect t84 See footnotes at end of table. STANDARD MICROCIRCUIT DRAWING DEFENSE ELECTRONICS SUPPLY CENTER DAYTON, OHIO 45444 5962-9561 2 REVISI

36、ON LEVEL SHEET I I I DESC FORM 193A JUL 94 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,- SND-5962-95bL2 9999996 O086273 279 TABLE I. 202 fC sg; =a K. %:Y, $3 .-. ELr.:i 01 no ?22 a w a YY 2M I T EN 07 I O*O *a O N O ao5 NOTES: 1. Dimensions are in

37、 inches. 2. lhe US goverment preferred system of *asurement is the metric SI system. However, this item was originally designed using inch-pound units of mesurement. the inch-pound units shall take precedence. 3. Packages are shipped flat as depicted &. Lead dimensions call out includes Lead finish.

38、 5. The leads of this package style shall be protected from mechanical distortion and damage such that dimensions pertaining to relative lead/body “true positions11 and Lead lkoplanarityll are always maintained until the next higher level package attachment process is complete. Package lead protecti

39、on mechanisms (tie bars) are shown on the drawing for reference only. When microcircuit devices contained in this package style are shipped for use in Goverrment equipnent, or shipped directly to the Goverrment as spare parts or mechanical qualification sanples, lead “true positiont8 and 18coplanari

40、ty11 protection shall be in place. Case Y represents marking the device on the nonlid side of device, i.e., lid side facing down. When mounted in this position, the pin out is clockwise. Case 2 represents marking the device on the lid side of the device i.e., lid side facing up. In the event of conf

41、lict between the metric and inch-pound units, 4. When mounted in this position, the pin out is counterclockwise. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-Inches mn inches .o010 O. 025 .O50 .o01 0.03 .O60 .o02 0.05 -080 .O04 0.10 .O86 .O05 0.13

42、 .O95 .O08 0.20 -1 O0 .o10 0.25 -115 .o12 0.30 .160 . O1 75 O .445 -200 .O18 O .46 .645 .o20 0.51 1 .o00 .o21 0.53 1.130 -025 0.64 1.290 .O30 0.76 1.500 .O40 1 .o2 2.300 2.500 2.03 2.18 2.54 2.92 4.06 5.08 16.38 25.50 28.70 32.77 38.10 58.42 63.50 NOTE: Metric equivalents are for reference only. JUL

43、 94 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-SMD-59b2-75bL2 D b 00tib27 797 STAN DARD MICROCIRCUIT DRAWING DEFENSE ELECTRONICS SUPPLY CENTER DAYTON, OHIO 45444 Device type SIZE A 5962-9561 2 SHEET REVISION LEVEL 13 Termi na i Mmber A2 A3 A4 A5

44、 A6 A7 A8 A9 Al O Al 1 A12 A13 A14 A15 A16 81 82 83 84 85 B6 67 88 BO B10 B11 812 613 814 BI5 616 Al L terminal symbo 1 NC NC I /O I /O I /o I /o I /o I /o I /o I /O I /o I /o 1 /o NC NC 110 PidRDY I /O I /o 1 /O I /O I /O I /o 1 /O I /o I /o I /o I /o- M1 -RDATA MO-RTRIG I /O C Device type Termi na

45、 l nunber CI c2 c3 c4 c5 C6 c7 CB c9 c10 c11 c12 C13 C14 CI5 CI6 D1 D2 03 04 05 D6 D7 DB D9 D10 D11 Dl2 D13 D14 e outline X Al 1 Terminal Symbol A8- I /O AP-I/O GND I /o I /o I /o I /o I /o I /o I /o I /o I /o I /o GND M2-1/0 I /o Al 1 - I/O I /o V TEfKIN-I/O I /o I /o I /o GND 3s I /o I /o I /O vcc

46、 _ Devi ce type Terminal nunber D15 D16 El E2 E3 E14 E15 El6 F1 F2 F3 F14 F15 Fl6 G1 G2 G3 G14 G15 G16 H1 H2 H3 H14 HI5 H16 J1 J2 J3 JI4 AL I Termina i symbol 1Lp LDC- i /O A7-1/0 I /O AIO-I/O HOC- I /O 1 /o I /o I /o A12- I/O I /o I /o I /o I /o I /o I /o I /o I /o 1 /o I /o A6-1/0 A13-1/0 vcc vcc

47、- INIT-1/0 I /o I /o I /o GND GND NC = no connect FIGURE 2. Terminal connectio nS. DESC FORM 193A JUL 94 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-SMD-5962-95612 9999996 0086280 409 Devi ce type Termi na 1 nunber J15 Jl6 K1 K2 K3 K14 K15 K16 L1

48、 L2 L3 L14 i15 Ll6 Ml M2 M3 M14 M15 Ml6 NI N2 N3 N4 U5 N6 17 AL I Terminal syinbol I /o I /o A5-I/O A14-1/0 I /o I /o I /o I /o I /o A4- 1/0 I /o I /o I /o I /o A15-1/0 I /o Al-CSZ-I/O I /o I /o I /o A3- 1/0 I /o GND DOUT-1/0 I /o I /o I /o Case outline X - Continued. Device type Termina 1 nunber N8

49、 N9 N10 N11 N12 N13 U14 NI5 N16 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 R1 ALL Termi na I s-1 GND 38 I /o I /o D7- I /O GND 1 /o I /o A2-UO AO-US- I /O V RDY/BUSY-RCLK-1/0 178 I /o I /o D3- I /O I /o I /o I /o D6- 1/0 I /o V XFEL2( IN)- I/O I /o I /o NC no connect FIGURE 2. Jerminal connectiom - Continued. Device type Terminal number R2 R3 R4 R5 R6 R7