DLA SMD-5962-95611 REV A-1996 MICROCIRCUIT MEMORY DIGITAL CMOS PROGRAMMABLE LOGIC CELL ARRAY MONOLITHIC SILICON《数字的互补金属氧化物半导体 可编程逻辑电池陈列硅单片电路线型微电路》.pdf

《DLA SMD-5962-95611 REV A-1996 MICROCIRCUIT MEMORY DIGITAL CMOS PROGRAMMABLE LOGIC CELL ARRAY MONOLITHIC SILICON《数字的互补金属氧化物半导体 可编程逻辑电池陈列硅单片电路线型微电路》.pdf》由会员分享，可在线阅读，更多相关《DLA SMD-5962-95611 REV A-1996 MICROCIRCUIT MEMORY DIGITAL CMOS PROGRAMMABLE LOGIC CELL ARRAY MONOLITHIC SILICON《数字的互补金属氧化物半导体 可编程逻辑电池陈列硅单片电路线型微电路》.pdf（28页珍藏版）》请在麦多课文档分享上搜索。

1、SMD-59b2-95bll REV A = 9999996 0090039 7T3 W DEFENSE LOGISTICS AGENCY DEFENSE SUPPLY CENTER COLUMBUS 3990 BROAD STREET COLUMBUS, OH 43216-5000 IN REPLY REFER TO: DSCC-VAS (Mr. K Rice/(DSN)850-053416 14-692-0534kr) OCT 3 0 1996 SUBJECT: Notice of Revision (NOR) 5962-Rol 1-97 for Standard Microcircuit

2、 Drawing (SMD) 5962-95611 Miiitary/Industry Distribution The enclosed NOR is approved for use effective as of the date of the NOR. In accordance with MIL-STD-100 SMD holders should, as a minimum, handwrite those changes described in the NOR to sheet 1 of the subject SMD. After completion, the NOR sh

3、ould be attached to the subject SMD for future reference. Those companies who were listed as approved sources of supply prior to this action have agreed to actions taken on devices for which they had previously provided DSCC a certificate of compliance. This is evidenced by an existing active curren

4、t certificate of compliance on file at DSCC with a DSCC record of verbal coordination. The certificate of compliance for these devices is considered concurrence with the new revision unless DSCC is otherwise notified. If you have comments or questions, please contact Ken Rice at (DSN)850-0534/(614)6

5、92-0534. 1 Encl Chief, Microelectronics Team Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-NOTICE OF REVISION (NOR) THIS REVISION DESCRIBED BELOW HAS BEEN AUTHORIZED FOR THE DOCUMENT LISTED. ubtic reporting, burden for,this giection Is estimated to

6、 average 2 hours per.response. induding me time for rewewin instructions. seain emsting data ACTIVITY NO. LEASE DO add IiAl1. Revisions description colum; add itchanges in accordance with NOR 5962-RO11-97ii. Revisions date colum; add 1i96-10-04ii. Rev status above sheet numbers 1 and 9, Revision lev

7、el block; ad iiA1l. Table 1, footnote 3/ Delete the last sentence of this footnote and replace it with the follouing: IiCharacterization data is taken initially end after any design or process change which may affect this parameter. II Revision level block; add iiA1l. add liAiI. Sheet 9: a. CURRENT

8、:ELL ARRAY, MONOLITHIC SILICON b. NEW A I. (xone) X (1) Existing document supplemented by the NOR may be used in manufacture. (2) Revised document must be received before manufacturer may incorporate this change. (3) Custodian of master document shall make above revision and furnish revised document

9、. i. TITE Microelectronics Team Chief 15a. ACTIVITY ACCOMPLISHING REVISION DSCC-VAS f. DATE SIGNED e. SIGNATURE (YYMMDD) Ray Monnin 96-10-04 c. DATE SIGNED b. REVISION COMPLETED (Signature) (YYMMDD) Kenneth S. Rice 96-10-04 Provided by IHSNot for ResaleNo reproduction or networking permitted without

10、 license from IHS-,-,-SMD-5962-95bLL 9999996 0086913 170 W LTR DESCRIPTiON DATE (YR-MO-DA) APPROVED SHEET =-Kt SHEET REV STATUS OF SHEETS PMIC NIA STANDARD MICROCIRCUIT DRAWING THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS AND AGENCIES OF THE DEPARTMENT OF DEFENSE AMSC NIA PREPAREDBY Kenneth

11、Rice CHECKED BY Jeff Bowling APPROVED BY Michael A. Frye DRAWING APPROVAL DATE 96-03-1 2 REVISION LEVEL DEFENSE ELECTRONICS SUPPLY CENTER DAYTON, OHIO 45444 MICROCIRCUIT, MEMORY, DIGITAL, CMOS, 9000 GATE PROGRAMMABLE LOGIC ARRAY, MONOLITHIC SILICON 1 CAiYID distribution is unlimited. Provided by IHS

12、Not for ResaleNo reproduction or networking permitted without license from IHS-,-,-SMD-5962-95b11 9999996 0086914 O07 W I. SCOPE 1.1 Scow. This drawing documents two product assurance class levels consisting of high reliability (device classes Q and M) and space application (device class V). A choic

13、e of case outlines and lead finishes are available and are reflected in the Part or Identifying N3 Electrical wrformance characteristics and Dostirradiation oarameter limits. Unless otherwise specified herein, the electrical performance characteristics and postirradiation parameter limits are as spe

14、cified in table I and shall apply over the full case operating temperature range. The electrical tests for each subgroup are defined in table I. 3.4 Electrical test reauirernents. The electrical test requirements shall be the subgroups specified in table IIA. 3.5 Marking. The part shall be marked wi

15、th the PIN listed in 1.2 herein. In addition, the manufacturers PIN may also be marked as listed in MIL-HDBK-103. For packages where marking of the entire SMD PIN nhr is not feasible due to space limitations, the manufacturer has the option of not marking the 115962-11 on the device. For RHA product

16、 using this option, the RHA designator shall still be marked. Marking for device classes Q and V shall be in accordance with MIL-PRF-38535. Marking for device class M shall be in accordance with MIL-PRF-38535, appendix A. 3.5.1 Certification/cmDliance mark. The certification mark for device classes

17、Q and V shall be a “QMLtl or iiQii as The compliance mark for device class M shall be a “C“ as required in MIL-PRF-38535, appendix required in MIL-PRF-38535. A. DESC FORM 193A JUL 94 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-SMD-5962-9563L 9999

18、996 0086937 836 W 4.2 Screeninq. For device classes Q and V, screening shall be in accordance with MIL-PRF-38535, and shall be conducted ,n all devices prior to qualification and technology conformance inspection. For device class M, screening shall be in accordance with method 5004 of MIL-STD-883,

19、and shall be conducted on all devices prior to quality conformance inspection. 4.2.1 Additional criteria for device class M. a. Delete the sequence specified as initial (pre-burn-in) electrical parameters through interim (post-burn-in) electrical parameters of method 5004 and substitute lines 1 thro

20、ugh 6 of table IIA herein. For device class M, the test circuit shall be maintained by the manufacturer under docunent revision level control and shall be made available to the preparing or acquiring activity upon request. For device class M the test circuit shall specify the inputs, outputs, biases

21、, and power dissipation, as applicable, in accordance with the intent specified in test method 1015. interim and final electrical test parameters shall be as specified in table IIA herein. b. c. 4.2.2 Additional criteria for device classes P and V. a. The burn-in test duration, test condition and te

22、st temperature, or approved alternatives shall be as specified in the device manufacturers QM plan in accordance with MIL-PRF-38535. The burn-in test circuit shall be maintained under docunent revision level control of the device manufacturers Technology Review Board (TRB) in accordance with MIL-PRF

23、-38535 and shall be made available to the acquiring or preparing activity upon request. The test circuit shall specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in test method 1015 of MIL-STD-883. Interim and final electrical test para

24、meters shall be as specified in table IA herein. Additional screening for device class V beyond the requirements of device class P shall be as specified in MIL- PRF-38535, appendix B. b. c. 4.3 Qualification insoection for device classes Q and V. Qualification inspection for device classes P and V s

25、hall Inspections to be performed shall be those specified in MIL-PRF-38535 and herein be in accordance with MIL-PRF-38535. for groups A, B, C, D, and E inspections (see 4.4.1 through 4.4.4). 4.4 Conformance insoection. Technology conformance inspection for classes Q and V shall be in accordance with

26、 MIL-PRF- 38535 including groups A, B, C, D, and E inspections and as specified herein except where option 2 of MIL-PRF-38535 permits alternate in-line control testing. Quality conformance inspection for device class M shall be in accordance with MIL-PRF-38535, appendix A and as specified herein. In

27、spections to be performed for device class M shall be those specified in method 5005 of MIL-STO-883 and herein for groups A, B, C, O, and E inspections (see 4.4.1 through 4.4.4). 4.4.1 Grouo A insDection. a. b. C. d. e. Tests shall be as specified in table IIA herein. Subgroups 5 and 6 of table I of

28、 method 5005 of MIL-STD-883 shall be omitted. For device class M subgroups 7, 8A and 88 tests shall consist of verifying functionality of the device. These tests form a part of the vendors test tape and shall be maintained and available upon request. For device classes Q and V subgroups 7, 8A and 8B

29、 shall include verifying the functionality of the device; these tests shall have been fault graded in accordance with MIL-STD-883, test method 5012 (see 1.5 herein). O/V (latch-up) tests shall be measured only for initial qualification and after any design or process changes which may affect the per

30、formance of the device. For device class M procedures and circuits shall be maintained under document revision level control by the manufacturer and shall be made available to the preparing activity or acquiring activity upon request. For device classes P and V, the procedures and circuits shall be

31、under the control of the device manufacturers technical review board (TRB) in accordance with MIL-PRF-38535 and shall be made available to the preparing activity or acquiring activity upon request. Testing shall be on all pins, on 5 devices with zero failures. Latch-up test shall be considered destr

32、uctive. Subgroup 4 (CIN and CwT measurements) shall be measured only for initial qualification and after any process or design changes which may affect input or output capacitance. Capacitance shall be measured between the designated terminal and GND at a frequency of 1 MHz. Sample size is five devi

33、ces with no failures, and all input and output terminals tested. Information contained in JEDEC standard number 17 may be used for reference. 5962-9561 l REVISION LEVEL SHEET STANDARD MICROCIRCUIT DRAWING DEFENSE ELECTRONICS SUPPLY CENTER DAYTON, OHIO 45444 I I EVEL I 5 JUL 94 Provided by IHSNot for

34、 ResaleNo reproduction or networking permitted without license from IHS-,-,-SMD-5962-75611 777777b 0086718 752 Group A Subgroups 1,2,3 1,2,3 1,2,3 Device type Al 1 Al 1 Al 1 Max 0.4 8 14 V V mA mA TABLE I. Electrical mrformance characteristics. Test Condi ti ons Limits Unit 4.5 v 5 vcc 5 5.5 v -55OC

35、 5 Tc 5 +125OC unless otherwise specified OH High Level output voltage Vcc 4.5 V, VIL = 0.8V IOH = -8.0 mA, VIH = 2.0 V vcc 5.5 v, IOL = 8.OV VIL = 0.8 v, VIH = 2.0 v Low level output vol tage VOL Quiescent power supply current Icco CMOS inputs, Vcc = VIN = 5.5 V Icco TTL inputs, Vcc = VIN = 5.5 V Q

36、uiescent power supply Input Leakage current current IIL vcc = 5.5 v, VIN o v and 5.5 V 1,2,3 I ALL IRLL = 5.5 v, VIN = o v 5.5 v Horizontal Long line, pull-up current High level input Low level input High level input Low level input voltage vol tage vol tage vo 1 tage “IHT TTL inputs TTL inputs CMOS

37、 inputs CMOS inputs PUR DUN = 0.0 V See 4.4.le See 4.4.le See 4.4.le See 4.4.1 V V “ILC PD Power down (PUR DUNIvoltage 2J IN Input capacitance except XTLI AND XTL2 Input capacitance XTLI and XTL2 Output capacitance Functional test PID + 320(t) + OPF IN + tB 1 1222.7 1232.2 2096.2 729.4 9, IO, 11 02

38、interconnect 83 + 320tpL0 + topF + tPL interconnect tB4 tp + OPUS + t + interconnect I 02 3e footnotes at end of table. 5962-9561 1 STANDARD MICROCIRCUIT DRAWING DEFENSEELECTRONICSSUPPLYCENTER DAYTON, OHIO 45444 I I REVISION LEVEL SHEET I I 6 1 I I DESC FORM 193A JUL 94 Provided by IHSNot for Resale

39、No reproduction or networking permitted without license from IHS-,-,-TABLE 1. Electrical performance characteristics - Continued. Device I Limits Test Conditions 4.5 v 5 vcc 5 5.5 v -55OC 5 TC. 5 +125OC unless otherwise specified Group A Subgroups tPID + 40tPUF + tOPF + interconnect 9,10,11 9,10,11

40、u 348.8 ns B6 t + 40t1 + t + interconnect 9,10,11 PID + 40t2 + t + interconnect 369.4 4.1 ns tIL0 3 See figures 4and 5 as applicable Logic input to output (combinational) Reset input to output 02 I 3.3 3 tRIO Reset direct width tRPW 3 %RQ Master reset pin to CLB output (X, Y) K clock input to CLB ou

41、tput 3 %KO Clock K to the outputs X or Y when P is return through function generators to drive X or Y K clock logic-input setup %LO I/ tICK %KI K clock logic-input Logic input setup to K hold clock o1 I 2.0 I I ns 02 1.6 I 1 I %KDI 3 Logic input hold from K clock t 3 Logic input setup to enable cloc

42、k Logic input hold to enable clock %KEC Al 1 1 .o ns ee footnotes at end of table. I SIZE I I 5962-9561 1 REVISION LEVEL SHEET STANDARD MICROCIRCUIT DRAWING DEFENSE ELECTRONICS SUPPLY CENTER DAYTON, OHIO 45444 DESC FORM 193A JUL 94 Provided by IHSNot for ResaleNo reproduction or networking permitted

43、 without license from IHS-,-,-SMD-5962-956LL - 9999996 0086920 300 TABLE 1. Electrical wrformance characteristics - Continued. I I Pad (package pin) to input direct 1/0 clock to 1/0 RI input (FFI I/O clock to pad-input setup 1/0 clock to pad-input 1/0 propagation delay clock (OK) to pad (fast) hold

44、1/0 clock to pad-output setup tOKPOf I/;o;ock to pad-output I Output (enabled fast) to pad output (enabled slow) to pad tops Master RESET to input RI I tRPO Master RESET to output (FFI %ID1 I Bidirectional buffer de 1 ay TBUF data input to output TBUF three-state to output active and (double pul 1-u

45、p) t IO tON1 - tON2 I ee footnotes at end of table. Conditions 4.5 v 5 vcc 5 5.5 v -55OC 5 Tr 5 +125OC unless otherw?se specified See figures 4 and 5 as applicable Grow A Device Limits Unit I SIZE I I 5962-9561 1 REVISION LEVEL SHEET STANDARD MICROCIRCUIT DRAWING DEFENSE ELECTRONICS SUPPLY CENTER DA

46、YTON, OHIO 45444 DESC FORM 193A JUL 94 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-SMD-5962-956LL = 9999996 0086923 247 TABLE I. Electrical mrformance characteristics - Continued. 1/ Tested initially and after any design or process change that ma

47、y affect this parameter and guaranteed to the limits specified in table i with the foilowing conditions: Global clock at 16 Mhz for device O1 and 25 MHz for device 02. 20 outputs at 5 MHz 50 outputs at 1 MHz Alternate clock at 10 MHz 100 configurable logic blocks (CLB) at 5 MHz 150 CLBs at 1 MHz 20

48、horizontal Long Lines at 5 MHz 30 vertical long lines at 1 MHz 50 inputs at 5 MHz 10 inputs at 10 MHz a PURDUN transitions must occur during operational Vcc levels. 3J Parameter is not directiy tested. Benchmark patterns (tgl-7).are then used to determine the compliance of this parameter. For class

49、M only characterization data is taken at initial device testing, prior to the introduction of significant changes, and at least twice yearly to monitor correlation between benchmark patterns and this parameter. Devices are first 100 percent functionally tested. 5962-9561 1 . REVISION LEVEL SHEET STANDARD MICROCIRCUIT DRAWING DEFENSE ELECTRONICS SUPPLY CENTER DAYTON, OHI