DLA SMD-5962-94611 REV T-2012 MICROCIRCUIT HYBRID MEMORY DIGITAL 512K x 32-BIT STATIC RANDOM ACCESS MEMORY CMOS.pdf

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1、 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED F Figure 1; changed case outline M to be available in either a single or dual cavity package. Added vendor CAGE code 0EU86 for device types 05 through 10. -sld 99-04-22 K. A. Cottongim G Added device types 11 through 16. 99-08-18 Raymond Monnin H A

2、dd note to paragraph 1.2.2 and table I, conditions. Add thermal resistance, junction-to-case (qJC) for all case outlines. Add case outline 9. 00-04-06 Raymond Monnin J Table I, ICCchange maximum limits and ISBchange maximum limits. Figure 1, case outline M, correct diagram adding “c“ dimension, lead

3、 thickness and change dimension A2 maximum from 0.020“ to 0.025“. 00-06-19 Raymond Monnin K Figure 1, case outline 9, minimum dimension for D2/E2, change 0.990 inches to 0.980 inches and 25.15 mm to 24.89 mm. 01-5-16 Raymond Monnin L Table I; Operating supply current (ICC) changed the maximum limit

4、for device types 9 and 15 at f = 50 MHz from 700 mA to 725 mA and for device types 10 and 16 at f = 58.8 MHz from 700 mA to 750 mA. -sld 01-12-21 Raymond Monnin M Added device types 17 through 20. -sld 02-11-18 Raymond Monnin N Added case outline A. -sld 03-02-24 Raymond Monnin P Added case outline

5、B. Added note to paragraph 1.2.4. -sld 03-12-19 Raymond Monnin R Table I; Changed the IOLfrom 8 mA to 6 mA for device types 07-10 and 13 -20 for the VOLtest. Editorial changes throughout. -sld 04-05-03 Raymond Monnin T Updated drawing paragraphs. -sld 12-09-12 Charles F. Saffle REV SHEET REV T T T T

6、 T T T T T T T T T T T T T SHEET 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 REV STATUS REV T T T T T T T T T T T T T T OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PMIC N/A PREPARED BY Gary Zahn DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 http:/www.landandmaritime.dla.mil/ STANDARD M

7、ICROCIRCUIT DRAWING CHECKED BY Michael C. Jones THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS AND AGENCIES OF THE DEPARTMENT OF DEFENSE APPROVED BY Kendall A. Cottongim MICROCIRCUIT, HYBRID, MEMORY, DIGITAL, 512K x 32-BIT, STATIC RANDOM ACCESS MEMORY, CMOS DRAWING APPROVAL DATE 95-11-13 AMSC

8、N/A REVISION LEVEL T SIZE A CAGE CODE 67268 5962-94611 SHEET 1 OF 31 DSCC FORM 2233 APR 97 5962-E471-12 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-94611 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 RE

9、VISION LEVEL T SHEET 2 DSCC FORM 2234 APR 97 1. SCOPE 1.1 Scope. This drawing documents five product assurance classes as defined in paragraph 1.2.3 and MIL-PRF-38534. A choice of case outlines and lead finishes which are available and are reflected in the Part or Identifying Number (PIN). When avai

10、lable, a choice of radiation hardness assurance levels are reflected in the PIN. 1.2 PIN. The PIN shall be as shown in the following example: 5962 - 94611 01 H A X Federal RHA Device Device Case Lead stock class designator type class outline finish designator (see 1.2.1) (see 1.2.2) designator (see

11、1.2.4) (see 1.2.5) / (see 1.2.3) / Drawing number 1.2.1 Radiation hardness assurance (RHA) designator. RHA marked devices shall meet the MIL-PRF-38534 specified RHA levels and shall be marked with the appropriate RHA designator. A dash (-) indicates a non-RHA device. 1.2.2 Device type(s). The device

12、 type(s) shall identify the circuit function as follows: Device type 1/ 2/ Generic number Circuit function Access time 01 S512K32-120 512K X 32-BIT SRAM 120 ns 02 S512K32-100 512K X 32-BIT SRAM 100 ns 03 S512K32-85 512K X 32-BIT SRAM 85 ns 04 S512K32-70 512K X 32-BIT SRAM 70 ns 05 S512K32-55 512K X

13、32-BIT SRAM 55 ns 06 S512K32-45 512K X 32-BIT SRAM 45 ns 07 S512K32-35 512K X 32-BIT SRAM 35 ns 08 S512K32-25 512K X 32-BIT SRAM 25 ns 09 S512K32-20 512K X 32-BIT SRAM 20 ns 10 S512K32-17 512K X 32-BIT SRAM 17 ns 11 S512K32-55 512K X 32-BIT SRAM 55 ns 12 S512K32-45 512K X 32-BIT SRAM 45 ns 13 S512K3

14、2-35 512K X 32-BIT SRAM 35 ns 14 S512K32-25 512K X 32-BIT SRAM 25 ns 15 S512K32-20 512K X 32-BIT SRAM 20 ns 16 S512K32-17 512K X 32-BIT SRAM 17 ns 17 S512K32-15 512K X 32-BIT SRAM 15 ns 18 S512K32-12 512K X 32-BIT SRAM 12 ns 19 S512K32-15 512K X 32-BIT SRAM 15 ns 20 S512K32-12 512K X 32-BIT SRAM 12

15、ns 1/ Due to the nature of the 4 transistor design of the die used in these device types, topologically pure testing is important, particularly for high reliability applications. The device manufacturer should be consulted concerning their testing methods and algorithms 2/ Device types 11 through 18

16、 are not tested to data retention supply voltage (VDR) and data retention current (ICCDR1). See table I. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-94611 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 R

17、EVISION LEVEL T SHEET 3 DSCC FORM 2234 APR 97 1.2.3 Device class designator. This device class designator shall be a single letter identifying the product assurance level. All levels are defined by the requirements of MIL-PRF-38534 and require QML Certification as well as qualification (Class H, K,

18、and E) or QML Listing (Class G and D). The product assurance levels are as follows: Device class Device performance documentation K Highest reliability class available. This level is intended for use in space applications. H Standard military quality class level. This level is intended for use in ap

19、plications where non-space high reliability devices are required. G Reduced testing version of the standard military quality class. This level uses the Class H screening and In-Process Inspections with a possible limited temperature range, manufacturer specified incoming flow, and the manufacturer g

20、uarantees (but may not test) periodic and conformance inspections (Group A, B, C, and D). E Designates devices which are based upon one of the other classes (K, H, or G) with exception(s) taken to the requirements of that class. These exception(s) must be specified in the device acquisition document

21、; therefore the acquisition document should be reviewed to ensure that the exception(s) taken will not adversely affect system performance. D Manufacturer specified quality class. Quality level is defined by the manufacturers internal, QML certified flow. This product may have a limited temperature

22、range. 1.2.4 Case outline(s). The case outline(s) shall be as designated in MIL-STD-1835 and as follows: Outline letter Descriptive designator Terminals Package style A See figure 1 68 Co-fired ceramic, quad flatpack, single cavity B See figure 1 68 Ceramic, quad flatpack, single cavity M 3/ See fig

23、ure 1 68 Co-fired ceramic, single/dual cavity, quad flatpack T See figure 1 66 Hex-in-line, single cavity, with standoffs U See figure 1 66 Hex-in-line, single cavity, with standoffs X See figure 1 66 Hex-in-line, single cavity, with standoffs Y See figure 1 68 Ceramic, quad flatpack, single cavity

24、9 3/ See figure 1 68 Ceramic, quad flatpack, single cavity 1.2.5 Lead finish. The lead finish shall be as specified in MIL-PRF-38534. 3/ Due to the short leads of case outlines M (single cavity) and case outline 9, caution should be taken if the system application is to be used where extreme thermal

25、 transitions can occur. Case outline A can be used if longer leads are necessary. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-94611 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL T SHEET 4

26、 DSCC FORM 2234 APR 97 1.3 Absolute maximum ratings. 4/ Supply voltage range (VCC) -0.5 V dc to +7.0 V dc Signal voltage range (Vg) . -0.5 V dc to VCC+0.5 V dc Power dissipation (PD): Device types 01-04 and 17-20 . 2.2 W Device types 05, 06, 11, and 12 3.2 W Device types 07, 08, 13, and 14 3.6 W Dev

27、ice types 09, 10, 15, and 16 4.4 W Thermal resistance, junction-to-case (qJC): Case outline A and M . 9.27 C/W Case outlines T, U, and X. 4.160 C/W Case outline Y 5.251 C/W Case outlines B and 9 1.495 C/W Storage temperature range -65 C to +150 C Lead temperature (soldering, 10 seconds) +300 C Junct

28、ion temperature (TJ) +150 C 1.4 Recommended operating conditions. Supply voltage range (VCC) +4.5 V dc to +5.5 V dc Input low voltage range (VIL) -0.3 V dc to +0.8 V dc Input high voltage range (VIH) +2.2 V dc to VCC+0.3 V dc Output low voltage, maximum (VOL) . +0.4 V dc Output high voltage, minimum

29、 (VOH) +2.4 V dc Ambient operating temperature range (TA) -55 C to +125 C 2. APPLICABLE DOCUMENTS 2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a part of this drawing to the extent specified herein. Unless otherwise specified, the

30、issues of these documents are those cited in the solicitation or contract. DEPARTMENT OF DEFENSE SPECIFICATION MIL-PRF-38534 - Hybrid Microcircuits, General Specification for. DEPARTMENT OF DEFENSE STANDARDS MIL-STD-883 - Test Method Standard Microcircuits. MIL-STD-1835 - Interface Standard for Elec

31、tronic Component Case Outlines. DEPARTMENT OF DEFENSE HANDBOOKS MIL-HDBK-103 - List of Standard Microcircuit Drawings. MIL-HDBK-780 - Standard Microcircuit Drawings. (Copies of these documents are available online at https:/assist.dla.mil/quicksearch/ or from the Standardization Document Order Desk,

32、 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.) 4/ Stresses above the absolute maximum rating may cause permanent damage to the device. Extended operation at the maximum levels may degrade performance and affect reliability. Provided by IHSNot for ResaleNo reproduction or networking

33、permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-94611 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL T SHEET 5 DSCC FORM 2234 APR 97 2.2 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein,

34、the text of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a specific exemption has been obtained. 3. REQUIREMENTS 3.1 Item requirements. The individual item performance requirements for device classes D, E, G, H, and K shall be in

35、 accordance with MIL-PRF-38534. Compliance with MIL-PRF-38534 shall include the performance of all tests herein or as designated in the device manufacturers Quality Management (QM) plan or as designated for the applicable device class. The manufacturer may eliminate, modify, or optimize the tests an

36、d inspections herein, however, the performance requirements as defined in MIL-PRF-38534 shall be met for the applicable device class. In addition, the modification in the QM plan shall not affect the form, fit, or function of the device for the applicable device class. 3.2 Design, construction, and

37、physical dimensions. The design, construction, and physical dimensions shall be as specified in MIL-PRF-38534 and herein. 3.2.1 Case outline(s). The case outline(s) shall be in accordance with 1.2.4 herein and figure 1. 3.2.2 Terminal connections. The terminal connections shall be as specified on fi

38、gure 2. 3.2.3 Truth table(s). The truth table(s) shall be as specified on figure 3. 3.2.4 Timing diagram(s). The timing diagram(s) shall be as specified on figures 4 and 5. 3.2.5 Block diagram. The block diagram shall be as specified on figure 6. 3.2.6 Output load circuit. The output load circuit sh

39、all be as specified on figure 7. 3.3 Electrical performance characteristics. Unless otherwise specified herein, the electrical performance characteristics are as specified in table I and shall apply over the full specified operating temperature range. 3.4 Electrical test requirements. The electrical

40、 test requirements shall be the subgroups specified in table II. The electrical tests for each subgroup are described in table I. 3.5 Marking of device(s). Marking of device(s) shall be in accordance with MIL-PRF-38534. The device shall be marked with the PIN listed in 1.2 herein. In addition, the m

41、anufacturers vendor similar PIN may also be marked. 3.6 Data. In addition to the general performance requirements of MIL-PRF-38534, the manufacturer of the device described herein shall maintain the electrical test data (variables format) from the initial quality conformance inspection group A lot s

42、ample, for each device type listed herein. Also, the data should include a summary of all parameters manually tested, and for those which, if any, are guaranteed. This data shall be maintained under document revision level control by the manufacturer and be made available to the preparing activity (

43、DLA Land and Maritime -VA) upon request. 3.7 Certificate of compliance. A certificate of compliance shall be required from a manufacturer in order to supply to this drawing. The certificate of compliance (original copy) submitted to DLA Land and Maritime -VA shall affirm that the manufacturers produ

44、ct meets the performance requirements of MIL-PRF-38534 and herein. 3.8 Certificate of conformance. A certificate of conformance as required in MIL-PRF-38534 shall be provided with each lot of microcircuits delivered to this drawing. Provided by IHSNot for ResaleNo reproduction or networking permitte

45、d without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-94611 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL T SHEET 6 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics. Test Symbol Conditions 1/ 2/ -55 C TC +125 C VSS= 0 V dc +4.5 V dc VCC +5.5 V

46、 dc unless otherwise specified Group A subgroups Device types Limits Unit Min Max DC parameters Operating supply current ICCCS = VIH, OE = VIH, VCC = 5.5 V dc 3/ f = 5 MHz f = 5 MHz f = 18.2 MHz f = 22.2 MHz f = 28.6 MHz f = 40 MHz f = 50 MHz f = 58.8 MHz f = 66.67 MHz f = 83.3 MHz 1,2,3 01-04 05-16

47、 05,11 06,12 07,13 08,14 09,15 10,16 17,19 18,20 200 600 625 635 650 675 725 750 200 250 mA Standby current ISBCS = VIH, OE = VIH, VCC = 5.5 V dc 3/ f = 5 MHz f = 5 MHz f = 18.2 MHz f = 22.2 MHz f = 28.6 MHz f = 40 MHz f = 50 MHz f = 58.8 MHz f = 66.67 MHz f = 83.3 MHz 1,2,3 01-04 05-16 05,11 06,12

48、07,13 08,14 09,15 10,16 17-20 17-20 4 80 150 150 190 240 280 320 80 80 mA Input leakage current ILIVCC= 5.5 V dc, VIN= GND or VCC1,2,3 All 10 mA Output leakage current ILOCS = VIH, OE = VIH, VIN= GND or VCC1,2,3 All 10 mA Output low voltage VOLVCC= +4.5 V dc, IOL= 2.1 mA 1,2,3 01-06, 11,12 0.4 V VCC= +4.5 V dc, IOL= 6 mA 07-10, 13-20 0.4 Output high voltage VOHVCC= +4.5 V dc, IOH= -1.0 mA 1,2,3 01-06, 11,12 2.4 V VCC= +4.5 V dc, IOH= -4.0 mA 07-10, 13-20 2.4 See footnotes at end of table. Provid