DLA SMD-5962-93252-1995 MICROCIRCUIT DIGITAL ADVANCED CMOS 1-TO-8 MINIMUM SKEW CLOCK DRIVER WITH MULTIPLEXED CLOCK INPUTS MONOLITHIC SILICON《硅单片 装有多路时钟输入的1-8最小失真时钟驱动器 改进型氧化物半导体数字微型.pdf

《DLA SMD-5962-93252-1995 MICROCIRCUIT DIGITAL ADVANCED CMOS 1-TO-8 MINIMUM SKEW CLOCK DRIVER WITH MULTIPLEXED CLOCK INPUTS MONOLITHIC SILICON《硅单片 装有多路时钟输入的1-8最小失真时钟驱动器 改进型氧化物半导体数字微型.pdf》由会员分享，可在线阅读，更多相关《DLA SMD-5962-93252-1995 MICROCIRCUIT DIGITAL ADVANCED CMOS 1-TO-8 MINIMUM SKEW CLOCK DRIVER WITH MULTIPLEXED CLOCK INPUTS MONOLITHIC SILICON《硅单片 装有多路时钟输入的1-8最小失真时钟驱动器 改进型氧化物半导体数字微型.pdf（19页珍藏版）》请在麦多课文档分享上搜索。

1、SMD-59b2-93252 9999996 00819Li3 351 W LTR t DATE (YR-MO-DA) APPROVED DESCRIPTION 18 REV SHEET I REV I I 1 12 3 4 5 6 7 8 9 1011121314 =-l- distribution is unlimited. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-SMD-59b2-93252 = 9999796 0081944 298

2、 W STANDARD MICROCIRCUIT DRAWING DEFENSEELECTRONICSSUPPLYCENTER DAYTON, OHIO 45444 1. SCOPE 1.1 u. This drawing forms a part of a one part - one part nuker docunentation system (see 6.6 herein). product assurance classes consisting of military high reliability (device classes P and M) and space appl

3、ication (device class V), and a choice of case outlines and lead finishes are available and are reflected in the Part or Identifying Nunber (PIN). 1.2.1 of MIL-STD-883, tlProvisions for the use of MIL-STD-863 in conjunction with conpliant non-JAN devicestt. available, EI choice of Radiation Hardness

4、 Assurance (RHA) levels are reflected in the PIN. Two Device class H microcircuits represent non-JAN class B microcircuits in accordance with Uhen 1.2 m. The PIN shall be as shown in the following example: Federal RHA 93252 Devi i ce 1 Devi ce 1 Case i Lead il stock class designator type ci ass outl

5、ine finish designator (see 1.2.1) (see 1.2.2) designator (see 1.2.4) (see 1.2.5) LA (see 1.2.3) / Drawing nunber 1.2.1 . Device class M RHA marked devices shall meet the MIL-1-38535 appendix A specified RHA levels and shall be marked with the appropriate RHA designator. MIL-1-38535 specified RHA lev

6、els and shall be marked with the appropriate RHA designator. non-RHA device. Device classes Q and V RHA marked devices shall meet the A dash (-1 indicates a 1.2.2 Device tm . The device type(s) shall identify the circuit function as follows: Device tm Epneric WJJILXL ircuit function SIZE A 5962-9325

7、2 REVISION LEVEL SHEET 2 o1 54AC2526 1-to-8 minim skew clock driver with multiplexed clock inputs 1.2.3 Device class decjanatar . lhe device class designator shall be a single letter identifying the product assurance level as follows: Device CL M Vendor self-certification to the requirements for non

8、-JAN class B microcircuits in accordance with 1.2.1 of MIL-STD-883 Q or V Certification and qualification to MIL-1-38535 . 1.2.4 Case outline(a The case outline(s) shall be as designated in MIL-STD-1835, and as follows: Outline letter Descr i Dt ive de5 ianator Jermi na 1s - I E F 2 GDIPl-T16 or CDI

9、PZ-T16 16 Dual - in- 1 i ne GDFP2-Fl6 or CDFP3-Fl6 16 Flat pack CPCC1 -I20 20 Leadless-chip-carrier Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,- - - SMD-5962-93252 W 9999996 0081945 124 W STANDARD MICROCIRCUIT DRAWING DEFENSEELECTRONICSSUPPLYCENT

10、ER DAYTON, OHIO 45444 1.3 Absolute - ua5J Supply voltage range (V c) . DC input vottage range LI,) DC output voltage range (V ) . DC input cianp current (i,?! VIw=-O-SV . VII=Vcc+O.5V DC output clanp current (IOK): -0.5V DC output current (Iw 1 per output pin OC vCc or GND current Ticc, per pin . St

11、orage tenperature range (1 lead temperature (soldering,S!8 seconds) Thermal resistance, junction- to-case (3 Jc) Junction temperature (TJ) . Maxim power dissipation (P,) . : Vcc + 0.5 V. - Uz/ and the absolute value of the magnitude, not the sign, is relative to the minim and maximm limits, as appli

12、cable, listed herein. Specified in table I, as applicable, at 3.0 V Vcc s 3.6 V and 4.5 V L Vcc i 5.5 V. All devices shall meet the limits For device classes Q and V, this test is guaranteed, if not tested, to the limits specified in table I herein. Transmission driving tests are performed at Vcc =

13、5.5 V dc with a 2 ms duration maxim. performed using VIN = Vcc or GND. This test may be When VIN = VIN or GND, the test is guaranteed for VIN = VIH or VIL. Power dissipation capacitance (CpD) shall be tested by loading all outputs with a 50 pF minim load capacitance (measured from output pin to GND)

14、 and conditioning CKO with the signal specified in table I, herein. input pins, CK1 and SEL are tied to 0.0 V. using the following equation: The other CpD is then calculated The resulting Icc current is then measured. I CCD - 400 pF cpD = vcc x 106 where ICCD is the Icc measured. Under the condition

15、s specified in table I, herein, for CKO and CKI over frequencies (f) of 1 MHz to 100 MHz, CpD is guaranteed to meet the limits calculated uith the foliouing equation: CpD = 850 PF - (1.2 X x f) CpD determines both the power consunption (PD) and current consuiption (Is). Where and f is the frequency

16、of the input signal and CL is the external output load capacitance. See JEDEC Standard No. 17 for electrically induced latch-up test methods and procedures. Vtrigger, Itrigger, and Vover are to be accurate within 15 percent. The values listed for Tests shall be performed in sequence, attributes data

17、 only. Functional tests shall include the truth table and other logic patterns used for fault detection. minimun, test all functions of each input and output. All possible input to output logic patterns per function shall be guaranteed, if not tested, to the truth table in figure 2 herein. Functiona

18、l tests shall be performed in sequence as approved by the qualifying activity on qualified devices. - 4.5 V and 5.5 V, H r 2.5 V and L 2.5 V. For Vcc = 3.0 V and 3.6 V, H L 1.5 V and L 1.5 V. Alternative at Vcc = 4.5 V, VIH minimun +20% = 3.78 V and VIL maxim -!O% = 0.68 V), and guarantee tkis test

19、uith input levels of VIH minimun and VIL maxim. The test vectors used to verify the truth table shall, at a For V are acceptable. For all device classes, functional tests at V I 5962-93252 STAN DARD MICROCIRCUIT DRAWING SHEET REVISION LEVEL DEFENSE ELECTRONICS SUPPLY CENTER DAYTON, OHIO 45444 I I I

20、DESC FORM 193A JUL 94 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-TABLE I. Electrical wrformance characteristics - Continued. ip/ AC Limits at Vcc = 5.5 V are equal to the limits at Vcc = 4.5 V and guaranteed by testing at Vcc = 4.5 V. AC Limits

21、at Vc Minimm propagation SeTay time limits for Vcc = 5.5 V and Vcc 3.6 V are guaranteed by guardbanding the minimun limits for testing at Vcc = 4.5 V and Vcc = 3.0 V, respectively, to 0.5 ns greater than the limits specified in table I, herein. For propagation delay tests, all paths mist be tested.

22、These tests shall be measured only for initial qualification and 3.6 V are equal to the limits at Vcc = 3.0 V and guaranteed by testing at Vcc = 3.0 V. 11/ This test is required only for Group A testing. after process or design changes which may affect dynamic performance (see 4.4.1 herein). u/ For

23、skew parameters, toskH is the absolute value of the difference between the tpLH of an output tan and the tpLH of any other output On, tpHL of any other cutput ErL is the absolute value of the difference between tEe maxim tpLH of any output Un and with the minimm tpHL kny output On, and also the abso

24、lute value of the difference between the maximun tpHL of any output Om and with the minim tp between the tpHL ay tpL of any output Un. !e limits for t the two test conditions ror tOST as described herein. For el?Skeu parameters, m = O to 7; n = O to 7; and m is not equal to n. is the absolute value

25、of the difference between the t HL of an output Un and the of any output On; and tps is the absolute value of the difference specified in table I, herein, apply to either of I SIZE I I IAI I 5962-93252 STAN DARD MICROCIRCUIT DRAWING DEFENSE ELECTRONICS SUPPLY CENTER DAYTON, OHIO 45444 I SHEET1l REVI

26、SION LEVEL DESC FORM 193A JUL 94 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-Case out 1 inei 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Terminal symbol CKO, CK1 SEL On (n = O to 7) o1 Description Clock inputs Select input Outputs - Terminal S

27、TANDARD MICROCIRCUIT DRAWING DEFENSE ELECTRONICS SUPPLY CENTER DAYTON, OHIO 45444 S SIZE 5962-93252 A REVISION LEVEL SHEET 12 O0 02 NC GND vcc SEL o4 o6 07 05 CK1 GND vcc CKO 03 o1 - _- -_ - ml NC O0 02 NC GND NC vcc SEL o4 o6 NC 07 05 CK1 GND NC “cc CKO 03 o1 FIGURE 1. Terminal connections. Provide

28、d by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-I Inputs I outputs I H = High voltage level L = L3u voltage level X = Irrelevant FIGURE 2. Truth tabla. CKO CK1 SEL I SIZE 5962-93252 A STANDARD MICROCIRCUIT DRAWING DEFENSEELECTRONICSSUPPLYCENTER DAYTON, OHIO

29、 45444 SHEET REVISION LEVEL 13 DESC FORM 193A JUL 94 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-SMD-5962-93252 m 9999996 OOBL95b TOT TO VCC OR GND AS REQUIRED - “OUT VIN DEVICE La - UNDER TEST PULSE GENERATOR Gb - A 7FL - - - SIZE A STAN DARD MI

30、CROCIRCUIT DRAWING DEFENSE ELECTRONICS SUPPLY CENTER DAYTON, OHIO 45444 REVISION LEVEL 5962-93252 SHEET 14 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-. 4.2.1 a. Witional critwia for device cla. Burn-in test, method 1015 of MIL-STD-883. (1) lest

31、condition A, B, C, or D. The test circuit shall be maintained by the manufacturer under docunent revision level control and shall be made available to the preparing or acquiring activity upon request. The test circuit shall specify the inputs, outputs, biases, and puer dissipation, as applicable, in

32、 accordance uith the intent specified in test method 1015. (2) TA = +125C, mininun. (3) For device class M, unless otheruise noted, method 1015 of MIL-STD-883 shall be followed. 4.2.2 a. criteria for device classes Q and 1. The burn-in test duration, test condition and test temperature, or approved

33、alternatives shall be as specified in the device manufacturers QM plan in accordance uith MIL-1-38535. The burn-in test circuit shall be maintained under docunent revision level control of the device manufacturers Technology Review Board (TRB) in accordance uith MIL-1-38535 and shall be made availab

34、le to the preparing or acquiring activity upon request. lhe test circuit shall specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance uith the intent specified in test method 1015. b. Interim and final electrical test parameters shall be as Specified in table II her

35、ein. c. Additional screening for device class V beyond the requirements of device class P shall be as specified in appendix B of MIL-1-38535. a and v . 4.3 Ulification inswction for device classes Qualification inspection for device classes a and V shall Inspections to be performed shall be those sp

36、ecified in MIL-1-38535 and herein for . . x in accordance with MIL-1-38535. groups A, B, C, D, and E inspections (see 4.4.1 through 4.4.4). . Electrostatic discharge sensitivity (ESDS) itivitv wlification inswction 4.3.1 Electrostatic discharse sens ESDS testing shall be measured only for . . ,. tes

37、ting shall be performed in accordance with MIL-STD-883, method 3015. initial qualification and after process or design changes which may affect ESDS Classification. 4.4 -rice insDect ioo. Quality conformance inspection for device class M shall be in accordance uith IIL-STD-883 (see 3.1 herein) and a

38、s specified herein. Inspections to be performed for device class M shall be those ipecified in method 5005 of MIL-STD-883 and herein for groups A, E, C, D, and E inspections (see 4.4.1 through 4.4.4). iechnology conformance inspection for classes P and V shall be in accordance with MIL-1-38535 inclu

39、ding groups A, B, :, D, and E inspections and as specified herein except where option 2 of MIL-1-38535 permits alternate in-line control test i ng . 4.4.1 Uction. a. b. lests shall be as specified in table il herein. For device class M, subgroups 7 and 8 tests shall be sufficient to verify the truth

40、 table in figure 2 herein. lhe test vectors used to verify the truth table shall test all possible input to output logic patterns. device classes and V, subgroups 7 and 8 shall include verifying the functionality of the device; these tests shall have been fault graded in accordance with MIL-STD-883,

41、 test method 5012 (see 1.5 herein). a#!ect capacitance. CI shall be measured between the designated terminal and GND at a frequency of 1 MHz. For CI, and CpD, test ar1 amticable pins on five devices with zero failures. Latch-up tests are required for device classes P and V. qualification and after p

42、rocess or design changes which may affect the performance of the device. tests shall be considered destructive. lhe tOSHL, tOSLH, t ST, tpS,.t ISE, and tFA tests shall be measured only for initial qualification and after process or design cflanges whicl may affect hynamic performance. Test twelve de

43、vices at lC = -55“C, +25*C, and +125“C, with zero failures. The group C inspection end-paint electrical parameters shall be as specified in table II For c. C and CpD shall be measured only for initial qualification and after process or design changes which may d. These tests shall be performed only

44、for initial Catch-up Test all applicable pins on five devices with zero failures. e. 4.4.2 GrouD C i nsoec t ion. herein. STAN DARD MICROCIRCUIT DRAWING DEFENSEELECTRONICSSUPPLYCENTER DAYTON, OHIO 45444 5962-93252 REVISION LEVEL SHEET I I I DESC FORM 193A JUL 94 Provided by IHSNot for ResaleNo repro

45、duction or networking permitted without license from IHS-,-,-SMD-5762-93252 m 7999996 0083758 882 m L U PDA applies to subgroup 1. PDA applies to subgroups 1 and 7. 3 Delta limits shall be required only on table I, subgroup 1. be computed with reference to the previous interim electrical parameters.

46、 limits are specified in table III. lhe delta values shall lhe delta TABLE III. peita limits at +25“C. Parameter U Device types Limits Al 1 I100 nA * CCHI ICCL u These parameters shall be recorded before and after the required burn-in and life test to determine the delta limits. 4.4.2.1 gdditi onal

47、criteria fo r device class H . Steady-state life test conditions, methcd 1005 of MIL-STO-883: a. Test condition A, i, C or D. lhe test circuit shall be maintained by the manufacturer under docunent revision level control and shall be made available to the preparing or acquiring activity upon request

48、. circuit shall specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in test method 1005. lhe test b. TA +125“C, minim. c. Test duration: 1,000 hours, except as permitted by method 1005 of MIL-STD-883. 4.4.2.2 Additional criteria for devi

49、ce ctasses P and V. The steady-state life test duration, test condition and test temperature, or approved alternatives shall be as specified in the device manufacturers QM plan in accordance with MIL-1-38535. manufacturers TRB in accordance with MIL-1-38535 and shall be made available to the preparing or acquiring activity upon request. The test circuit shall specify the inputs, outputs, biase