DLA SMD-5962-93247 REV B-2013 MICROCIRCUIT MEMORY DIGITAL CMOS ELECTRICALLY ERASABLE PROGRAMMABLE LOGIC ARRAY MONOLITHIC SILICON.pdf

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1、REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Changes in accordance with NOR 5962-R146-95 95-05-30 Michael A. Frye B Update boilerplate to meet current MIL-PRF-38535 requirements. - glg 13-11-15 Charles F. Saffle REV SHEET REV B B B B B B B B SHEET 15 16 17 18 19 20 21 22 REV STATUS REV B B B

2、 B B B B B B B B B B B OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PMIC N/A PREPARED BY Kenneth Rice DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 http:/www.landandmaritime.dla.mil STANDARD MICROCIRCUIT DRAWING CHECKED BY Jeff Bowling THIS DRAWING IS AVAILAALE FOR USE AY ALL DEPARTMENTS APPRO

3、VED BY Michael Frye MICROCIRCUIT, MEMORY, DIGITAL, CMOS, ELECTRICALLY ERASABLE PROGRAMMABLE LOGIC ARRAY, MONOLITHIC SILICON AND AGENCIES OF THE DEPARTMENT OF DEFENSE DRAWING APPROVAL DATE 95-02-07 AMSC N/A REVISION LEVEL B SIZE A CAGE CODE 67268 5962-93247 SHEET 1 OF 22 DSCC FORM 2233 APR 97 5962-E0

4、59-14 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-93247 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 2 DSCC FORM 2234 APR 97 1. SCOPE 1.1 Scope. This drawing documents two produc

5、t assurance class levels consisting of high reliability (device classes Q and M) and space application (device class V). A choice of case outlines and lead finishes are available and are reflected in the Part or Identifying Number (PIN). When available, a choice of Radiation Hardness Assurance (RHA)

6、 levels are reflected in the PIN. 1.2 PIN. The PIN is as shown in the following example: 5962 - 93247 01 M X A Federal stock class designator RHA designator (see 1.2.1) Device type (see 1.2.2) Device class designator Case outline (see 1.2.4) Lead finish (see 1.2.5) / (see 1.2.3) / Drawing number 1.2

7、.1 RHA designator. Device classes Q and V RHA marked devices meet the MIL-PRF-38535 specified RHA levels and are marked with the appropriate RHA designator. Device class M RHA marked devices meet the MIL-PRF-38535, appendix A specified RHA levels and are marked with the appropriate RHA designator. A

8、 dash (-) indicates a non-RHA device. 1.2.2 Device type(s). The device type(s) shall identify the circuit function as follows: Device type Generic number Circuit function Access time 01 7256E 256-Macrocell EEPLD 20 ns 02 7256E 256-Macrocell EEPLD 15 ns 1.2.3 Device class designator. The device class

9、 designator is a single letter identifying the product assurance level as follows: Device class Device requirements documentation M Vendor self-certification to the requirements for MIL-STD-883 compliant, non-JAN class level B microcircuits in accordance with MIL-PRF-38535, appendix A Q or V Certifi

10、cation and qualification to MIL-PRF-38535 1.2.4 Case outline(s). The case outline(s) shall be as designated in MIL-STD-1835 and as follows: Outline letter Descriptive designator Terminals Package style X CMGA9-P192 192 1/ pin grid array Y see figure 1 208 2/ quad flat pack 1.2.5 Lead finish. The lea

11、d finish is as specified in MIL-PRF-38535, appendix A. _ 1/ 192 = actual number of pins used, not maximum listed in MIL-STD-1835. 2/ 208 = actual number of pins used, not maximum listed in MIL-STD-1835. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,

12、-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-93247 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 3 DSCC FORM 2234 APR 97 1.3 Absolute maximum ratings. 3/ Supply voltage range with respect to ground (VCC).-2.0 V dc to +7.0 V dc 4/ Programming supply voltage range with respect t

13、o ground (VPP).-2.0 V dc to +13.0 V dc 4/ DC input voltage range with respect to ground -2.0 V dc to +7.0 V dc 4/ DC VCCor GND current (IMAX) 800 mA DC output current, per pin IOUT + 25 mA Storage temperature range -65C to +150C Lead temperature (soldering, 10 seconds) +260C Thermal resistance, junc

14、tion-to-case (JC): . See MIL-STD-1835 Case Y 12C/W Maximum power dissipation 5/ 4.0 W Temperature under bias range -65C to +135C Junction temperature (TJ). +175C Endurance 100 erase/write cycles (minimum) Data retention 10 years (minimum) 1.4 Recommended operating conditions. Supply voltage range (V

15、CC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +4.5 V dc to +5.5 V dc Input voltage range (VIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0 V dc to VCCOutput voltage range (VOUT) . . . . . . . . . . . . . . . . . . . . . . .

16、 . . . . . . . . . . . . . . . . . 0 V dc to VCCInput rise time (tR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 ns maximum Input fall time (tF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 ns

17、maximum Case operating temperature range (TC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55C to +125C 6/ 2. APPLICABLE DOCUMENTS 2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a part of this drawing to the extent s

18、pecified herein. Unless otherwise specified, the issues of these documents are those cited in the solicitation or contract. DEPARTMENT OF DEFENSE SPECIFICATION MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for. DEPARTMENT OF DEFENSE STANDARDS MIL-STD-883 - Test Method Sta

19、ndard Microcircuits. MIL-STD-1835 - Interface Standard Electronic Component Case Outlines. DEPARTMENT OF DEFENSE HANDBOOKS MIL-HDBK-103 - List of Standard Microcircuit Drawings. MIL-HDBK-780 - Standard Microcircuit Drawings. (Copies of these documents are available online at http:/quicksearch.dla.mi

20、l or from the Standardization Document Order Desk, 700 Robins Avenue, Building 4D, Philadelphia, PA 19111-5094.) _ 3/ Stresses above the absolute maximum rating may cause permanent damage to the device. Extended operation at the maximum levels may degrade performance and affect reliability. 4/ When

21、the thermal resistance for this case is specified in MIL-STD-1835, that value shall supersede the value indicated herein. 5/ Minimum dc input voltage is -0.3 V. During transitions, inputs may undershoot to -2.0 V or overshoot to +7.0 V for periods shorter than 20 ns under no-load conditions. 6/ Must

22、 withstand the added PDdue to short circuit test (e.g., ISC). Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-93247 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 4 DSCC FORM 2234 APR

23、97 2.2 Non-Government publications. The following documents form a part of this document to the extent specified herein. Unless otherwise specified, the issues of the documents are the issues of the documents cited in the solicitation. JEDEC SOLID STATE TECHNOLOGY ASSOCIATION JESD 78 - IC Latch-Up T

24、est. (Applications for copies should be addressed to JEDEC Solid State Technology Association, 3103 North 10thStreet, Suite 240-S, Arlington, VA 22201-2107; http:/www.jedec.org.) (Non-Government standards and other publications are normally available from the organizations that prepare or distribute

25、 the documents. These documents also may be available in or through libraries or other informational services.) 2.3 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text of this drawing takes precedence. Nothing in this document, h

26、owever, supersedes applicable laws and regulations unless a specific exemption has been obtained. 3. REQUIREMENTS 3.1 Item requirements. The individual item requirements for device classes Q and V shall be in accordance with MIL-PRF-38535 and as specified herein or as modified in the device manufact

27、urers Quality Management (QM) plan. The modification in the QM plan shall not affect the form, fit, or function as described herein. The individual item requirements for device class M shall be in accordance with MIL-PRF-38535, appendix A for non-JAN class level B devices and as specified herein. 3.

28、2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified in MIL-PRF-38535, appendix A and herein. 3.2.1 Case outline(s). The case outline(s) shall be in accordance with 1.2.2 herein. 3.2.2 Terminal connections. The terminal connections

29、shall be as specified on figure 1. 3.2.3 Truth table(s). The truth table(s) shall be as specified on figure 2. 3.2.3.1 Unprogrammed devices. The truth table for unprogrammed devices for contracts involving no altered item drawing shall be as specified on figure 2. When required in screening (see 4.2

30、 herein) or qualification conformance inspection, groups A, B, C, or D (see 4.3 herein), the devices shall be programmed by the manufacturer prior to test. A minimum of 50 percent of the total number of cells shall be programmed or at least 25 percent of the total number of cells to any altered item

31、 drawing. 3.2.3.2 Programmed devices. The truth table for programmed devices shall be as specified by an attached altered item drawing. 3.3 Electrical performance characteristics. Unless otherwise specified herein, the electrical performance characteristics are as specified in table I and shall appl

32、y over the full case operating temperature range. 3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table II. The electrical tests for each subgroup are described in table I. 3.5 Marking. Marking shall be in accordance with MIL-PRF-38535, appendix

33、 A. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturers PIN may also be marked. For packages where marking of the entire SMD PIN number is not feasible due to space limitations, the manufacturer has the option of not marking the “5962-“ on the device. 3.5.1 Cer

34、tification/compliance mark. A compliance indicator “C” shall be marked on all non-JAN devices built in compliance to MIL-PRF-38535, appendix A. The compliance indicator “C” shall be replaced with a “Q“ or “QML“ certification mark in accordance with MIL-PRF-38535 to identify when the QML flow option

35、is used. 3.6 Certificate of compliance. A certificate of compliance shall be required from a manufacturer in order to be listed as an approved source of supply in MIL-HDBK-103 (see 6.6 herein). The certificate of compliance submitted to DLA Land and Maritime-VA prior to listing as an approved source

36、 of supply shall affirm that the manufacturers product meets the requirements of MIL-PRF-38535, appendix A and the requirements herein. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-93247 DLA LAND AND MARIT

37、IME COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 5 DSCC FORM 2234 APR 97 3.7 Certificate of conformance. A certificate of conformance as required in MIL-PRF-38535, appendix A shall be provided with each lot of microcircuits delivered to this drawing. 3.8 Notification of change. Notification of c

38、hange to DLA Land and Maritime-VA shall be required for any change that affects this drawing. 3.9 Verification and review. DLA Land and Maritime, DLA Land and Maritimes agent and the acquiring activity retain the option to review the manufacturers facility and applicable required documentation. Offs

39、hore documentation shall be made available onshore at the option of the reviewer. 3.10 Processing of EEPLDs. All testing requirements and quality assurance provisions herein shall be satisfied by the manufacturer prior to delivery. 3.10.1 Conditions of supplied devices. Devices will be supplied is e

40、rased state. No provision will be made for supplying written devices. 3.10.2 Writing of EEPLDs When specified, devices shall be written in accordance with procedures and characteristics specified in 4.6. 3.10.3 Clearing of EEPLDs. When specified, devices shall be cleared in accordance with the proce

41、dures and characteristics specified in 4.7. 3.10.4 Verification of state of EEPLDs. When specified, devices shall be verified as either written to the specified pattern or cleared. As a minimum, verification shall consist of performing a functional test (subgroup 7) to verify that all bits are in th

42、e proper state. Any bit that does not verify to be in the proper state shall constitute a device failure, and shall be removed from the lot or sample. 3.11 Endurance. A reprogrammability test shall be completed as part of the vendors reliability monitors, this reprogrammability test shall be done on

43、ly for initial characterization and after any design or process changes which may affect the reprogrammability of the device. The methods and procedures may be vendor specific, but will guarantee the number of program/erase endurance cycles listed in section 1.3 herein over the full military tempera

44、ture range. The vendors procedure shall be under document control and shall be made available upon request. 3.12 Data retention. A data retention stress test shall be completed as part of the vendors reliability monitors, This test shall be done only for initial characterization and after any design

45、 or process changes which may affect data retention of the device. The methods and procedures may be vendor specific, but will guarantee the number of program/erase endurance cycles listed in section 1.3 herein over the full military temperature range. The vendors procedure shall be under document c

46、ontrol and shall be made available upon request. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-93247 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 6 DSCC FORM 2234 APR 97 TABLE I. E

47、lectrical performance characteristics. Test Symbol Conditions -55C TC +125C 4.5 V VCC 5.5 V Group A subgroups Device type Limits Unit unless otherwise specified Min Max Output high voltage VOHVCC= 4.5 V, VIH= 2.0 V, IOH= -4.0 mA, VIL= -0.8 V 1, 2, 3 All 2.4 V Output low voltage VOLVCC= 4.5 V, VIH= 2.0 V, IOL= 8.0 mA, VIL= 0.8 V 1, 2, 3 All 0.45 Input high voltage VIH1, 2, 3 All 2.0 VCC+0.3 Input low voltage VIL1, 2, 3 All -0.3 0.8 Input leakage current ILVCC= 5.5 V, VIN= 5.5 V and GND 1, 2, 3 All -10 10 A Output linkage current IOZVCC= 5.5 V, VOUT= 5.5 V and GND 1, 2, 3 All