DLA SMD-5962-93195 REV C-2008 MICROCIRCUIT LINEAR 12-BIT + SIGN DATA ACQUISITION SYSTEM WITH SELF-CALIBRATION MONOLITHIC SILICON《线性单硅片微电路 带12比特的自校标识数据采集系统》.pdf

《DLA SMD-5962-93195 REV C-2008 MICROCIRCUIT LINEAR 12-BIT + SIGN DATA ACQUISITION SYSTEM WITH SELF-CALIBRATION MONOLITHIC SILICON《线性单硅片微电路 带12比特的自校标识数据采集系统》.pdf》由会员分享，可在线阅读，更多相关《DLA SMD-5962-93195 REV C-2008 MICROCIRCUIT LINEAR 12-BIT + SIGN DATA ACQUISITION SYSTEM WITH SELF-CALIBRATION MONOLITHIC SILICON《线性单硅片微电路 带12比特的自校标识数据采集系统》.pdf（21页珍藏版）》请在麦多课文档分享上搜索。

1、 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Add case outline Z for vendor CAGE 27014. Editorial changes throughout. 97-01-28 Ray Monnin B Change limits for test parameter Differential non-linearity, group A subgroup 2 to max LSB. -lgt 99-07-21 Ray Monnin C Redraw. Update drawing to current

2、 requirements. - drw 08-06-11 Robert M. Heber REV SHET REV C C C C C C SHEET 15 16 17 18 19 20 REV STATUS REV C C C C C C C C C C C C C C OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PMIC N/A PREPARED BY Sandra Rooney CHECKED BY Sandra Rooney DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3

3、990 http:/www.dscc.dla.mil APPROVED BY Michael A. Frye STANDARD MICROCIRCUIT DRAWING THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS AND AGENCIES OF THE DEPARTMENT OF DEFENSE DRAWING APPROVAL DATE 94-08-18 MICROCIRCUIT, LINEAR, 12-BIT + SIGN DATA, ACQUISITION SYSTEM WITH SELF-CALIBRATION, MONOL

4、ITHIC SILICON AMSC N/A REVISION LEVEL C SIZE A CAGE CODE 67268 5962-93195 SHEET 1 OF 20 DSCC FORM 2233 APR 97 5962-E408-08 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-93195 DEFENSE SUPPLY CENTER COLUMBUS

5、COLUMBUS, OHIO 43218-3990 REVISION LEVEL C SHEET 2 DSCC FORM 2234 APR 97 1. SCOPE 1.1 Scope. This drawing documents two product assurance class levels consisting of high reliability (device classes Q and M) and space application (device class V). A choice of case outlines and lead finishes are avail

6、able and are reflected in the Part or Identifying Number (PIN). When available, a choice of Radiation Hardness Assurance (RHA) levels is reflected in the PIN. 1.2 PIN. The PIN is as shown in the following example: 5962 - 93195 01 Q X C Federal stock class designator RHA designator (see 1.2.1) Device

7、 type (see 1.2.2)Device class designatorCase outline (see 1.2.4) Lead finish (see 1.2.5) / (see 1.2.3) / Drawing number 1.2.1 RHA designator. Device classes Q and V RHA marked devices meet the MIL-PRF-38535 specified RHA levels and are marked with the appropriate RHA designator. Device class M RHA m

8、arked devices meet the MIL-PRF-38535, appendix A specified RHA levels and are marked with the appropriate RHA designator. A dash (-) indicates a non-RHA device. 1.2.2 Device types. The device types identify the circuit function as follows: Device type Generic number Circuit function 01 12458 12-bit

9、+ sign data acquisition system with self-calibration, 5 MHz 02 12H458 12-bit + sign data acquisition system with self-calibration, 8 MHz 1.2.3 Device class designator. The device class designator is a single letter identifying the product assurance level as follows: Device class Device requirements

10、documentation M Vendor self-certification to the requirements for MIL-STD-883 compliant, non-JAN class level B microcircuits in accordance with MIL-PRF-38535, appendix A Q or V Certification and qualification to MIL-PRF-38535 1.2.4 Case outlines. The case outlines are as designated in MIL-STD-1835 a

11、nd as follows: Outline letter Descriptive designator Terminals Package style X See figure 1 44 Leaded chip carrier Y See figure 1 44 Quad flat pack Z See figure 1 44 Gullwing lead chip carrier 1.2.5 Lead finish. The lead finish is as specified in MIL-PRF-38535 for device classes Q and V or MIL-PRF-3

12、8535, appendix A for device class M. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-93195 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL C SHEET 3 DSCC FORM 2234 APR 97 1.3 Absolute

13、maximum ratings. 1/ Supply voltage (VA+ and VD+) 6.0 V Voltage at input and output pins except IN0-IN7 -0.3 V to V+ 0.3 V Voltage at analog inputs IN0-IN7 . GND - 5 V to V+ 5 V |VA+ - VD+| 300 mV Input current at any pin 2/ +5 mA Package input current 2/ +20 mA Storage temperature range (TSTG) . -65

14、C to +150C Maximum power dissipation (PD): Case X 1.75 W Cases Y and Z 2.5 W Lead temperature (soldering, 10 seconds). +300C Thermal resistance, junction-to-case (JC): Case X 3.5C/W Cases Y and Z 5.8C/W Junction temperature (TJ) +150C Thermal resistance, junction-to-ambient (JA): Case X 70C/W Cases

15、Y and Z 50C/W 1.4 Recommended operating conditions. Supply voltage (VA+ and VD+) 3.0 V to 5.5 V Supply voltage |VA+ - VD+| 100 mV VIN+ Input range GND VIN+ VA+ VIN- Input range. GND (VA+ or VD+), the current at that pin should be limited to 5 mA. The 20 mA maximum package input current rating allows

16、 the voltage at any four pins, with an input current of 5 mA, to simultaneously exceed the power supply voltages. 3/ VREFCM(Reference voltage common mode range) is defined as (VREF+ + VREF-)/2. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD

17、 MICROCIRCUIT DRAWING SIZE A 5962-93195 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL C SHEET 4 DSCC FORM 2234 APR 97 DEPARTMENT OF DEFENSE STANDARDS MIL-STD-883 - Test Method Standard Microcircuits. MIL-STD-1835 - Interface Standard Electronic Component Case Outlines. DEPA

18、RTMENT OF DEFENSE HANDBOOKS MIL-HDBK-103 - List of Standard Microcircuit Drawings. MIL-HDBK-780 - Standard Microcircuit Drawings. (Copies of these documents are available online at http:/assist.daps.dla.mil/quicksearch/ or from the Standardization Document Order Desk, 700 Robbins Avenue, Building 4D

19、, Philadelphia, PA 19111-5094.) 2.2 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a specific exemption h

20、as been obtained. 3. REQUIREMENTS 3.1 Item requirements. The individual item requirements for device classes Q and V shall be in accordance with MIL-PRF-38535 and as specified herein or as modified in the device manufacturers Quality Management (QM) plan. The modification in the QM plan shall not af

21、fect the form, fit, or function as described herein. The individual item requirements for device class M shall be in accordance with MIL-PRF-38535, appendix A for non-JAN class level B devices and as specified herein. 3.2 Design, construction, and physical dimensions. The design, construction, and p

22、hysical dimensions shall be as specified in MIL-PRF-38535 and herein for device classes Q and V or MIL-PRF-38535, appendix A and herein for device class M. 3.2.1 Case outlines. The case outlines shall be in accordance with 1.2.4 herein and figures 1, 2, and 3. 3.2.2 Terminal connections. The termina

23、l connections shall be as specified on figure 4. 3.2.3 Block diagram. The block diagram shall be as specified on figure 5. 3.3 Electrical performance characteristics and postirradiation parameter limits. Unless otherwise specified herein, the electrical performance characteristics and postirradiatio

24、n parameter limits are as specified in table I and shall apply over the full ambient operating temperature range. 3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table II. The electrical tests for each subgroup are defined in table I. 3.5 Markin

25、g. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturers PIN may also be marked. For packages where marking of the entire SMD PIN number is not feasible due to space limitations, the manufacturer has the option of not marking the “5962-“ on the device. For RHA pr

26、oduct using this option, the RHA designator shall still be marked. Marking for device classes Q and V shall be in accordance with MIL-PRF-38535. Marking for device class M shall be in accordance with MIL-PRF-38535, appendix A. 3.5.1 Certification/compliance mark. The certification mark for device cl

27、asses Q and V shall be a “QML“ or “Q“ as required in MIL-PRF-38535. The compliance mark for device class M shall be a “C“ as required in MIL-PRF-38535, appendix A. 3.6 Certificate of compliance. For device classes Q and V, a certificate of compliance shall be required from a QML-38535 listed manufac

28、turer in order to supply to the requirements of this drawing (see 6.6.1 herein). For device class M, a certificate of compliance shall be required from a manufacturer in order to be listed as an approved source of supply in MIL-HDBK-103 (see 6.6.2 herein). The certificate of compliance submitted to

29、DSCC-VA prior to listing as an approved source of supply for this drawing shall affirm that the manufacturers product meets, for device classes Q and V, the requirements of MIL-PRF-38535 and herein or for device class M, the requirements of MIL-PRF-38535, appendix A and herein. 3.7 Certificate of co

30、nformance. A certificate of conformance as required for device classes Q and V in MIL-PRF-38535 or for device class M in MIL-PRF-38535, appendix A shall be provided with each lot of microcircuits delivered to this drawing. Provided by IHSNot for ResaleNo reproduction or networking permitted without

31、license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-93195 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL C SHEET 5 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics. Test Symbol Conditions 1/ -55C TA +125C Group A subgroups Device type Limits U

32、nit unless otherwise specified Min Max Positive and negative integral linearity error EILAfter auto-cal 1, 2, 3 All 1 LSB Resolution with no missing codes RES After auto-cal 1, 2, 3 All 13 Bits Differential nonlinearity EDLAfter auto-cal 1, 3 All 1/2 LSB 2 3/4 Zero error EZAfter auto-cal 1, 2, 3 All

33、 1 LSB Positive full-scale error +EFSAfter auto-cal 1, 2, 3 All 2 LSB Negative full-scale error -EFSAfter auto-cal 1, 2, 3 All 2 LSB DC common mode error CME 2/ 1, 2, 3 All 3.5 LSB 8-Bit +sign and “watchdog“ mode positive and negative integral linearity error ILE1, 2, 3 All 1/2 LSB 8-Bit +sign and “

34、watchdog“ mode total unadjusted error ETUAfter auto-zero 1, 2, 3 All 3/4 LSB 8-Bit +sign and “watchdog“ mode resolution with no missing codes WRES 1, 2, 3 All 9 Bits 8-Bit +sign and “watchdog“ mode differential non-linearity DNL1, 2, 3 All 1/2 LSB 8-Bit +sign and “watchdog“ mode zero error WZEAfter

35、auto-zero 1, 2, 3 All 1/2 LSB 8-Bit +sign and “watchdog“ positive and negative full-scale error WFSE 1, 2, 3 All 1/2 LSB Differential input voltage range VDIF1, 2, 3 All Gnd VA+ V Common mode input voltage range VCMI1, 2, 3 All Gnd VA+ V Power supply sensitivity PSSZero error 3/ VA+ = VD+ = 5 V 10 %

36、 1, 2, 3 All 1.75 LSB Full-scale error VREF+ = 4.5 V, VREF- = Gnd 2.00 See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-93195 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-

37、3990 REVISION LEVEL C SHEET 6 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics - continued. Test Symbol Conditions 1/ -55C TA +125C Group A subgroups Device type Limits Unit unless otherwise specified Min Max VD+ supply current ID+ CS = “1“ 4/ 1, 2, 3 All 1.0 mA VA+ supply curre

38、nt IA+ CS = “1“ 4/ 1, 2, 3 All 5.0 mA Multiplexer ON-channel leakage current ILONVA+ = 5.5 V 4/ ON-channel = 5.5 V, OFF-channel = 0 V 1, 2, 3 All 0.3 A VA+ = 5.5 V 4/ ON-channel = 0 V, OFF-channel = 5.5 V Multiplexer OFF-channel leakage current ILOFFVA+ = 5.5 V 4/ ON-channel = 5.5 V, OFF-channel = 0

39、 V 1, 2, 3 All 0.3 A VA+ = 5.5 V 4/ ON-channel = 0 V, OFF-channel = 5.5 V Internal reference output voltage VREFOUTVA+ = VD+ = 5 V 5/ 1, 2, 3 All 2.4 2.6 V Internal reference load regulation REFL Sourcing (0 IL +4 mA) VA+ = VD+ = 5 V 1, 2, 3 All 0.2 %/mA Sinking (-1 IIL 0 mA) VA+ = VD+ = 5 V 1.2 Lin

40、e regulation VREF4.5 V VA+ 5.5 V VA+ = VD+ = 5 V 1, 2, 3 All 15 mV Internal reference short circuit current ISCVREFOUT= 0 V VA+ = VD+ = 5 V 1, 2, 3 All 25 mA Logical “1“ input voltage VIN(1) VA+ = VD+ = 5.5 V 6/ 1, 2, 3 All 2.0 V Logical “0“ input voltage VIN(0) VA+ = VD+ = 4.5 V 6/ 1, 2, 3 All 0.8

41、V Logical “1“ input current IIN(1) VIN= 5 V 6/ 1, 2, 3 All 1.0 A Logical “0“ input current IIN(0) VIN= 0 V 6/ 1, 2, 3 All -1.0 A Logical “1“ output voltage VOUT(1) VA+ = VD+ = 4.5 V, 6/ IOUT= -360 A 1, 2, 3 All 2.40 V VA+ = VD+ = 4.5 V, 6/ IOUT= -10 A 4.25 See footnotes at end of table. Provided by

42、IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-93195 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL C SHEET 7 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics - continued. T

43、est Symbol Conditions 1/ -55C TA +125C Group A subgroups Device type Limits Unit unless otherwise specified Min Max Logical “0“ output voltage VOUT(0) VA+ = VD+ = 4.5 V, 6/ IOUT= 1.6 mA 1, 2, 3 All 0.4 V TRI-STATE output leakage current IOUTVOUT= 0 V 6/ 1, 2, 3 All -3.0 A VOUT= 5 V 6/ 3.0 Clock duty

44、 cycle tCLK9, 10, 11 All 40 60 % Conversion time tC13-Bit resolution sequencer state S5 9, 10, 11 All 44 (tCLK) +50 ns 9-Bit resolution sequencer state S5 21 (tCLK) +50 Acquisition time tASequencer State S7 built-in minimum for 13-bits 9, 10, 11 All 9 (tCLK) +50 ns Built-in minimum for 9-bits and “w

45、atchdog“ mode 2 (tCLK) +50 Auto-zero time tZSequencer State S2 9, 10, 11 All 76 (tCLK) +50 ns Full calibration time tCALSequencer State S2 9, 10, 11 All 4944 (tCLK) +50 ns “Watchdog“ mode comparison time tWDSequencer States S6, S4 and S5 9, 10, 11 All 11 (tCLK) +50 ns CS or address valid to ALE low

46、set-up time t1,37/, See figure 6. 9, 10, 11 All 40 ns CS or address valid to ALE low hold time t2,47/, See figure 6. 9, 10, 11 All 20 ns ALE Pulse width t57/, See figure 6 9, 10, 11 All 45 ns RD high to next ALE high t67/, See figure 6 9, 10, 11 All 35 ns ALE low to RD low t77/, See figure 6 9, 10,

47、11 All 20 ns RD pulse width t87/, See figures 6 and 7 9, 10, 11 All 100 ns RD high to next RD or WR low t97/, See figures 6 and 7 9, 10, 11 All 100 ns See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUI

48、T DRAWING SIZE A 5962-93195 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL C SHEET 8 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics - continued. Test Symbol Conditions 1/ -55C TA +125C Group A subgroups Device type Limits Unit unless otherwise specified Min Max ALE low to WR low t107/, See figure 6 9, 10, 11 All 20 ns WR pulse width t117/, See figures 6 and 7 9, 10, 11 All 60 ns WR high to next ALE high t127/, See figu