DLA SMD-5962-93026-1995 MICROCIRCUIT DIGITAL FAST CMOS OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH CURRENT LIMITING RESISTORS AND THREE-STATE OUTPUTS TTL COMPATIBLE INPUTS AND LIMIT.pdf

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1、SMD-5762-93026 9997996 OOL304 116 LTR REVISIONS DATE (YR-MO-DA) APPROVED DESCRIPTION DRAWING APPROVAL DATE 95-1 1-28 REVISION LEVEL PREPARED BY Thanh V. Nguyen SIZE CAGE CODE 5962-93026 A 67268 CHECKED BY Thanh V. Nguyen STANDARD MICROCIRCUIT APPROVED BY DRAWING THIS DRAWING IS AVAILABLE FOR USE BY

2、ALL DEPARTMENTS AND AGENCIES OF THE DEPARTMENT OF DEFENSE AMSC N/A DEFENSE ELECTRONICS SUPPLY CENTER DAYTON, OHIO 45444 MICROCIRCUIT, DIGITAL, FAST CMOS, OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH CURRENT LIMITING RESISTORS AND THREE-STATE OUTPUTS, TTL COMPATIBLE INPUTS AND LIMITED OUTPUT VOLTAGE SW

3、ING, MONOLITHIC SILICON 1 OF 18 I I ESC FORM 193 JUL 94 DISTRIBUTION STATEMENT 4. Approved for public release; distribution is unlimited. 5962-El 94-96 Licensed by Information Handling ServicesSMD-59b2-93026 9999996 0081305 052 W STANDARD MICROCIRCUIT DRAWING DEFENSE ELECTRONICS SUPPLY CENTER DAYTON

4、, OHIO 45444 I 1. SCOPE 1.1 m. This drawing form a part of a one part - one part nunber documentation system (see 6.6 herein). Two product assurance classes consisting of military high reliability (device classes Q and M) and space application (device class V), and a choice of case outlines and lead

5、 finishes are available and are reflected in the Part or Identifying Nunber (PIN). Device class M microcircuits represent non-JAN class B microcircuits in accordance with 1.2.1 of MIL-STD-883, IProvisions for the use of MIL-STD-83 in conjunction with compliant non-JAN devices“. When available, a cho

6、ice of Radiation Hardness Assurance (RHA) levels are reflected in the PIN. I 1.2 pLN. The PIN shall be as shown in the following example: 9z-uLr i 11 Federal RHA Device Device Case Lead stock class designator type class outline finish designator (see 1.2.1) (see 1.2.2) designator (see 1.2.4) (see 1.

7、2.5) Il LA (see 1.2.3) / Drawing nunber 1.2.1 MA desianator . Device class M RHA marked devices shall meet the MIL-1-38535 appendix A specified RHA levels and shall be marked with the appropriate RHA designator. MIL-1-38535 specified RHA levels and shall be marked with the appropriate RHA designator

8、. A dash (-) indicates a non-RHA device. Device classes P and V RHA marked devices shall meet the 1.2.2 Device twetsl . The device type(s) shall identify the circuit function as follows: Device tvDe Generic nmkx ircuit function o1 54FCT2374T Octal edge-triggered D-type flip-flop with current limitin

9、g resistors and 02 54FCT2374AT Octal edge-triggered D-type flip-flop with current limiting resistors and 03 54FCT2374CT Octal edge-triggered D-type flip-flop with current Limiting resistors and three-state outputs, TTL compatible inputs and limited output voltage swing three-state outputs, TTL corrp

10、atible inputs and Limited output voltage swing three-state outputs, TTL conpatible inputs and limited output voltage swing 1.2.3 pevice class des ianato r. The device class designator shall be a single letter identifying the product assurance level as follows: Device class pevice reauirements docume

11、ntation I SIZE A 5962-93026 REVISION LEVEL SHEET 2 M Vendor self-certification to the requirements for non-JAN class B microcircuits in accordance with 1.2.1 of MIL-STD-883 Q or V Certification and qualification to MIL-1-38535 1.2.4 Case outlinew . The case outline(s) shall be as designated in MIL-S

12、TD-1835, and as follows: Putline letter pescriDtive des ianator Temi na 1 b ;r/ type subgroups Unit Functional test 3014 VIH.= 2.0 V, VIL = 0.8 V Verify output Vo See 4.4.1 . = 50 pF minimm = 5oon See figure 5 ns Propagation delay time, CP to On 3003 I I 02 I 19, 10, 11 I 2.0 I 7.2 9, 10, 11 Propaga

13、tion delay time, ou*t enable, OE to on 3003 9, 10, 11 I I &; 9, 10, 11 ns 9, 10, 11 ns Setup time, high or low, Dn to CP Hold time, high or low, Dn from CP ns CP pulse width, high ns 1/ For tests not listed in the referenced MIL-STD-883 (e.9. AIcc), utilize the general test procedure of 883 under th

14、e conditions listed herein. Each input/output, as applicable, shall be tested at the specified temperature, for the specified limits, to the tests in table I herein. Output terminals not designated shall be high level logic, low level logic, or open, except for all I and A tests, the output terminal

15、s shall be open. Uhen performing these tests, the current meter shall be pfaced in ti% circuit such that all current flows through the meter. 3 For negative and positive voltage and current values, the sign designates the potential difference in reference to GND and the direction of current flow, re

16、spectively; and the absolute value of the magnitude, not the sign, is relative to the minimm and maxim limits, as applicable, listed herein. limits specified in table I at 4.5 V 5 Vcc i 5.5 V. 4/ This parameter is guaranteed, if not tested, to the limits specified in table I herein. 3 Three-state ou

17、tput conditions are required. 6/ This test may be performed using VIH = 3.0 V. Not more than one output should be tested at a time. All devices shall meet or exceed the Uhen VIH = 3.0 V is used, the test is guaranteed for VIH = 2.0 V. The duration of the test should not exceed one second. DESC FORM

18、193A JUL 94 Licensed by Information Handling ServicesSMD-5b2-9302b m 7999996 OOl13L2 292 m SIZE A STAN DARD MICROCIRCUIT DRAWING DEFENSE ELECTRONICS SUPPLY CENTER DAYTON, OHIO 45444 REVISION LEVEL TABLE I. Flectrical oerforma nce cha racteristics - Continued. 5962-93026 SHEET 9 y ICCD may be verifie

19、d by thefollowing equation: ICCT Icc DHNTAICC fCp/2 + fiNi CCD = where ICCT, Icc (Icc or ICCH in table I), and AI device under test, when tested as described in tab?: I, herein. The values for DH, NT, fCp, fi, and Ni shall be as listed in the test conditions column for ICCT This test may be performe

20、d either one input at a time (preferred method) or with all input pins simultaneously at VI, = V - 2.1 V (alternate method). using tke alternate test method, the maxim limit is equal to the number of inputs at a high TTL input level times 2.0 mA; and the preferred method and limits are guaranteed. s

21、hall be the measured values of these parameters, for the in table i, herein. y Classes Q and V shall use the preferred method. When the test is performed o/ CCT is calculated as follows: where I DF=-Duty cycle for TTL inputs at 3.4 V NT = Number of TTL inputs at 3.4 V f=-Clock frequency for register

22、ed devices (fCp O for nonregistered devices) fi - Input frequency Ni = Number of inputs at fi - Quiescent supply current (any IccL or ICCH) Quiescent supply current delta, TTL inputs at 3.4 V Dynamic power supply current caused by an input transition pair (HLH or LHL) fcc -= 11/ This test is require

23、d only for group A testing; see 4.4.1 herein. a/ This test is for qualification only. Ground and V bounce tests are performed on a non-switching (quiescent) output and are used to measure the magnitude of in%ced noise caused by other simultaneously switching outputs. The test is performed on a low n

24、oise bench test fixture. with 500n of load resistance and a minim of 50 pF of load capacitance (see figure 4). resistors shall be used. It is suggested, that whenever possible, this distance be kept to less than 0.25 inches. shall be placed in parallel from Vcc to ground. the device manufacturer. Th

25、e low and high level ground and V a 1 GHr minimum bandwidth oscilloscope with a 50Q input inpeik7ce. The device inputs shall be conditioned such that all outputs are at a high nominal VOH level. The device inputs shall then be conditioned such that they switch simultaneously and the output under tes

26、t remains at V other outputs possible are switched from VoH to VOL. VOHV and VOHP are then measured from the nominaPHVOH level to the largest negative and positive peaks, respectively (see figure 4). outputs not under test switching from VOL to VOH. The device inputs shall be conditioned such that a

27、ll outputs are at a low nominal VOL level. shall then be conditioned such that they switch simultaneously and the output under test remains at V other outputs possible are switched from VOL to VOH: VoLp and VOLV are then measured from the nominaPLVoL level to the largest positive and negative peaks,

28、 respectively (see figure 4). outputs not under test switching from VOH to VOL. The V shall% added by revision no more than 90 days from the date of this drawing. For the device under test, all outputs shall be loaded Only chip capacitors and The output load components shall be located as close as p

29、ossible to the device outputs. Decoupling capacitors The values of these decoupling capacitors shall be determined by bounce noise is measured at the quiet output using as all This is then repeated with the same The device inputs as all This is then repeated with the same and ground bounce tests wer

30、e not completed at the date of this drawing. The limits for these parameters 13/ Tests shall be performed in sequence, attributes data only. other logic patterns used for fault detection. minimum, test all functions of each input and output. shall be guaranteed, if not tested, to the truth table in

31、figure 2 herein. sequence as approved by the qualifying activity on qualified devices. propagation defgy time limits for Vc = 4.5 V and 5.5 V are guaranteed, if not tested, to the fimits specified in table I, herein. Functional tests shall include the truth table and All possible input to output log

32、ic patterns per function For outputs, L 1.5 V, H r 1.5 V. The test vectors used to verify the truth table shall, at a Functional tests shall be performed in 14.5 V. Minimum 14/ AC limits at V = 5.5 V are equal to the limits at Vcc = 4.5 V and guaranteed by testing at V For propagation defay tests, a

33、ll paths must be tested. DESC FORM 193A JUL 94 Licensed by Information Handling ServicesSUD-5962-93026 m 9999996 OOBL3L3 L29 m I Device types I 01, 02, 03 I I Case wtiines I R, S, and 2 I Terminal Termina 1 Terminal Terminal nunber symbol nunber symbol 1 OE 11 CP 2 O0 I2 04 3 DO 13 D4 4 DI 14 05 5 o

34、1 15 05 6 02 16 o6 7 D2 17 D6 a D3 18 D7 9 03 19 07 - 10 GND 20 “cc I Terminal descriptions I Terminal symbol I Description I Dn (n = O to 7) On (n = O to 7) Data inputs Three-state outputs - . OE Output enable control input (active low) CP Clock input FIGURE 1. Terminal connectiom. SIZE A STANDARD

35、MICROCIRCUIT DRAWING DEFENSEELECTRONICSSUPPLYCENTER DAYTON, OHIO 45444 REVISION LEVEL 5962-93026 SHEET 10 DESC FORM 19% JUL 94 Licensed by Information Handling ServicesSMD-5962-9302b 9999996 ODBL3ItLl Ob5 I nputc - OE CP Dn H L X H H X L t L L T H H T L H T H I Device types 01, 02, 03 I Outputs Func

36、tion On 2 High impedance 2 L Load register H z 2 H = High voltage level L = LOW voltage level 1 Low-to-high transition X = Irrelevant Z = High impedance FIGURE 2. Truth table. O0 o1 D2 03 04 05 06 07 CP - - - x I. A I- Al XI AI A I- x I - X I - CD CD CD C D CD CO CD CD O - - - - - - O o O O O O O -

37、OE O0 o1 O2 03 O4 o5 06 07 FIGURE 3. Loaic diasram. 5962-93026 REVISION LEVEL STANDARD MICROCIRCUIT DRAWING DEFENSEELECTRONICSSUPPLYCENTER DAYTON, OHIO 45444 DESC FORM 193A JUL 94 Licensed by Information Handling ServicesSMD-5762-93026 7977796 00813L5 TTL STAN DARD MICROCIRCUIT DRAWING DEFENSE ELECT

38、RONICS SUPPLY CENTER DAYTON, OHIO 45444 SVITCHING INPUT c_ SIZE A 5962-93026 REVISION LEVEL SHEET 12 IN-PHASE INPUTS 3.0V INPUT SKEV 1.w 3.0V - 1% 0.ov DUT-OF-PHASE INPUTS 3.W 1.w OOV RL OUTPUT 1 RL DUT Cn DUTWTS) - OUTPUT 2 IOTES: 1. C includes a 47 pF chip capacitor (-O percent, +20 percent) and a

39、t le t 3 pF of equivalent capacitance frm the test jig and probe. 2. RL =-4500 11 percent, chip resistor in series with a 50n termination. For monitored outputs, the 500 termination shall be the 500 characteristic impedance of the coaxial connector to the oscilloscope. 3. Input signal to the device

40、under test: a. VIN = 0.0 V to 3.0 V; duty cycle = 50 percent; fIN r 1 MHz. b. tr, tf =-3-ns 11.0 ns. For input signal generators incapable of maintaining these values of tr and tf, the 3.0 ns limit may be increased up to 10 ns, as needed, maintaining the 21.0 ns tolerance and guaranteeing the result

41、s at 3.0 ns 11.0 ns; skew between any two switching inputs signals (tsk): i 250 ps. FIGURE 4. Dound bounce load circuit and uaveform. Licensed by Information Handling ServicesSMD-5962-93026 9999996 OOl13Lb 938 SIZE A STANDARD MICROCIRCUIT DRAWING DEFENSE ELECTRONICS SUPPLY CENTER DAYTON, OHIO 45444

42、REVISION LEVEL 3.0 v CLOCK 1.5 v 0.0 v INPUT OUTPUT JtPH;.j “OH 1.5 v “OL 5962-93026 SHEET 13 3*0 1.5 V 2.7 V 0.3 V t 0.0 v - - - tPZL - PLZ - OUTPUT ENABLE CONTROL INPUT OUTPUT + 0.3 V VOH VOH - 0.3 V OUTPUT 1.5 v s GND FIGURE 5. Switchins waveforms and test c i rcui t. DESC FORM 193A JUL 94 Licens

43、ed by Information Handling ServicesSMD-5762-93026 = 9999996 0081317 874 d tw STAN DARD MICROCIRCUIT DRAWING DEFENSEELECTRONICSSUPPLYCENTER DAYTON, OHIO 45444 NOTES: 1. Uhen measuring tpLZ and tpZL: VTEST = 7.0 V. 2. Uhen measuring tpHZ, tpZH, tpLH, and tpH : VIEST = open. 3. The tp is at GOL except

44、when disabled by the output enable control. The tpZH and tpHZ reference waveform is for the output under test with internal conditions such that the output is at VoH except when disabled by the output enable control. CL = 50 pF minimm or equivalent (includes test jig and probe capacitance). RL = 500

45、Q or equivalent. RT = 50Q or equivalent. Input signal from pulse generator: VIN = 0.0 V to 3.0 V; PRR s 10 MHz; t s 2.5 ns; tf s 2.5 ns; tr and tf shall be measured from 0.3 V to 2.7 V and from 2.7 V to 0.3 V, respectivery; duty cycle = 50 percent. Timing parameters shall be tested at a minim input

46、frequency of 1 MHz. The outputs are measured one at a time with one transition per measurement. and tpLZ reference waveform is or the output under test with internal conditions such that the output 4. 5. 6. 7. 8. 9. SIZE A 5962-93026 REVISION LEVEL SHEET 14 FIGURE 5. Suitchina waveforms and test cir

47、cuit - Continued. DESC FORM 193A JUL 94 Licensed by Information Handling ServicesSMD-59b2-9302b 9999976 008L318 700 Subgroups MI L-STD -883 , TM 5005, table I) Devi ce class M Test requirements (in accordance with - interim electrical Final electrical 1, 2, 3, 4, 5, 6, parameters (see 4.2) parameter

48、s (see 4.2) 7, 8, 9, IO, 11 I/ 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11 1, 2, 3, 4, 5, 6 1, 2, 3 1, 4, 7, 9 Group A test requirements (see 4.4) parameters (see 4.4) parameters (see 4.4) parameters (see 4.4) Group C end-point electrical Group D end-point electrical Group E end-point electrical Subgroups ( i

49、n accordance wi th MIL-1-38535, table III) Device Device class Q class V 1 1 1, 2, 3, 4, 5, 6, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11 7, 8, 9, 10, 11 1/ u 7, 8, 9, IO, 11 7, 8, 9, 10, 11 1, 2, 3, 4, 5, 6 1, 2, 3, 4, 5, 6 7, 8, 9, 10, 11 1, 2, 3 1, 2, 3 1, 4, 7, 9 1, 4, 7, 9 1, 2, 3s 4, 5, 6, 1, 2, 3, 4, 5, 6, 1/ PDA applies to subgroups 1 and 4 (i.e., ICCT only). u PDA applies to subgroups 1, 4, and 7. SIZE A STAN DARD MICROCIRCUIT DRAWING DEFENSE ELECTRONICS SUPPLY CENTER DAYTON, OHIO 45444 REVISION LEVEL 4.2.2 Additional c riteria for device c