DLA SMD-5962-92062 REV B-2007 MICROCIRCUIT MEMORY DIGITAL CMOS UV ERASABLE PROGRAMMABLE LOGIC DEVICE MONOLITHIC SILICON《硅单块 紫外擦拭可编程逻辑设备 互补金属氧化物半导体 数字主储存器微型电路》.pdf

《DLA SMD-5962-92062 REV B-2007 MICROCIRCUIT MEMORY DIGITAL CMOS UV ERASABLE PROGRAMMABLE LOGIC DEVICE MONOLITHIC SILICON《硅单块 紫外擦拭可编程逻辑设备 互补金属氧化物半导体 数字主储存器微型电路》.pdf》由会员分享，可在线阅读，更多相关《DLA SMD-5962-92062 REV B-2007 MICROCIRCUIT MEMORY DIGITAL CMOS UV ERASABLE PROGRAMMABLE LOGIC DEVICE MONOLITHIC SILICON《硅单块 紫外擦拭可编程逻辑设备 互补金属氧化物半导体 数字主储存器微型电路》.pdf（21页珍藏版）》请在麦多课文档分享上搜索。

1、 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Added device type 03. Updated format, editorial changes throughout. 94-08-10 M. A. Frye B Boilerplate update, part of 5 year review. ksr 07-05-25 Robert M. Heber FIRST PAGE HAS BEEN REPLACED REV SHET REV B B B B B B SHEET 15 16 17 18 19 20 REV ST

2、ATUS REV B B B B B B B B B B B B B B OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PMIC N/A PREPARED BY Kenneth Rice DEFENSE SUPPLY CENTER COLUMBUS STANDARD MICROCIRCUIT DRAWING CHECKED BY Rajesh Pithadia COLUMBUS, OHIO 43218-3990 http:/www.dscc.dla.mil THIS DRAWING IS AVAILABLE FOR USE BY ALL AP

3、PROVED BY Michael Frye DEPARTMENTS AND AGENCIES OF THE DEPARTMENT OF DEFENSE DRAWING APPROVAL DATE 93-08-05 MICROCIRCUIT, MEMORY, DIGITAL, CMOS, UV ERASABLE PROGRAMMABLE LOGIC DEVICE, MONOLITHIC SILICON AMSC N/A REVISION LEVEL B SIZE A CAGE CODE 67268 5962-92062 SHEET 1 OF 20 DSCC FORM 2233 APR 97 5

4、962-E316-07 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-92062 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 2 DSCC FORM 2234 APR 97 1. SCOPE 1.1 Scope. This drawing docum

5、ents two product assurance class levels consisting of high reliability (device classes Q and M) and space application (device class V). A choice of case outlines and lead finishes are available and are reflected in the Part or Identifying Number (PIN). When available, a choice of Radiation Hardness

6、Assurance (RHA) levels are reflected in the PIN. 1.2 PIN. The PIN is as shown in the following example: 5962 - 92062 01 Q Y C Federal RHA Device Device Case Lead stock class designator type class outline finish designator (see 1.2.1) (see 1.2.2) designator (see 1.2.4) (see 1.2.5) / (see 1.2.3) / Dra

7、wing number 1.2.1 RHA designator. Device classes Q and V RHA marked devices meet the MIL-PRF-38535 specified RHA levels and are marked with the appropriate RHA designator. Device class M RHA marked devices meet the MIL-PRF-38535, appendix A specified RHA levels and are marked with the appropriate RH

8、A designator. A dash (-) indicates a non-RHA device. 1.2.2 Device type(s). The device type(s) identify the circuit function as follows: Device type Generic number 1/ Circuit function Propagation delay time 01 192 Macrocell EPLD 40 ns 02 192 Macrocell EPLD 30 ns 03 192 Macrocell EPLD 35 ns 1.2.3 Devi

9、ce class designator. The device class designator is a single letter identifying the product assurance level as follows: Device class Device requirements documentation M Vendor self-certification to the requirements for MIL-STD-883 compliant, non-JAN class level B microcircuits in accordance with MIL

10、-PRF-38535, appendix A Q or V Certification and qualification to MIL-PRF-38535 1.2.4 Case outline(s). The case outline(s) are as designated in MIL-STD-1835 and as follows: Outline letter Descriptive designator Terminals Package style X GQCC1-J84E 84 “J“ lead chip carrier 2/ Y CMGA15-P84E 84 Pin grid

11、 array 2/ Z CMGA3-P84E 84 Pin grid array 2/ 1.2.5 Lead finish. The lead finish is as specified in MIL-PRF-38535 for device classes Q and V or MIL-PRF-38535, appendix A for device class M. 1/ Generic numbers are listed on the Standard Microcircuit Drawing Source Approval Bulletin at the end of this d

12、ocument and will also be listed in QML-38535 and MIL-HDBK-103 (see 6.6 herein). 2/ Lid shall be transparent to permit ultraviolet light erasure. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-92062 DEFENSE S

13、UPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 3 DSCC FORM 2234 APR 97 1.3 Absolute maximum ratings. 3/ Supply voltage range (VCC) - -2.0 V dc to +7.0 V dc DC input voltage range - -2.0 V dc to +7.0 V dc 4/ Maximum power dissipation - 2.5 W 5/ Lead temperature (soldering, 10

14、seconds) - +260C Thermal resistance, junction-to-case (JC): Case outlines X, Y, and Z - See MIL-STD-1835 Junction temperature (TJ) - +175C Storage temperature range - -65C to +150C Temperature under bias range - -55C to +125C Endurance - 25 erase/write cycles (minimum) Data retention - 10 years (min

15、imum) 1.4 Recommended operating conditions. Supply voltage range (VCC) - +4.5 V dc to +5.5 V dc Ground voltage (GND) - 0 V dc Input high voltage (VIH) - 2.2 V dc minimum Input low voltage (VIL) - 0.8 V dc maximum Case operating temperature range (TC) - -55C to +125C 6/ Input rise time (tR) - 100 ns

16、maximum Input fall time (tF) - 100 ns maximum 2. APPLICABLE DOCUMENTS 2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a part of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents ar

17、e those cited in the solicitation or contract. DEPARTMENT OF DEFENSE SPECIFICATION MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for. DEPARTMENT OF DEFENSE STANDARDS MIL-STD-883 - Test Method Standard Microcircuits. MIL-STD-1835 - Interface Standard Electronic Component C

18、ase Outlines. DEPARTMENT OF DEFENSE HANDBOOKS MIL-HDBK-103 - List of Standard Microcircuit Drawings. MIL-HDBK-780 - Standard Microcircuit Drawings. (Copies of these documents are available online at http:/assist.daps.dla.mil/quicksearch/ or http:/assist.daps.dla.mil from the Standardization Document

19、 Order Desk, 700 Robins Avenue, Building 4D, Philadelphia, PA 19111-5094.) 3/ Stresses above the absolute maximum rating may cause permanent damage to the device. Extended operation at the maximum levels may degrade performance and affect reliability. 4/ Minimum dc input voltage is -0.3 V. During tr

20、ansitions, inputs may undershoot to -2.0 V for periods less than 20 ns. Maximum dc voltage on output pins is VCC+ 0.3 V, which may overshoot to +7.0 V for periods less than 20 ns under no load conditions. 5/ Must withstand the added PDdue to short circuit test (e.g., ISC). 6/ Case temperatures are i

21、nstant on. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-92062 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL B SHEET 4 DSCC FORM 2234 APR 97 2.2 Non-Government publications. The fo

22、llowing document(s) form a part of this document to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the solicitation. AMERICAN SOCIETY FOR TESTING AND MATERIALS (ASTM) ASTM Standard F1192-00 - Standard Guide for the Measurement of Single Even

23、t Phenomena from Heavy Ion Irradiation of Semiconductor Devices. (Applications for copies of ASTM publications should be addressed to: ASTM International, PO Box C700, 100 Barr Harbor Drive, West Conshohocken, PA 19428-2959; http:/www.astm.org.) ELECTRONICS INDUSTRIES ASSOCIATION (EIA) JEDEC Standar

24、d EIA/JESD78 - IC Latch-Up Test. (Applications for copies should be addressed to the Electronics Industries Association, 2500 Wilson Boulevard, Arlington, VA 22201; http:/www.jedec.org.) (Non-Government standards and other publications are normally available from the organizations that prepare or di

25、stribute the documents. These documents also may be available in or through libraries or other informational services.) 2.3 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text of this drawing takes precedence. Nothing in this doc

26、ument, however, supersedes applicable laws and regulations unless a specific exemption has been obtained. 3. REQUIREMENTS 3.1 Item requirements. The individual item requirements for device classes Q and V shall be in accordance with MIL-PRF-38535 and as specified herein or as modified in the device

27、manufacturers Quality Management (QM) plan. The modification in the QM plan shall not affect the form, fit, or function as described herein. The individual item requirements for device class M shall be in accordance with MIL-PRF-38535, appendix A for non-JAN class level B devices and as specified he

28、rein. 3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified in MIL-PRF-38535 and herein for device classes Q and V or MIL-PRF-38535, appendix A and herein for device class M. 3.2.1 Case outline(s). The case outline(s) shall be in a

29、ccordance with 1.2.4 herein. 3.2.2 Terminal connections. The terminal connections shall be as specified on figure 1. 3.2.3 Truth table(s). The truth table shall be as specified on figure 2. 3.2.4.1 Unprogrammed devices. The truth table for unprogrammed devices for contracts involving no altered item

30、 drawing shall be as specified on figure 2. When required in screening (see 4.2 herein), or qualification conformance inspection groups A, B, C, or D (see 4.4 herein), the devices shall be programmed by the manufacturer prior to test. A minimum of 50 percent of the total number of gates shall be pro

31、grammed or at least 25 percent of the total number of gates to any altered item drawing. 3.2.4.2 Programmed devices. The truth table for programmed devices shall be as specified by an attached altered item drawing. 3.3 Electrical performance characteristics and postirradiation parameter limits. Unle

32、ss otherwise specified herein, the electrical performance characteristics and postirradiation parameter limits are as specified in table I and shall apply over the full case operating temperature range. 3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specifi

33、ed in table IIA. The electrical tests for each subgroup are defined in table I. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-92062 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL B

34、SHEET 5 DSCC FORM 2234 APR 97 3.5 Marking. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturers PIN may also be marked. For packages where marking of the entire SMD PIN number is not feasible due to space limitations, the manufacturer has the option of not marki

35、ng the “5962-“ on the device. For RHA product using this option, the RHA designator shall still be marked. Marking for device classes Q and V shall be in accordance with MIL-PRF-38535. Marking for device class M shall be in accordance with MIL-PRF-38535, appendix A. 3.5.1 Certification/compliance ma

36、rk. The certification mark for device classes Q and V shall be a “QML“ or “Q“ as required in MIL-PRF-38535. The compliance mark for device class M shall be a “C“ as required in MIL-PRF-38535, appendix A. 3.6 Certificate of compliance. For device classes Q and V, a certificate of compliance shall be

37、required from a QML-38535 listed manufacturer in order to supply to the requirements of this drawing (see 6.6.1 herein). For device class M, a certificate of compliance shall be required from a manufacturer in order to be listed as an approved source of supply in MIL-HDBK-103 (see 6.6.2 herein). The

38、 certificate of compliance submitted to DSCC-VA prior to listing as an approved source of supply for this drawing shall affirm that the manufacturers product meets, for device classes Q and V, the requirements of MIL-PRF-38535 and herein or for device class M, the requirements of MIL-PRF-38535, appe

39、ndix A and herein. 3.7 Certificate of conformance. A certificate of conformance as required for device classes Q and V in MIL-PRF-38535 or for device class M in MIL-PRF-38535, appendix A shall be provided with each lot of microcircuits delivered to this drawing. 3.8 Notification of change for device

40、 class M. For device class M, notification to DSCC-VA of change of product (see 6.2 herein) involving devices acquired to this drawing is required for any change that affects this drawing. 3.9 Verification and review for device class M. For device class M, DSCC, DSCCs agent, and the acquiring activi

41、ty retain the option to review the manufacturers facility and applicable required documentation. Offshore documentation shall be made available onshore at the option of the reviewer. 3.10 Microcircuit group assignment for device class M. Device class M devices covered by this drawing shall be in mic

42、rocircuit group number 42 (see MIL-PRF-38535, appendix A). 3.11 Processing EPLDs. All testing requirements and quality assurance provisions herein shall be satisfied by the manufacturer prior to delivery. 3.12.1 Erasure of EPLDs. When specified, devices shall be erased in accordance with the procedu

43、res and characteristics specified in 4.6. 3.12.2 Programmability of EPLDs. When specified, devices shall be programmed to the specified pattern using the procedures and characteristics specified in 4.5. 3.12.3 Verification of erasure or programmed EPLDs. When specified, devices shall be verified as

44、either programmed (see 4.5) to the specified pattern or erased (see 4.6). As a minimum, verification shall consist of performing a functional test (subgroup 7) to verify that all bits are in the proper state. Any bit that does not verify to be in the proper state shall constitute a device failure, a

45、nd shall be removed from the lot. 3.13 Endurance. A reprogrammability test shall be completed as part of the vendors reliability monitor. This reprogrammability test shall be done only for initial characterization and after any design or process changes which may affect the reprogrammability of the

46、device. The methods and procedures may be vendor specific, but will guarantee the number of program/erase endurance cycles listed in section 1.3 herein. The vendors procedure shall be under document control and shall be made available upon request. 3.14 Data retention. A data retention stress test shall be completed as part of the vendors reliability process. This test shall be done in