DLA SMD-5962-91501 REV D-2005 MICROCIRCUIT DIGITAL CMOS 32-BIT INTEGRATED MICROCONTROLLER MONOLITHIC SILICON《硅单块 32比特综合微型控制器 互补金属氧化物半导体 数字微型电路》.pdf

《DLA SMD-5962-91501 REV D-2005 MICROCIRCUIT DIGITAL CMOS 32-BIT INTEGRATED MICROCONTROLLER MONOLITHIC SILICON《硅单块 32比特综合微型控制器 互补金属氧化物半导体 数字微型电路》.pdf》由会员分享，可在线阅读，更多相关《DLA SMD-5962-91501 REV D-2005 MICROCIRCUIT DIGITAL CMOS 32-BIT INTEGRATED MICROCONTROLLER MONOLITHIC SILICON《硅单块 32比特综合微型控制器 互补金属氧化物半导体 数字微型电路》.pdf（39页珍藏版）》请在麦多课文档分享上搜索。

1、 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Changes in accordance with NOR 5962-R006-98 98-01-22 Monica L. Poelking B Changes in accordance with NOR 5962-R111-98 98-05-22 Monica L. Poelking C Add device 02. Editorial changes throughout. 98-07-01 Monica L. Poelking D Update boilerplate to M

2、IL-PRF-38535 requirements. - CFS 05-10-04 Thomas M. Hess REV D D D D SHEET 35 36 37 38 REV D D D D D D D D D D D D D D D D D D D D SHEET 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 REV STATUS REV D D D D D D D D D D D D D D OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PMIC N/A PR

3、EPARED BY Thomas M. Hess DEFENSE SUPPLY CENTER COLUMBUS STANDARD MICROCIRCUIT DRAWING CHECKED BY Thomas M. Hess COLUMBUS, OHIO 43218-3990 http:/www.dscc.dla.mil THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS APPROVED BY Monica L. Poelking MICROCIRCUIT, DIGITAL, CMOS, 32-BIT INTEGRATED MICROCON

4、TROLLER, AND AGENCIES OF THE DEPARTMENT OF DEFENSE DRAWING APPROVAL DATE 94-10-17 MONOLITHIC SILICON AMSC N/A REVISION LEVEL D SIZE A CAGE CODE 67268 5962-91501 SHEET 1 OF 38 DSCC FORM 2233 APR 97 5962-E433-05 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from

5、IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-91501 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL D SHEET 2 DSCC FORM 2234 APR 97 1. SCOPE 1.1 Scope. This drawing documents two product assurance class levels consisting of high reliability (device classes Q and M) and sp

6、ace application (device class V). A choice of case outlines and lead finishes are available and are reflected in the Part or Identifying Number (PIN). When available, a choice of Radiation Hardness Assurance (RHA) levels is reflected in the PIN. 1.2 PIN. The PIN is as shown in the following example:

7、 5962 - 91501 01 Q Z X Federal stock class designator RHA designator (see 1.2.1) Device type (see 1.2.2)Device class designatorCase outline (see 1.2.4) Lead finish (see 1.2.5) / (see 1.2.3) / Drawing number 1.2.1 RHA designator. Device classes Q and V RHA marked devices meet the MIL-PRF-38535 specif

8、ied RHA levels and are marked with the appropriate RHA designator. Device class M RHA marked devices meet the MIL-PRF-38535, appendix A specified RHA levels and are marked with the appropriate RHA designator. A dash (-) indicates a non-RHA device. 1.2.2 Device type(s). The device type(s) identify th

9、e circuit function as follows: Device type Generic number Circuit function 01 68332 1/ 32-bit integrated microcontroller 02 68332-20 1/ 32-bit integrated microcontroller 1.2.3 Device class designator. The device class designator is a single letter identifying the product assurance level as follows:

10、Device class Device requirements documentation M Vendor self-certification to the requirements for MIL-STD-883 compliant, non-JAN class level B microcircuits in accordance with MIL-PRF-38535, appendix A Q or V Certification and qualification to MIL-PRF-38535 1.2.4 Case outline(s). The case outline(s

11、) are as designated in MIL-STD-1835 and as follows: Outline letter Descriptive designator Terminals Package style Z CMGA5-P132 132 Pin grid array X See figure 1 132 Gull wing leaded chip carrier Y See figure 1 132 Gull wing leaded chip carrier 1.2.5 Lead finish. The lead finish is as specified in MI

12、L-PRF-38535 for device classes Q and V or MIL-PRF-38535, appendix A for device class M. _ 1/ This part does not include the Quadrature Decoder (QDEC) function. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-

13、91501 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL D SHEET 3 DSCC FORM 2234 APR 97 1.3 Absolute maximum ratings. 1/ Storage temperature range (TSTG) -55C to +150C Supply voltage range -0.3 V dc to +6.5 V dc 1/ 2/ 3/ Input voltage range (VIN) -0.3 V dc to +6.5 V dc 1/ 2/ 3/

14、 4/ Instantaneous maximum current single pin limit (applies to all pins) 25 mA 1/ 2/ 3/ 5/ Power dissipation (PD) 690 mW Operating maximum current digital input disruptive current range VSS 0.3 VIN VDD+ 0.3 . -500 A to +500 A 5/ 6/ 7/ Thermal resistance, junction-to-case (JC): Case Z 10C/W Case X an

15、d Y . 10C/W Lead temperature range (soldering, 5 seconds). 270C 1.4 Recommended operating conditions. Case operating temperature range -55C to +125C Supply voltage range 4.50 V dc VDD 5.50 V dc PLL reference frequency range (fREF). 25 kHz to 50 kHz System frequency: 8/ Device 01 16.78 MHz Device 02

16、20.97 MHz On-chip PLL system frequency (fSYS): Device 01 0.131 fSYS 16.78 MHz Device 02 0.131 fSYS 20.97 MHz External clock operation: Device 01 16.78 MHz Device 02 20.97 MHz PLL lock time (tLPLL) 20 ms 9/ Limp mode clock frequency (fLIMP): 10/ SYNCR X bit = 0. fSYSmax/2 MHz SYNCR X bit = 1. fSYSmax

17、 MHz CLKOUT stability (CSTAB): 11/ 12/ Short term. -1.0% to +1.0% Long term . -0.5% to +0.5% _ 1/ Permanent damage can occur if maximum ratings are exceeded. Exposure to voltages or currents in excess of recommended values affects device reliability. Device modules may not operate normally while bei

18、ng exposed to electrical extremes. 2/ Although sections of the device contain circuitry to protect against damage from high static voltages or electrical fields, take normal precautions to avoid exposure to voltages higher than maximum-rated voltages. 3/ This parameter is periodically sampled rather

19、 than 100% tested. 4/ All pins except TSTME/TSC. 5/ All functional non-supply pins are internally clamped to VSS. All functional pins except EXTAL, TSTME/TSC, and XFC are internally clamped to VDD. 6/ Power supply must maintain regulation within operating VDDrange during instantaneous and operating

20、maximum current conditions. 7/ Total input current for all digital input-only and all digital input/output pins must not exceed 10 mA. Exceeding this limit can cause disruption of normal operation. 8/ All internal registers retain data at 0 Hz. 9/ Assumes that stable VDDSYNis applied, that an extern

21、al filter capacitor with a value of 0.1 FF is attached to the XFC pin. and that the crystal oscillator is stable. Lock time is measured from power-up to reset release. This specification also applies to the period required for PLL lock after changing the W and Y frequency control bits in the synthes

22、izer control register (SYNCR) while the PLL is running, and to the period required for the clock to lock after LPSTOP. 10/ Determine by the internal reference voltage applied to the on-chip VCO. The X-bit in SYNCR controls a divide by two prescaler on the system clock output. 11/ Short-term CLKOUT s

23、tability is the average deviation from programmed frequency measured over a 2 Fs interval at maximum fSYS. Long-term CLKOUT stability is the average deviation from programmed frequency measured over a 1 ms interval at maximum fSYS. Stability is measured with a stable external clock input applied var

24、iation in crystal oscillator frequency is additive to this figure. 12/ This parameter is periodically sampled rather than 100% tested. 13/ Values will be added when they become available. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICRO

25、CIRCUIT DRAWING SIZE A 5962-91501 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL D SHEET 4 DSCC FORM 2234 APR 97 2. APPLICABLE DOCUMENTS 2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a part of this drawing

26、to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the solicitation or contract. DEPARTMENT OF DEFENSE SPECIFICATION MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for. DEPARTMENT OF DEFENSE STANDARDS MIL-STD-883 -

27、Test Method Standard Microcircuits. MIL-STD-1835 - Interface Standard Electronic Component Case Outlines. DEPARTMENT OF DEFENSE HANDBOOKS MIL-HDBK-103 - List of Standard Microcircuit Drawings. MIL-HDBK-780 - Standard Microcircuit Drawings. (Copies of these documents are available online at http:/ass

28、ist.daps.dla.mil/quicksearch/ or http:/assist.daps.dla.mil or from the Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.) 2.2 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text of

29、 this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a specific exemption has been obtained. 3. REQUIREMENTS 3.1 Item requirements. The individual item requirements for device classes Q and V shall be in accordance with MIL-PRF-38535 an

30、d as specified herein or as modified in the device manufacturers Quality Management (QM) plan. The modification in the QM plan shall not affect the form, fit, or function as described herein. The individual item requirements for device class M shall be in accordance with MIL-PRF-38535, appendix A fo

31、r non-JAN class level B devices and as specified herein. 3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified in MIL-PRF-38535 and herein for device classes Q and V or MIL-PRF-38535, appendix A and herein for device class M. 3.2.1

32、 Case outlines. The case outlines shall be in accordance with 1.2.4 herein and on figure 1. 3.2.2 Terminal connections. The terminal connections shall be as specified on figure 2. 3.2.3 Block diagram. The block diagram shall be as specified on figure 3. 3.2.4 Timing waveforms. The timing waveforms s

33、hall be as specified on figure 4. 3.3 Electrical performance characteristics and postirradiation parameter limits. Unless otherwise specified herein, the electrical performance characteristics and postirradiation parameter limits are as specified in table I and shall apply over the full case operati

34、ng temperature range. 3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table II. The electrical tests for each subgroup are defined in table I. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STAN

35、DARD MICROCIRCUIT DRAWING SIZE A 5962-91501 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL D SHEET 5 DSCC FORM 2234 APR 97 3.5 Marking. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturers PIN may also be marked. For packages where marki

36、ng of the entire SMD PIN number is not feasible due to space limitations, the manufacturer has the option of not marking the “5962-“ on the device. For RHA product using this option, the RHA designator shall still be marked. Marking for device classes Q and V shall be in accordance with MIL-PRF-3853

37、5. Marking for device class M shall be in accordance with MIL-PRF-38535, appendix A. 3.5.1 Certification/compliance mark. The certification mark for device classes Q and V shall be a “QML“ or “Q“ as required in MIL-PRF-38535. The compliance mark for device class M shall be a “C“ as required in MIL-P

38、RF-38535, appendix A. 3.6 Certificate of compliance. For device classes Q and V, a certificate of compliance shall be required from a QML-38535 listed manufacturer in order to supply to the requirements of this drawing (see 6.6.1 herein). For device class M, a certificate of compliance shall be requ

39、ired from a manufacturer in order to be listed as an approved source of supply in MIL-HDBK-103 (see 6.6.2 herein). The certificate of compliance submitted to DSCC-VA prior to listing as an approved source of supply for this drawing shall affirm that the manufacturers product meets, for device classe

40、s Q and V, the requirements of MIL-PRF-38535 and herein or for device class M, the requirements of MIL-PRF-38535, appendix A and herein. 3.7 Certificate of conformance. A certificate of conformance as required for device classes Q and V in MIL-PRF-38535 or for device class M in MIL-PRF-38535, append

41、ix A shall be provided with each lot of microcircuits delivered to this drawing. 3.8 Notification of change for device class M. For device class M, notification to DSCC-VA of change of product (see 6.2 herein) involving devices acquired to this drawing is required for any change that affects this dr

42、awing. 3.9 Verification and review for device class M. For device class M, DSCC, DSCCs agent, and the acquiring activity retain the option to review the manufacturers facility and applicable required documentation. Offshore documentation shall be made available onshore at the option of the reviewer.

43、 3.10 Microcircuit group assignment for device class M. Device class M devices covered by this drawing shall be in microcircuit group number 105 (see MIL-PRF-38535, appendix A).Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRA

44、WING SIZE A 5962-91501 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL D SHEET 6 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics. Test Symbol Conditions 1/ -55C TC +125C unless otherwise specified 4.5 V VDD 5.5 V Group A subgroups Device type Limits Unit

45、 Min Max Input high voltage VIH0.7(VDD) VDD+ 0.3 V Input low voltage VIL SS 0.3 0.2(VDD) V Input hysteresis 2/ VHYS0.5 V Input leakage current, input-only pins 3/ IINVIN= VDDor VSSInput-only pins. -2.5 +2.5 A High impedance (off-state) leakage current, all input/output and output pins 3/ IOZVIN= VDD

46、or VSSAll input/output and output pins. -2.5 +2.5 A CMOS outputs high voltage 3/ 4/ VOHIOH= -10.0 A Group 1, 2, 4 I/O pins and all output pins. VDD 0.2 V CMOS outputs low voltage 3/ VOLIOL= 10.0 A Group 1, 2, 4 I/O pins and all output pins. 0.2 V Output high voltage 3/ 4/ VOHIOH= -0.8 mA Group 1, 2,

47、 4 I/O pins and all output pins. VDD 0.8 V IOL= 1.6mA, Group 1 CLKOUT, FREEZE/QOUT, IPIPE 0.4 IOL= 5.3 mA, Group 2, 4 I/O pins, CSBOOT, BG/CS 0.4 Output low voltage 3/ VOLIOL= 12 mA, Group 3 0.4 V Three-state control input high voltage VIHTSC1.6(VDD) 9.1 V VIN= VILData(15:0) -120 Data bus mode selec

48、t pull-current 5/ IMSPVIN= VIHData(15:0) All -15 A 01 124 VDD supply current, RUN 6/ 7/ IDD02 160 mA LPSTOP = 32.768 kHz crystal VCO off (STSIM = 0) SIDD350 A LPSTOP (external clock input freq. = max. fSYS) SIDD1, 2, 3 All 5 mA See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-91501 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 REVISION LEVEL D SHEET 7 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics - Continued. Test Symbol Cond