DLA SMD-5962-90965 REV H-2011 MICROCIRCUIT MEMORY DIGITAL CMOS FIELD PROGRAMMABLE GATE ARRAY 2 000 GATES MONOLITHIC SILICON.pdf

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1、 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Add device type 02; editorial changes throughout. Redrawn. 93-06-23 M. A. Frye B Update boilerplate. Add device types 03 and 04. Add case outline M. Editorial changes throughout. 94-06-30 M. A. Frye C Add 05 device. Removed some parameters from t

2、able IIB. Updated boilerplate. ksr 98-04-06 Raymond Monnin D Added equation to footnote 2/, made corrections to table IB. Changed sample size in paragraph 4.4.1. Removed (Dose Rate Induced latchup testing) and (Dose Rate Upset testing) paragraphs. Updated boilerplate. ksr 98-07-10 Raymond Monnin E C

3、hange 1.3 Maximum junction temperature from 175C to 150C. Added footnote 2/ to Figure 2 for the T and M case outlines. Add die information per Appendix A. ksr 98-09-21 Raymond Monnin F Correct bond pad symbol on figure A-1, pad #45 I/O vs GND. Updated boilerplate. ksr 04-03-08 Raymond Monnin G Added

4、 additional information to footnote 2 on figure 2 Terminal connections, for case outlines T and M. Added note 3 to figure A-1 A1020B and RH1020 Bond Pad Locations and Functions. ksr 05-05-13 Raymond Monnin H Added device types 06-09 in section 1.2.2. Added vendor CAGE 1RU44. Added updated RHA requir

5、ements in section 1.5 for device types 06-09. Added Case outline N. Updated SEP limits in Table IB. Updated boilerplate paragraphs required by the MIL-PRF-38535 requirements. lhl 11-11-07 Charles F. Saffle REV SHET REV H H H H H H H H H H H H SHEET 15 16 17 18 19 20 21 22 23 24 25 26 REV STATUS REV

6、H H H H H H H H H H H H H H OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PMIC N/A PREPARED BY Tim H. Noh DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 http:/www.landandmaritime.dla.mil STANDARD MICROCIRCUIT DRAWING CHECKED BY Kenneth Rice THIS DRAWING IS AVAILABLE FOR USE BY ALL APPROVED BY Ti

7、m H. Noh MICROCIRCUIT, MEMORY, DIGITAL, CMOS, FIELD PROGRAMMABLE GATE ARRAY, 2,000 GATES, MONOLITHIC SILICON DEPARTMENTS AND AGENCIES OF THE DEPARTMENT OF DEFENSE DRAWING APPROVAL DATE 92-06-23 AMSC N/A REVISION LEVEL H SIZE A CAGE CODE 67268 5962-90965 SHEET 1 OF 26 DSCC FORM 2233 APR 97 5962-E409-

8、09 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-90965 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL H SHEET 2 DSCC FORM 2234 APR 97 1. SCOPE 1.1 Scope. This drawing documents two product a

9、ssurance class levels consisting of high reliability (device classes Q and M) and space application (device class V). A choice of case outlines and lead finishes are available and are reflected in the Part or Identifying Number (PIN). When available, a choice of Radiation Hardness Assurance (RHA) le

10、vels is reflected in the PIN. 1.2 PIN. The PIN is as shown in the following example: 5962 - 90965 01 Q X C | | | | | | | | | | | | | | | | | Federal RHA Device Device Case Lead stock class designator type class outline finish designator (see 1.2.1) (see 1.2.2) designator (see 1.2.4) (see 1.2.5) / (s

11、ee 1.2.3) / Drawing number 1.2.1 RHA designator. Device classes Q and V RHA marked devices meet the MIL-PRF-38535 specified RHA levels and are marked with the appropriate RHA designator. Device class M RHA marked devices meet the MIL-PRF-38535, appendix A specified RHA levels and are marked with the

12、 appropriate RHA designator. A dash (-) indicates a non-RHA device. 1.2.2 Device type(s). The device type(s) identify the circuit function as follows: Device type Generic number Circuit function Bin speed 01 1020A 2000 gate, field programmable gate array 186 ns 02 1020A-1 2000 gate, field programmab

13、le gate array 158 ns 03 1020B 2000 gate, field programmable gate array 168.2 ns 04 1020B-1 2000 gate, field programmable gate array 142.9 ns 05 RH1020 2000 gate, field programmable gate array (radiation hardened) 168.2 ns 06 197A805 (RH1020B) 2000 gate, field programmable gate array (radiation harde

14、ned) 168.2 ns 07 197A805 (RH1020B) 2000 gate, field programmable gate array (radiation hardened) 168.2 ns 08 197A805 (RH1020B) 2000 gate, field programmable gate array (radiation hardened) 168.2 ns 09 197A805 (RH1020B) 2000 gate, field programmable gate array (radiation hardened) 168.2 ns 1.2.3 Devi

15、ce class designator. The device class designator is a single letter identifying the product assurance level as follows: Device class Device requirements documentation M Vendor self-certification to the requirements for MIL-STD-883 compliant, non-JAN class level B microcircuits in accordance with MIL

16、-PRF-38535, appendix A Q or V Certification and qualification to MIL-PRF-38535 1.2.4 Case outline(s). The case outline(s) are as designated in MIL-STD-1835 and as follows: Outline letter Descriptive designator Terminals Package style X CQCC2 - J44 44 J-lead chip carrier Y CQCC2 - J68 68 J-lead chip

17、carrier Z CQCC2 - J84 84 J-lead chip carrier U CMGA15 - P85 84 Pin grid array 1/ T CQCC1 - F84 84 Unformed lead chip carrier M See figure 1 84 Unformed lead chip carrier N See figure 1 84 Unformed lead chip carrier 1.2.5 Lead finish. The lead finish is as specified in MIL-PRF-38535 for device classe

18、s Q and V or MIL-PRF-38535, appendix A for device class M. 1/ Actual number of pins is 85 including one index or orientation pin (C3). Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-90965 DLA LAND AND MARITI

19、ME COLUMBUS, OHIO 43218-3990 REVISION LEVEL H SHEET 3 DSCC FORM 2234 APR 97 1.3 Absolute maximum ratings. 2/ DC supply voltage range (VDD) - 0.5 V dc to +7.0 V dc Input voltage range (VI) - - 0.5 V dc to VDD+ 0.5 V dc Output voltage range (VO) - - 0.5 V dc to VDD+ 0.5 V dc I/O source sink current (I

20、IO) - 20 mA Storage temperature range (TSTG) - - 65C to +150C Lead temperature (soldering, 10 seconds), (device 05) - 300C Lead temperature (soldering, 5 seconds), (devices 06 09) - 250C Thermal resistance, junction-to-case (JC) Case outline X, Y, Z, U, T - See MIL-STD-1835 Case outline M (device ty

21、pes 03-04) - 10C/W 3/ Case outline M and N (device types 05-07) - 3C/W 3/ Case outline N (device types 08-09) - 2.5C/W 3/ Maximum junction temperature (TJ) - +150C 1.4 Recommended operating conditions. 4/ Supply voltage (VDD) - +4.5 V dc to +5.5 V dc Case operating temperature range (TC) - -55C to +

22、125C 1.5 Radiation features. Maximum total dose available: Device type 05 (dose rate = 50 300 rads (Si)/s) - 300K rads (Si) 5/ Device type 06-09 (dose rate = 27 rads (Si)/s) - 100K rads (Si) 6/ Single event phenomenon (SEP): Device type 05: No SEL occurs at an effective LET (see 4.4.4.2) - 84 MeV/(m

23、g/cm2) Device types 06-09: No SEL occurs at an effective LET (see 4.4.4.2) - 120 MeV/(mg/cm2) Device types 05: No SEU occurs at an effective LET (see 4.4.4.2) (C-Latch) - 13 MeV/(mg/cm2) No SEU occurs at an effective LET (see 4.4.4.2) (1 MHz clock) 18.8 MeV/(mg/cm2) Device types 06-09: No SEU occurs

24、 at an effective LET (see 4.4.4.2) (C-Latch) - 3.6 MeV/(mg/cm2) No SEU occurs at an effective LET (see 4.4.4.2) (1 MHz clock) 120 MeV/(mg/cm2) Device types 05: No SEDR occurs at effective LET (see 4.4.4.2) - 40 MeV/(mg/cm2) Device types 06-09: No SEDR occurs at effective LET (see 4.4.4.2) - 115 MeV/

25、(mg/cm2) 1.6 Digital logic testing for device classes Q and V. Fault coverage measurement of manufacturing logic tests (MIL-STD-883, method 5012) - 100 percent 7/ 2/ Stresses above the absolute maximum rating may cause permanent damage to the device. Extended operation at the maximum levels may degr

26、ade performance and affect reliability. 3/ When a thermal resistance for this case is specified in MIL-STD-1835 that value shall supersede the value indicated herein. 4/ Power shall be applied to the device only in the following sequences to prevent damage due to excessive currents. a. Power- up seq

27、uence: GND, VDD, Inputs. b. Power-down: Inputs, VDD, GND. 5/ For device 05, device electrical characteristics are verified for post irradiation levels at 25C per MIL-STD-883, method 1019, condition A and post 168 hours, 100C, biased anneal. 6/ For device types 06-09, total dose irradiation test perf

28、ormed according to MIL-STD-883, method 1019, condition B. 7/ 100 percent test coverage of blank programmable logic devices. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-90965 DLA LAND AND MARITIME COLUMBUS

29、, OHIO 43218-3990 REVISION LEVEL H SHEET 4 DSCC FORM 2234 APR 97 2. APPLICABLE DOCUMENTS 2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a part of this drawing to the extent specified herein. Unless otherwise specified, the issues of

30、 these documents are those cited in the solicitation or contract. DEPARTMENT OF DEFENSE SPECIFICATION MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for. DEPARTMENT OF DEFENSE STANDARDS MIL-STD-883 - Test Method Standard Microcircuits. MIL-STD-1835 - Interface Standard For

31、 Microcircuit Case Outlines. DEPARTMENT OF DEFENSE HANDBOOKS MIL-HDBK-103 - List of Standard Microcircuit Drawings. MIL-HDBK-780 - Standard Microcircuit Drawings. (Copies of these documents are available online at https:/assist.daps.dla.mil/quicksearch/ or from the Standardization Document Order Des

32、k, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.) 2.2 Non-Government publications. The following document(s) form a part of this document to the extent specified herein. Unless otherwise specified, the issues of the documents are the issues of the documents cited in the solicitation.

33、 ASTM INTERNATIONAL (ASTM) ASTM Standard F1192 - Standard Guide for the Measurement of Single Event Phenomena (SEP) Induced by Heavy Ion Irradiation of Semiconductor Devices. (Applications for copies of ASTM publications should be addressed to: ASTM International, PO Box C700, 100 Barr Harbor Drive,

34、 West Conshohocken, PA 19428-2959; http:/www.astm.org.) JEDEC SOLID STATE TECHNOLOGY ASSOCIATION (JEDEC) JEDEC Standard No. 78 - IC Latch-Up Test. (Copies of this document are available online at www.jedec.org/ or from JEDEC Solid State Technology Association, 3103 North 10thStreet, Suite 240-S, Arl

35、ington, VA 22201). (Non-Government standards and other publications are normally available from the organizations that prepare or distribute the documents. These documents also may be available in or through libraries or other informational services.) 2.3 Order of precedence. In the event of a confl

36、ict between the text of this drawing and the references cited herein, the text of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a specific exemption has been obtained. 3. REQUIREMENTS 3.1 Item requirements. The individual item req

37、uirements for device classes Q and V shall be in accordance with MIL-PRF-38535 and as specified herein or as modified in the device manufacturers Quality Management (QM) plan. The modification in the QM plan shall not affect the form, fit, or function as described herein. The individual item require

38、ments for device class M shall be in accordance with MIL-PRF-38535, appendix A for non-JAN class level B devices and as specified herein. 3.1.1 Microcircuit die. For the requirements of microcircuit die, see appendix A to this document. 3.2 Design, construction, and physical dimensions. The design,

39、construction, and physical dimensions shall be as specified in MIL-PRF-38535 and herein for device classes Q and V or MIL-PRF-38535, appendix A and herein for device class M. 3.2.1 Case outline(s). The case outline(s) shall be in accordance with 1.2.4 herein and figure 1. Provided by IHSNot for Resa

40、leNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-90965 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 REVISION LEVEL H SHEET 5 DSCC FORM 2234 APR 97 3.2.2 Terminal connections. The terminal connections shall be as specified on figure 2

41、. 3.2.3 Truth table(s). 3.2.3.1 Unprogrammed devices. The truth table or test vectors for unprogrammed devices for contracts involving no altered item drawing is not part of this drawing. When required in screening (see 4.2 herein) or quality conformance inspection group A, B, C, D, or E (see 4.4 he

42、rein), the devices shall be programmed by the manufacturer prior to test. A minimum of 50 percent of the total number of logic modules shall be utilized or at least 25 percent of the total logic modules shall be utilized for any altered item drawing pattern. 3.2.3.2 Programmed devices. The truth tab

43、le or test vectors for programmed devices shall be as specified by an attached altered item drawing. 3.2.4 Switching waveform and test circuit. The switching waveform and test circuit shall be as specified on figure 3. 3.2.5 Radiation exposure circuit. The radiation exposure circuit shall be specifi

44、ed on figure 4. 3.3 Electrical performance characteristics and postirradiation parameter limits. Unless otherwise specified herein, the electrical performance characteristics and postirradiation parameter limits are as specified in table IA and shall apply over the full case operating temperature ra

45、nge. 3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table IIA. The electrical tests for each subgroup are defined in table IA. 3.5 Marking. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturers PIN may also be marked. For packages where marking of the entire SMD PIN number is not feasible due to space limitations, the manufacturer has the option of not marking the “5962-“ on the devic