DLA SMD-5962-90692 REV C-1996 MICROCIRCUIT DIGITAL CMOS 16-BIT MICROCONTROLLER WITH ON CHIP EPROM MONOLITHIC SILICON《硅单片 装有单片电可编程序只读存储器的16位微型处理器 氧化物半导体数字微型电路》.pdf

《DLA SMD-5962-90692 REV C-1996 MICROCIRCUIT DIGITAL CMOS 16-BIT MICROCONTROLLER WITH ON CHIP EPROM MONOLITHIC SILICON《硅单片 装有单片电可编程序只读存储器的16位微型处理器 氧化物半导体数字微型电路》.pdf》由会员分享，可在线阅读，更多相关《DLA SMD-5962-90692 REV C-1996 MICROCIRCUIT DIGITAL CMOS 16-BIT MICROCONTROLLER WITH ON CHIP EPROM MONOLITHIC SILICON《硅单片 装有单片电可编程序只读存储器的16位微型处理器 氧化物半导体数字微型电路》.pdf（37页珍藏版）》请在麦多课文档分享上搜索。

1、SMD-5b2-90672 REV C b 00904LO 3011 W DEFENSE LOGISTICS AGENCY DEFENSE SUPPLY CENTER, COLUMBUS 3990 E BROAD STREET COLUMBUS, OH 43216-5000 IN REPLY REFER TO DSCC-V . Hess(DS1 850- 47/6 692- NOV 2 O 1996 SUBJECT: Notice of Revision (NOR) 5962-RO43-97 for Standard Microcircuit Drawing (SMD) 5962-90692

2、Military/Industry Distribution The enclosed NOR is approved for use effective as of the date of the NOR. In accordance with MIL-STD-100 SMD holders should, as a minimum, handwrite those changes described in the NOR to sheet 1 of the subject SMD. After completion, the NOR should be attached to the su

3、bject SMD for future reference. Those companies who were listed as approved sources of supply prior to this action have agreed to actions taken on devices for which they had previously provided DSCC a certificate of compliance. This is evidenced by an existing active current certificate of complianc

4、e on file at DSCC with a DSCC record of verbal coordination. The certificate of compliance for these devices is considered concurrence with the new revision unless DSCC is otherwise notified. If you have comments or questions, please contact Tom Hess at (DSN)850-0547/(6 14)692-0547. 1 Encl /MONICA L

5、. POELKING 1 Chief, Custom Microelectronics Branch Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-NOTICE OF REVISION (NOR) THIS REVISION DESCRIBED BELOW HAS BEEN AUTHORIZED FOR THE DOCUMENT LISTED. 1. DATE (YYMMDD) Form Approved 96-1 0-29 OMB No. 07

6、04-0188 3990 East Broad St. Columbus, OH 43216-5000 I. TYPED NAME (First, Middle Initial, Last) UM reporting burden for this colledion is estimated to average 2 houn per response including the me for reviewi 2, ISUING CONTRACTING OFFICER FOR THE CONTRACT/ PROCURING ACTIVITY NUMBER LISTED IN ITEM 2 O

7、F THIS FORM. . s, mi%,eris(ing ab xlrces. amats gaihaMi o( LEASE D%T RETURN Y UA c MPLETED FORM TO ET distribution io unlimlted. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-1. SCOPE I X Y 1.1 m. This drawing docunents two product assurance class

8、levels consisting of high reliability (device classes P and M) and space application (device class V). and are reflected in the Part or Identifying Nvnber (PIN). (RHA) leveis are reflected in the PIN. A choice of case outlines and lead finishes are available !Am available, a choice of Radiation Hard

9、ness Assurance 1.2 m. lhe PI# is as shown in the following exenple: AL111 Federal R HA Device Device Case Lead stock class designator type c 1 ass out 1 ine finish designator (see 1.2.1) (see 1.2.2) des i gnat or (see 1.2.4) (see 1.2.5) Ad (see 1.2.3) / Drawing nunber 1.2.1 desi- . Device classes P

10、and V RHA marked devices meet the MIL-PRF-38535 specified RHA levels and are marked with the appropriate RHA designator. specified RHA levels and are marked with the appropriate RHA designator. A dash (-1 indicates a non-RHA device. Device class M RHA marked devices meet the MIL-PRF-38535, appendix

11、A 1.2.2 Device tam . The device typeCs) identify the circuit function as follows: Device WE i rcui t funct i pn SIZE A STANDARD MICROCIRCUIT DRAWING DEFENSE ELECTRONICS SUPPLY CENTER DAYTON, OHIO 45444 REVISION LEVEL o1 02 03 o4 5962-90692 SHEET 2 87C196KC 87C19U 87C 1- 87C19C 16 MHz CHMOS 16-bit, m

12、icrocontroller with 16 k bytes of on-chip EPROW and 512 byte register file. 16 MHt CWS 16-bit, microcontroller with 32 k bytes of on-chip EPROM and 1024 byte register RAH. 20 MHz CHIIOS 16-bit microcontroller with 32 k bytes of on-chip EPROW and 1024 byte register RAM. 16 MHz CHWS 16-bit, microcontr

13、oller with 16 k bytes of on-chip EPROM and 512 byte register file. 1/ 1.2.3 pevice e- . The device class designator is a single letter identifying the product assurance level as follows: M Vendor self-certification to the requirenicnts for MIL-STD-883 conpliant, non-JAN class level B microcircuits i

14、n accordance with MIL-PRF-38535, appendix A O or V Cert i fi cat i on and qw 1 i fi cat i on to Mi L -PRF-38535 1.2.4 . The case outline(s1 are as designated in MIL-STD-1835 and as follows: BLtlim ISmL l3duLwk CMGU - P68 See figure 1 68 Pin grid array u 68 Ceramic quad f Lat u . lhe lead finish is a

15、s specified in MIL-PRF-38535 for device classes P and V or 1.2.5 finiee figure 4, eacal Derforinence -isticee figure 4, HOLD/HLDA timings Group A subgroups 9,10,11 evi ce type Ai l i1-03 04 ALL Limits todo i- OSC -25 55 l Unit ns STANDARD I SIZE A MICROCIRCUIT DRAWING DEFENSE ELECTRONICS SUPPLY CENT

16、ER DAYTON, OHIO 45444 5962-90692 I SHEET 9 REVISION LEVEL DESC FORM 193A JUL 94 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-SVD-5962-90672 REV B 9999996 0083333 330 Test HLDA low to address float HLDA OU to BHE, INST, RD, UR ueakly driven CLKOUT

17、Lou to HLDA high TABLE 1. -ractpristics r - Continued. I s-1 tHALAZ tHALBZ CLHAH evi ce type Al l 1-03 04 I Limits Hin Max 10 10 15 *IA high to address no HAHAX 01,02 04 03 01,OZ o4 03 01,oz 04 03 01,oz 04 03 ALL IA high to EHE, INST, RD, dR valid 3.5 16 3.5 20 62.5 286 50 286 22 17 22 17 10 .- 1 O

18、lest I1 I2 I2 +l +1 Input capacitance Resolution Absolute error Full scale error Zero offset error Nonlinearity Differential non1 ineari ty error Channel to ch8nneL mtching RepeatabiLity Tenperature coefficients: offset, full scale, different ia1 non1 ineari ty See footnotes at end of table. Condi t

19、i ons -55.C S TC S +125C unless otherwise specified 4.5 v s vcc s 5.5 v 1/ 10-bit converter e/ characteristics B-bit A/D converter e/ characteristics Group A subgroups 4. 5, 6 Limits Unit Min I Max I Levels bits I I 0.003 LSBPC 5962-90692 . REVISION LEVEL SHEET STANDARD MICROCIRCUIT DRAWING DEFENSEE

20、LECTRONICSSUPPLYCENTER DAYTON, OHIO 45444 DESC FORM 193A JUL 94 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-TABLE I. Flectrical wrforinence characteristics - Continued. - - - - - - J./ The following pins are active low: pins include Port 1, P2.6,

21、 and P2.7. Standard outputs include ADO-15, RD.M, ALE, BHE, INST, HSO pins, PW/P2.5, E of ALE/AVD, BHE/MH, EA, RD, REXT,UR/RL.PBD (Quasi-bidirectional) STAN DARD MICROCIRCUIT DRAWING DEFENSE ELECTRONICS SUPPLY CENTER DAYTON, OHIO 45444 CLKOUT, RESET, Ports 3 and 4, TXD/PZ.O and RXD (in-serial mode O

22、). EXTINT/P2.2, T2CLK/P2.3, and T2RST/P2.4. and wilt typically operate below 1 Ht. k3.2 nd. or VOH is held below VCC -0.7 V: specification is not valid for RESET. However, the device is static by design Maxinun current per bus pin (date and control) during normal operation is Waximun current per pin

23、 must be externally limited to the following values if VOL is held above 0.45 V Ports 3 and 4 are open drain outputs. Stardard inputs include HSI pk, READY, BUSUIDTH, HI, RXD/P2.1, Testing performed at 3.5 MHz. IoL on output pins: IOH on quasi-bidirectional pins: IOH on standard output pins: During

24、normal (nontransient) conditions the follow total current limits apply: 10 mA self limiting 10 IM Port 1, P2.6 IOL: 29 nd 10 is self limiting HSO, P2.0, Rn, BESET IOL: 29 mA IOH: 26 nd dp0-AD15 IOL: 52 ITA IOH: 52 nd RD, ALE, INST-CLKWT IOL: 13 nd 10: 13 d P2.5, P2.7, UR, BHE IOL: 13 nd IOH: 11 w Un

25、less otherwise specified, all test cditions shell be worst conditions. Test initially and at process and design changes. in table I. Violating these specifications in RESET may cause the part to enter test modes. If maximm is exceeded, additional wait states will occur. If wait states are used, add

26、2 TOSC*N, where N = mniber of wait states. Assuning back-to-back bus cycles. * P2.4 STANDARD MICROCIRCUIT DRAWING DEFENSE ELECTRONICS SUPPLY CENTER DAYTON, OHIO 45444 wth rewated PROG wlse and SIZE A 5962090692 REVISION LEVEL SHEET 26 RESET I - AODR AODR *2 DATA DATA PORTS ADDR/COMMAND FICURE 5. con

27、figycation wrvefornis - Continued. JUL 94 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-3.11.2 -ititv of . Uhen specified, devices shall be programed to the specified pattern using the procedures and characteristics specified in 4.6 and table 111.

28、, 3.12.3 yerificatjon of erasure DrQarwilitv of EPm When specified, devices shall be verified as either programed to the specification pattern or erased. As a minim, verification shall consist of performing a functional test (subgroup 7) to verify that all bits are in the proper state. the proper st

29、ate shall constitute a device failure, and shall be removed from the lot. Any bit that does not verify to be in 4. WALITY ASSURANCE PROVISIONS 4.1 wlina and mect ipp. For device classes P and V, senpiing and inspection procedures shall be in accordance with MIL-PRF-38535 or as modified in the device

30、 manufacturers Quality Management (PMI plan. PM plan shall not affect the form, fit, or function as described herein. procedures shall be in accordance with MIL-PRF-38535, appendix A. The modification in the For device class M, sampling and inspection 4.2 Screen inq. For device classes P and V, scre

31、ening shall be in accordance uith MIL-PRF-38535, and shall be conducted on al devices prior to qualification and technology conformance inspection. shall be in accordance uith method 5001 of MIL-STD-883, and shall be conducted on all devices prior to quality conformance inspection. For device class

32、M, screening 4.2.1 w. a. Burn-in test, method 1015 of MIL-STO-883. (1) Test condition C or D. level control and shall be made available to the preparing or acquiring activity upon request. circuit shall specify the inputs, outputs, biases, and poner dissipation, as applicable, in accordance uith the

33、 intent specified in test method 1015. The test circuit shall be maintained by the manufacturer under docunent revision The test (2) TA = +125C, minim. Interim and final electrical test parameters shall be as specified in table II herein. c. A data retention stress test shall be included as part of

34、the screening procedure and shall consist of the following steps: b. Program greater than 95 percent of the bit locations, including the slowest programing cell (see 3.11.2). Bake, unbiased, for 72 hours at +140DC to screen for data retention lifetime. Perform a margin test using V, = +5.9 V at +25*

35、C using loose timing (i-e., TACC 1 ps). Perform dynamic burn-in (see 4.2.la). Margin at VM = 5.9 V. Perform electrical tests (see 4.2). Erase (see 3.11.11, except devices submitted for groups A, E, C and D testing. Verify erasure (see 3.11.3). lhe remaining cells shall provide a worst case speed pat

36、tern. I SIZE I I 5962-90692 REVISION LEVEL SHEET STANDARD MICROCIRCUIT DRAWING DEFENSE ELECTRONICS SUPPLY CENTER DAYTON, OHIO 45444 I I 1 DESC FORM 193A JUL 94 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-SND-5962-9069E REV B = 9999996 O083329 370

37、 Program at +25C, 100 percent of the bits. Bake, unbiased, for 24 hours at +250*C. Perform margin test at vM = 5.9 V. Erase (see 3.11.1). Perform interim electrical tests in accordance with table II. Program 100 percent of the bits and verify (see 3.11.3). Perform burn-in (see 4.2.la). One-hurtdred

38、percent test at +25Y (group A, subgroups 1 and 7). apply PDA. Perform remaining final electrical subgroups and group A testing. Erase, devices may be submitted for groups B, C, and D at this time. Verify erasure (see 3.11.3). Steps 1 through 4 are performed at wafer level. VM 5.9 V with loose timing

39、, .2.2 Wtional criteria for device cl- p and 1. a. The burn-in test duration, test condition and test temperature, or approved alternatives shall be as specified in the device manufacturers QM plan in accordance with MIL-PRF-38535. maintained under docunent revision Level control of the device manuf

40、acturers Technology Review Board (TRB) in accordance with MIL-PRF-38535 and shall be made available to the acquiring or preparing activity upon request. The test circuit shall specify the inputs, outpts, biases, and power dissipation, as applicable, in accordance with the intent specified in test me

41、thod 1015 of MIL-STD-883. The burn-in test circuit shall be b. Interim and final electrical test parenieters shall be as specified in table II herein. c. Additional screening for device class V beyond the requirements of device class P shall be as specified in MIL-PRF-38535, appendix B. . . ;.3 $es

42、a . Qualification inspection for device classes P and V shall Inspections to be performed shall be those specified in MIL-PRF-38535 and herein 8- groups A, B, C, D, and E inspections (see 4.4.1 through 4.4.4). -.4 - * . in accordance with MIL-PRF-38535. Technology conformance inspection for classes

43、Q and V shall be in accordance with MIL- -38535 including groups A, B, C, D, and E inspections and as specified herein except where option 2 of Quality conformance inspection for device class M shall be accordance with MIL-PRF-38535, appendix A and as specified herein. Inspections to be performed fo

44、r device class M 1 be those specified in method 5005 of MIL-STD-883 end herein for groups A, B, C, D, and E inspections (see 4.4.1 ugh 4.4.4). PRF-38535 permits alternate in-line control testing. 4.1 A inswctiQp. a. Tests shall be as specified in table II herein. b. for device class M, subgrwps 7 an

45、d 8 tests shall consist of verifying the EPROM pattern specified and the instruction set. available from the approved source of supply. For device classes a and V, subgroups 7 and 8 shall include verifying the fvictionality of the device; these tests shall have bem fault graded in accordance with MI

46、L-STD-883, test method 5012 (see 1.5 herein). changes which may afbct capacitance. A minimun sample size of 5 devices with zero rejects shall be required. After completion of all testing, the devices shall be erased an verified (except devices submitted for groups C and 0 testing). lhe instruction s

47、et forms a part of the vendors test tape and shall be maintained and c. Subgroup 4 (Cs and C measurement) shall k measured only for the initial test and after process or design d. All devices selected for testing shall have the EPROM programed with a checkerboard pattern or equivalent. 5962-90692 REVISION LEVEL SHEET STANDARD MICROCIRCUIT DRAWING DEFENSE ELECTRONICS SUPPLY CENTER DAYTON, OHIO 45444 DESC FORM 193A JUL 94 Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-