DLA SMD-5962-90544 REV A-2003 MICROCIRCUIT DIGITAL CMOS HIGH PERFORMANCE MICROCONTROLLER MONOLITHIC SILICON《硅单片 高性能微型控制器 氧化物半导体数字微型电路》.pdf

《DLA SMD-5962-90544 REV A-2003 MICROCIRCUIT DIGITAL CMOS HIGH PERFORMANCE MICROCONTROLLER MONOLITHIC SILICON《硅单片 高性能微型控制器 氧化物半导体数字微型电路》.pdf》由会员分享，可在线阅读，更多相关《DLA SMD-5962-90544 REV A-2003 MICROCIRCUIT DIGITAL CMOS HIGH PERFORMANCE MICROCONTROLLER MONOLITHIC SILICON《硅单片 高性能微型控制器 氧化物半导体数字微型电路》.pdf（21页珍藏版）》请在麦多课文档分享上搜索。

1、 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED A Update boilerplate to MIL-PRF-38535 requirements. - CFS 03-10-07 Thomas M. Hess CURRENT CAGE CODE 67268 THE ORIGINAL FIRST SHEET OF THIS DRAWING HAS BEEN REPLACED. REV SHET REV A A A A A A SHEET 15 16 17 18 19 20 REV STATUS REV A A A A A A A A A

2、A A A A A OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PMIC N/A PREPARED BY Jeffery Tunstall DEFENSE SUPPLY CENTER COLUMBUS STANDARD MICROCIRCUIT DRAWING CHECKED BY Tim H. Noh COLUMBUS, OHIO 43216 http:/www.dscc.dla.mil THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS APPROVED BY Monica L. P

3、oelking MICROCIRCUIT, DIGITAL, CMOS, HIGH PERFORMANCE MICROCONTROLLER AND AGENCIES OF THE DEPARTMENT OF DEFENSE DRAWING APPROVAL DATE 91-11-01 MONOLITHIC SILICON AMSC N/A REVISION LEVEL A SIZE A CAGE CODE 14933 5962-90544 SHEET 1 OF 20 DSCC FORM 2233 APR 97 5962-E510-03 DISTRIBUTION STATEMENT A. App

4、roved for public release; distribution is unlimited.Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-90544 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 REVISION LEVEL A SHEET 2 DSCC FORM 2234 APR 9

5、7 1. SCOPE 1.1 Scope. This drawing documents two product assurance class levels consisting of high reliability (device classes Q and M) and space application (device class V). A choice of case outlines and lead finishes are available and are reflected in the Part or Identifying Number (PIN). When av

6、ailable, a choice of Radiation Hardness Assurance (RHA) levels are reflected in the PIN. 1.2 PIN. The PIN is as shown in the following example. 5962 - 90544 01 M X X Federal RHA Device Device Case Lead stock class designator type class outline finish designator (see 1.2.1) (see 1.2.2) designator (se

7、e 1.2.4) (see 1.2.5) / (see 1.2.3) / Drawing number 1.2.1 RHA designator. Device classes Q and V RHA marked devices meet the MIL-PRF-38535 specified RHA levels and are marked with the appropriate RHA designator. Device class M RHA marked devices meet the MIL-PRF-38535, appendix A specified RHA level

8、s and are marked with the appropriate RHA designator. A dash (-) indicates a non-RHA device. 1.2.2 Device type(s). The device type(s) identify the circuit function as follows: Device type Generic number Circuit function 01 HPC16003 High-performance microcontroller 02 HPC16083 High-performance progra

9、mmed microcontroller 1.2.3 Device class designator. The device class designator is a single letter identifying the product assurance level as follows: Device class Device requirements documentation M Vendor self-certification to the requirements for MIL-STD-883 compliant, non-JAN class level B micro

10、circuits in accordance with MIL-PRF-38535, appendix A Q or V Certification and qualification to MIL-PRF-38535 1.2.4 Case outline(s). The case outline(s) are as designated in MIL-STD-1835 and as follows: Outline letter Descriptive designator Terminals Package style X See figure 1 68 Leaded chip carri

11、er Y See figure 1 68 Pin grid array 1.2.5 Lead finish. The lead finish is as specified in MIL-PRF-38535 for device classes Q and V or MIL-PRF-38535, appendix A for device class M. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT

12、DRAWING SIZE A 5962-90544 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 REVISION LEVEL A SHEET 3 DSCC FORM 2234 APR 97 1.3 Absolute maximum ratings. 1/ VCCwith respect to GND -0.5 V dc to +7.0 V dc All other pins GND 0.5 V dc to VCC+0.5 V dc Total allowable source current. 100 mA Total al

13、lowable sink current . 100 mA Storage temperature range -65C to +150C Lead temperature (soldering, 10 seconds) +300C Junction temperature (TJ) +150C Power dissipation (PD) . 0.85 W Thermal resistance, junction-to-case (JC): Cases X and Y . 5C/W 1.4 Recommended operating conditions. Supply voltage ra

14、nge (VCC) +4.5 V dc to +5.5 V dc Case operating temperature range (TC). -55C to +125C 2. APPLICABLE DOCUMENTS 2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a part of this drawing to the extent specified herein. Unless otherwise spe

15、cified, the issues of these documents are those listed in the issue of the Department of Defense Index of Specifications and Standards (DoDISS) and supplement thereto, cited in the solicitation. SPECIFICATION DEPARTMENT OF DEFENSE MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specifica

16、tion for. STANDARDS DEPARTMENT OF DEFENSE MIL-STD-883 - Test Method Standard Microcircuits. MIL-STD-1835 - Interface Standard Electronic Component Case Outlines. HANDBOOKS DEPARTMENT OF DEFENSE MIL-HDBK-103 - List of Standard Microcircuit Drawings. MIL-HDBK-780 - Standard Microcircuit Drawings. (Unl

17、ess otherwise indicated, copies of the specification, standards, and handbooks are available from the Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.) 2.2 Order of precedence. In the event of a conflict between the text of this drawing and the refer

18、ences cited herein, the text of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a specific exemption has been obtained. _ 1/ Stresses above the absolute maximum rating may cause permanent damage to the device. Extended operation at

19、the maximum levels may degrade performance and affect reliability. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-90544 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 REVISION LEVEL A SHEET 4 DSCC

20、FORM 2234 APR 97 3. REQUIREMENTS 3.1 Item requirements. The individual item requirements for device classes Q and V shall be in accordance with MIL-PRF-38535 and as specified herein or as modified in the device manufacturers Quality Management (QM) plan. The modification in the QM plan shall not aff

21、ect the form, fit, or function as described herein. The individual item requirements for device class M shall be in accordance with MIL-PRF-38535, appendix A for non-JAN class level B devices and as specified herein. 3.2 Design, construction, and physical dimensions. The design, construction, and ph

22、ysical dimensions shall be as specified in MIL-PRF-38535 and herein for device classes Q and V or MIL-PRF-38535, appendix A and herein for device class M. 3.2.1 Case outlines. The case outlines shall be in accordance with 1.2.4 herein and figure 1. 3.2.2 Terminal connections. The terminal connection

23、s shall be as specified on figure 2. 3.2.3 Block diagram. The block diagram shall be as specified on figure 3. 3.2.4 Timing waveforms. The timing waveforms shall be as specified on figure 4. 3.3 Electrical performance characteristics and postirradiation parameter limits. Unless otherwise specified h

24、erein, the electrical performance characteristics and postirradiation parameter limits are as specified in table I and shall apply over the full case operating temperature range. 3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table II. The elec

25、trical tests for each subgroup are described in table I. 3.5 Marking. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturers PIN may also be marked as listed in MIL-HDBK-103. For packages where marking of the entire SMD PIN number is not feasible due to space limi

26、tations, the manufacturer has the option of not marking the “5962-“ on the device. For RHA product using this option, the RHA designator shall still be marked. Marking for device classes Q and V shall be in accordance with MIL-PRF-38535. Marking for device class M shall be in accordance with MIL-PRF

27、-38535, appendix A. 3.5.1 Certification/compliance mark. The certification mark for device classes Q and V shall be a “QML“ or “Q“ as required in MIL-PRF-38535. The compliance mark for device class M shall be a “C“ as required in MIL-PRF-38535, appendix A. 3.6 Certificate of compliance. For device c

28、lasses Q and V, a certificate of compliance shall be required from a QML-38535 listed manufacturer in order to supply to the requirements of this drawing (see 6.6.1 herein). For device class M, a certificate of compliance shall be required from a manufacturer in order to be listed as an approved sou

29、rce of supply in MIL-HDBK-103 (see 6.6.2 herein). The certificate of compliance submitted to DSCC-VA prior to listing as an approved source of supply for this drawing shall affirm that the manufacturers product meets, for device classes Q and V, the requirements of MIL-PRF-38535 and herein or for de

30、vice class M, the requirements of MIL-PRF-38535, appendix A and herein. 3.7 Certificate of conformance. A certificate of conformance as required for device classes Q and V in MIL-PRF-38535 or for device class M in MIL-PRF-38535, appendix A shall be provided with each lot of microcircuits delivered t

31、o this drawing. 3.8 Notification of change for device class M. For device class M, notification to DSCC-VA of change of product (see 6.2 herein) involving devices acquired to this drawing is required for any change as defined in MIL-PRF-38535, appendix A. 3.9 Verification and review for device class

32、 M. For device class M, DSCC, DSCCs agent, and the acquiring activity retain the option to review the manufacturers facility and applicable required documentation. Offshore documentation shall be made available onshore at the option of the reviewer. 3.10 Microcircuit group assignment for device clas

33、s M. Device class M devices covered by this drawing shall be in microcircuit group number 105 (see MIL-PRF-38535, appendix A). Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-90544 DEFENSE SUPPLY CENTER COLUM

34、BUS COLUMBUS, OHIO 43216-5000 REVISION LEVEL A SHEET 5 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics. Test Symbol Conditions 1/ -55C TC +125C +4.5 V VCC +5.5 V unless otherwise specified Group A subgroups Device type Limits Unit Min Max VIH1RESET, NMI, CK1, WO, B10-B13, B15 .

35、9VCCVIH2All inputs except port A .7VCCPort A, VCC= 5.5 V 4.65 Logical “1” input voltage VIH31/ Port A, VCC= 4.5 V 1, 2, 3 All 3.95 V VIL1RESET, NMI, CK1, WO .1VCCVIL2All inputs except port A .2VCCPort A, VCC= 5.5 V .7 Logical “0” input voltage VIL32/ Port A, VCC= 4.5 V 1, 2, 3 All .5 V VOH2IOH= -7 m

36、A (A0-A15, B10-B12, B15, CK2) 2.4 VOH3IOH= -1.6 mA (B0-B9, B13, B14, P0-P3), WO (open drain) 2.4 VOH4IOH= -6 mA (ST1, ST2) 2.4 Logical “1” output voltage VOH5IOH= -1 mA (A0-A15, B10-B12, B15) when used as an external address/data. 1, 2, 3 All 2.4 V VOL2IOL= +3 mA (A0-A15, B10-B12, B15, CK2) .4 VOL3I

37、OL= +0.5 mA (B0-B9, B13, B14, P0-P3), WO (open drain) .4 VOL4IOL= +1.6 mA (ST1, ST2) .4 Logical “0” output voltage VOL5IOL= +3 mA (A0-A15, B10-B12, B15) when used as an external address/data. 1, 2, 3 All .4 V Tri-state leakage current IOZVSS VIN VCC(WO, Port A) Port B, VCC= 5.5 V 1, 2, 3 All 5 A Inp

38、ut leakage current ILI1VSS VIN VCCVCC= 5.5 V, (I1-I6, D0-D7, CK1, RESET, EXM, EI) 3/ 1, 2, 3 All -2 +2 A Input pullup current IIL2VIN= 0, (I0, I7, RDY/HLD, EXUI), VCC= 5.5 V 3/ 1, 2, 3 All -3 50 A Port B12 pulldown during reset IIL3VIN= VCC, Port B12, VCC= 5.5 V 1, 2, 3 All 1 7 mA See footnotes at e

39、nd of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-90544 DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43216-5000 REVISION LEVEL A SHEET 6 DSCC FORM 2234 APR 97 TABLE I. Electrical performance chara

40、cteristics - Continued. Test Symbol Conditions 1/ -55C TC +125C +4.5 V VCC +5.5 V unless otherwise specified Group A subgroups Device type Limits Unit Min Max RAM keep alive voltage VRAMTest duration = 100 ms 1, 2, 3 All 2.5 V Supply current dynamic ICC1FIN= 20 MHz, RESET = VSSIOH= 0 mA, IOL= 0 mA V

41、CC= 5.5 V 1, 2, 3 All 55 mA IDLE mode current ICC2FIN= 20 MHz, external clock 1, 2, 3 All 3.5 mA HALT mode current ICC3NMI = 20 MHz, external clock 1, 2, 3 All 2 mA Input/output capacitance CI/Oftest = 1.0 MHz, I/O pin to GND See 4.4.1c 4/ 4 All 20 pF Input capacitance CIftest = 1.0 MHz, Input pin t

42、o GND See 4.4.1c 4/ 4 All 10 pF Functional tests See 4.4.1b 7, 8 All Operating frequency fC5/ 9, 10, 11 All 2 20 MHz Clock period tC1See figure 4. (Write cycle) 5/ 9, 10, 11 All 50 ns Timing cycle tCSee figure 4. (Write cycle) 5/ 9, 10, 11 All 100 ns ALE pulse width tLLSee figure 4. (Write cycle and

43、 Read cycle) 6/ 9, 10, 11 All 41 ns Address valid to ALE falling edge tSTSee figure 4. (Write cycle and Read cycle) 6/ 9, 10, 11 All 18 ns Wait state period tWAIT5/ 9, 10, 11 All 100 ns External microwire/plus CLK input frequency fMW6/ 9, 10, 11 All 1.25 MHz External UART clock input frequency fU5/

44、9, 10, 11 All 2.5 MHz CK2 delay from CK1 tDC1C2See figure 4. (Write cycle) 6/ 9, 10, 11 All 55 ns See footnotes at end of table. Provided by IHSNot for ResaleNo reproduction or networking permitted without license from IHS-,-,-STANDARD MICROCIRCUIT DRAWING SIZE A 5962-90544 DEFENSE SUPPLY CENTER COL

45、UMBUS COLUMBUS, OHIO 43216-5000 REVISION LEVEL A SHEET 7 DSCC FORM 2234 APR 97 TABLE I. Electrical performance characteristics - Continued. Test Symbol Conditions 1/ -55C TC +125C +4.5 V VCC +5.5 V unless otherwise specified Group A subgroups Device type Limits Unit Min Max ALE falling edge to RD fa

46、lling edge tARRSee figure 4. (Read cycle) 6/ 9, 10, 11 All 20 ns RD pulse width tRWSee figure 4. (Read cycle) 6/ 9, 10, 11 All 140 ns Data hold after rising edge of RD tDRSee figure 4. (Read cycle) 6/ 9, 10, 11 All 0 60 ns RD falling edge to data in valid tRDSee figure 4. (Read cycle) 6/ 9, 10, 11 A

47、ll 85 ns RD rising edge to address valid tRDASee figure 4. (Read cycle) 6/ 9, 10, 11 All 85 ns Address hold from ALE falling edge tVPSee figure 4. (Write cycle and Read cycle) 6/ 9, 10, 11 All 20 ns ALE trailing edge to WR falling edge tARWSee figure 4. (Write cycle) 6/ 9, 10, 11 All 45 ns WR pulse

48、width tWWSee figure 4. (Write cycle) 6/ 9, 10, 11 All 160 ns Data hold after trailing edge of WR tHWSee figure 4. (Write cycle) 6/ 9, 10, 11 All 20 ns Data valid before rising edge of WR tVSee figure 4. (Write cycle) 6/ 9, 10, 11 All 145 ns Falling edge of ALE to falling edge of RDY tDARSee figure 4

49、. (Ready mode timing) 6/ 9, 10, 11 All 75 ns RDY pulse width tRWPSee figure 4. (Ready mode timing) 6/ 9, 10, 11 All 100 ns Falling edge of HLD to rising edge of ALE tSALESee figure 4. (Hold mode timing) 6/ 9, 10, 11 All 115 ns HLD pulse width tHWPSee figure 4. (Hold mode timing) 6/ 9, 10, 11 All 110 ns Rising edge